mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-21 11:47:02 +07:00
Qualcomm ARM64 Updates for v5.1
* Add MSM8998 RPMCC, I2C, and USB related nodes * Add MSM8996 rpmpd node * Fix typo in MSM8996 pin definitions * Disable MSM8996 VFE smmu to fix security violation * Add I2C, SPI, rpmcc, uart, and WCN3990 wlan nodes on QCS404 * Enable SDCC1 HS400 support on QCS404 * Add a multitude of nodes on SDM845: SD, UFS, USB, LPASS, SCM, QSPI, PDC, DPU, videocc, GPU, RPMh bus interconnect, WCN3990 WLAN * Add gpio ranges to SDM845 TLMM * Fix regulator load on sdcard on MSM8998-mtp board -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJcV5TZAAoJEFKiBbHx2RXVWnEP/2bGKgHubS0ADcn8SAJwM7K0 sIKHi9nuL4HW2JGqREjGSTkoXMbHWOgKsyZPyPYP8lCr/L5TJhkrq68Dmh1NWq0N HmgteyH9xBPDjGSdjJixB7REaW0mfdz97FComr+bEAAnqqKinILXIPK9RlYNS7Dh AKOaFevoFgwqrx3maKkWszJ0hu9UyHot/T9OfOJSNEab2SaOPjAwqvYncCVm7GGY uWihZo+kIqF4r3wzXP3xIIAeR/uTm61FbivWH16avhRUZz1UoZpQFlkZTT9eGg9o 09m1bdJrdEInBi+YUc/3zwhQg31mTadcvzmCH/Dz68OkrFEU7kSHy26gIVEfZ0uR WWXxw/xhk+o0Ob0apPjltg6f2UuPEoXvkoL5XM4xUBT2kOeDU9R13POEfJO4WU9T mCFVu/eMYIvxv+zpEK1JRmhMY/T+tO7Nnz+OFF0W4TrjkbEPQJWIjYDTWfheV7Zu hUHHT6nuSXwporSH6IlV9twkgpqw12BekTUp4BiN2VoTH7AgcedSqu/r2n5tKB6z 2kNLpqI8qROvsHR3kEVou1s92rjAhTPSxiuSov/nMSrdUfkU1G39PqmU8mBskp3y WoGiaytTta56lpmjcvDF7O/PeoUdtgct42XAwC4w4ceJsguCbfH8gXf/F2lCsQuy WYNmwzOiN1zrQZmu4mmX =uk+h -----END PGP SIGNATURE----- Merge tag 'qcom-arm64-for-5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux into arm/dt Qualcomm ARM64 Updates for v5.1 * Add MSM8998 RPMCC, I2C, and USB related nodes * Add MSM8996 rpmpd node * Fix typo in MSM8996 pin definitions * Disable MSM8996 VFE smmu to fix security violation * Add I2C, SPI, rpmcc, uart, and WCN3990 wlan nodes on QCS404 * Enable SDCC1 HS400 support on QCS404 * Add a multitude of nodes on SDM845: SD, UFS, USB, LPASS, SCM, QSPI, PDC, DPU, videocc, GPU, RPMh bus interconnect, WCN3990 WLAN * Add gpio ranges to SDM845 TLMM * Fix regulator load on sdcard on MSM8998-mtp board * tag 'qcom-arm64-for-5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux: (41 commits) arm64: dts: sdm845: Add interconnect provider DT nodes arm64: dts: qcom: msm8996: Disabled VFE SMMU arm64: dts: qcom: qcs404: Add rpmcc node arm64: dts: qcom: msm8998: Add rpmcc node arm64: dts: qcom: msm8998: Add USB-related nodes arm64: dts: qcom: qcs404: Add QUP I2C and SPI nodes arm64: dts: qcom: qcs404: Define remaining UARTs arm64: dts: qcom: qcs404: Specify pinctrl state for UART arm64: dts: qcom: sdm845: Fix lpasscc reg arm64: dts: qcom: sdm845: Remove the duplicate header inclusion arm64: dts: qcom: sdm845: Add reserve-memory nodes arm64: dts: qcom: sdm845: Add gpio-ranges to TLMM node arm64: dts: qcom: sdm845: Extend ranges and describe DMA space arm64: dts: qcom: sdm845: Increase address and size cells for soc arm64: dts: sdm845: Add rpmh powercontroller node arm64: dts: msm8996: Add rpmpd device node arm64: dts: sdm845: Add WCN3990 WLAN module device node arm64: dts: qcom: sdm845: Add PDC Global reset driver node arm64: dts: qcom: sdm845: Add SCM DT node arm64: dts: qcom: sdm845: Fix pcs_misc region address for UNI PHY ... Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
2ab58c853e
@ -644,6 +644,8 @@ l10 {
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l11 {
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regulator-min-microvolt = <1750000>;
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regulator-max-microvolt = <3337000>;
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regulator-allow-set-load;
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regulator-system-load = <200000>;
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};
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l12 {
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@ -139,7 +139,7 @@ pinmux {
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};
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pinconf {
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pins = "gpio4", "gpiio5", "gpio6", "gpio7";
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pins = "gpio4", "gpio5", "gpio6", "gpio7";
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drive-strength = <2>;
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bias-disable;
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};
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@ -306,6 +306,40 @@ rpmcc: qcom,rpmcc {
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#clock-cells = <1>;
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};
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rpmpd: power-controller {
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compatible = "qcom,msm8996-rpmpd";
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#power-domain-cells = <1>;
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operating-points-v2 = <&rpmpd_opp_table>;
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rpmpd_opp_table: opp-table {
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compatible = "operating-points-v2";
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rpmpd_opp1: opp1 {
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opp-level = <1>;
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};
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rpmpd_opp2: opp2 {
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opp-level = <2>;
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};
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rpmpd_opp3: opp3 {
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opp-level = <3>;
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};
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rpmpd_opp4: opp4 {
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opp-level = <4>;
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};
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rpmpd_opp5: opp5 {
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opp-level = <5>;
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};
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rpmpd_opp6: opp6 {
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opp-level = <6>;
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};
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};
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};
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pm8994-regulators {
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compatible = "qcom,rpm-pm8994-regulators";
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@ -404,7 +438,7 @@ tcsr: syscon@7a0000 {
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};
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intc: interrupt-controller@9bc0000 {
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compatible = "arm,gic-v3";
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compatible = "qcom,msm8996-gic-v3", "arm,gic-v3";
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#interrupt-cells = <3>;
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interrupt-controller;
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#redistributor-regions = <1>;
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@ -966,7 +1000,7 @@ vfe_smmu: arm,smmu@da0000 {
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clock-names = "iface",
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"bus";
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#iommu-cells = <1>;
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status = "ok";
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status = "disabled";
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};
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camss: camss@a00000 {
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@ -65,6 +65,13 @@ &blsp2_uart1 {
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status = "okay";
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};
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&qusb2phy {
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status = "okay";
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vdda-pll-supply = <&vreg_l12a_1p8>;
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vdda-phy-dpdm-supply = <&vreg_l24a_3p075>;
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};
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&rpm_requests {
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pm8998-regulators {
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compatible = "qcom,rpm-pm8998-regulators";
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@ -192,6 +199,8 @@ vreg_l20a_2p95: l20 {
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vreg_l21a_2p95: l21 {
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regulator-min-microvolt = <2960000>;
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regulator-max-microvolt = <2960000>;
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regulator-allow-set-load;
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regulator-system-load = <800000>;
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};
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vreg_l22a_2p85: l22 {
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regulator-min-microvolt = <2864000>;
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@ -257,3 +266,18 @@ &sdhc2 {
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pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>;
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pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>;
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};
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&usb3 {
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status = "okay";
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};
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&usb3_dwc3 {
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dr_mode = "host"; /* Force to host until we have Type-C hooked up */
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};
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&usb3phy {
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status = "okay";
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vdda-phy-supply = <&vreg_l1a_0p875>;
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vdda-pll-supply = <&vreg_l2a_1p2>;
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};
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@ -3,6 +3,7 @@
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/qcom,gcc-msm8998.h>
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#include <dt-bindings/clock/qcom,rpmcc.h>
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#include <dt-bindings/gpio/gpio.h>
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/ {
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@ -266,6 +267,11 @@ rpm-glink {
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rpm_requests: rpm-requests {
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compatible = "qcom,rpm-msm8998";
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qcom,glink-channels = "rpm_requests";
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rpmcc: clock-controller {
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compatible = "qcom,rpmcc-msm8998", "qcom,rpmcc";
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#clock-cells = <1>;
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};
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};
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};
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@ -540,6 +546,11 @@ qfprom: qfprom@780000 {
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reg = <0x780000 0x621c>;
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#address-cells = <1>;
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#size-cells = <1>;
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qusb2_hstx_trim: hstx-trim@423a {
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reg = <0x423a 0x1>;
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bits = <0 4>;
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};
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};
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gcc: clock-controller@100000 {
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@ -607,6 +618,93 @@ apcs_glb: mailbox@9820000 {
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#mbox-cells = <1>;
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};
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usb3: usb@a8f8800 {
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compatible = "qcom,msm8998-dwc3", "qcom,dwc3";
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reg = <0x0a8f8800 0x400>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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clocks = <&gcc GCC_CFG_NOC_USB3_AXI_CLK>,
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<&gcc GCC_USB30_MASTER_CLK>,
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<&gcc GCC_AGGRE1_USB3_AXI_CLK>,
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<&gcc GCC_USB30_MOCK_UTMI_CLK>,
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<&gcc GCC_USB30_SLEEP_CLK>;
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clock-names = "cfg_noc", "core", "iface", "mock_utmi",
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"sleep";
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assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
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<&gcc GCC_USB30_MASTER_CLK>;
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assigned-clock-rates = <19200000>, <120000000>;
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interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "hs_phy_irq", "ss_phy_irq";
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power-domains = <&gcc USB_30_GDSC>;
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resets = <&gcc GCC_USB_30_BCR>;
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usb3_dwc3: dwc3@a800000 {
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compatible = "snps,dwc3";
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reg = <0x0a800000 0xcd00>;
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interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
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snps,dis_u2_susphy_quirk;
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snps,dis_enblslpm_quirk;
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phys = <&qusb2phy>, <&usb1_ssphy>;
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phy-names = "usb2-phy", "usb3-phy";
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snps,has-lpm-erratum;
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snps,hird-threshold = /bits/ 8 <0x10>;
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};
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};
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usb3phy: phy@c010000 {
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compatible = "qcom,msm8998-qmp-usb3-phy";
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reg = <0x0c010000 0x18c>;
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status = "disabled";
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#clock-cells = <1>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
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<&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
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<&gcc GCC_USB3_CLKREF_CLK>;
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clock-names = "aux", "cfg_ahb", "ref";
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resets = <&gcc GCC_USB3_PHY_BCR>,
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<&gcc GCC_USB3PHY_PHY_BCR>;
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reset-names = "phy", "common";
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usb1_ssphy: lane@c010200 {
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reg = <0xc010200 0x128>,
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<0xc010400 0x200>,
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<0xc010c00 0x20c>,
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<0xc010600 0x128>,
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<0xc010800 0x200>;
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#phy-cells = <0>;
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clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;
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clock-names = "pipe0";
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clock-output-names = "usb3_phy_pipe_clk_src";
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};
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};
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qusb2phy: phy@c012000 {
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compatible = "qcom,msm8998-qusb2-phy";
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reg = <0x0c012000 0x2a8>;
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status = "disabled";
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#phy-cells = <0>;
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clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
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<&gcc GCC_RX1_USB2_CLKREF_CLK>;
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clock-names = "cfg_ahb", "ref";
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resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
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nvmem-cells = <&qusb2_hstx_trim>;
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};
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sdhc2: sdhci@c0a4900 {
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compatible = "qcom,sdhci-msm-v4";
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reg = <0xc0a4900 0x314>, <0xc0a4000 0x800>;
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@ -624,6 +722,186 @@ sdhc2: sdhci@c0a4900 {
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status = "disabled";
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};
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blsp1_i2c1: i2c@c175000 {
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compatible = "qcom,i2c-qup-v2.2.1";
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reg = <0x0c175000 0x600>;
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interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
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<&gcc GCC_BLSP1_AHB_CLK>;
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clock-names = "core", "iface";
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clock-frequency = <400000>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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blsp1_i2c2: i2c@c176000 {
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compatible = "qcom,i2c-qup-v2.2.1";
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reg = <0x0c176000 0x600>;
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interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
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<&gcc GCC_BLSP1_AHB_CLK>;
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clock-names = "core", "iface";
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clock-frequency = <400000>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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blsp1_i2c3: i2c@c177000 {
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compatible = "qcom,i2c-qup-v2.2.1";
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reg = <0x0c177000 0x600>;
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interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
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<&gcc GCC_BLSP1_AHB_CLK>;
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clock-names = "core", "iface";
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clock-frequency = <400000>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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blsp1_i2c4: i2c@c178000 {
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compatible = "qcom,i2c-qup-v2.2.1";
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reg = <0x0c178000 0x600>;
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interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
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<&gcc GCC_BLSP1_AHB_CLK>;
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clock-names = "core", "iface";
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clock-frequency = <400000>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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blsp1_i2c5: i2c@c179000 {
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compatible = "qcom,i2c-qup-v2.2.1";
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reg = <0x0c179000 0x600>;
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interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
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<&gcc GCC_BLSP1_AHB_CLK>;
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clock-names = "core", "iface";
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clock-frequency = <400000>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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||||
};
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blsp1_i2c6: i2c@c17a000 {
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compatible = "qcom,i2c-qup-v2.2.1";
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reg = <0x0c17a000 0x600>;
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interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
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||||
clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
|
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<&gcc GCC_BLSP1_AHB_CLK>;
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clock-names = "core", "iface";
|
||||
clock-frequency = <400000>;
|
||||
|
||||
status = "disabled";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
blsp2_i2c0: i2c@c1b5000 {
|
||||
compatible = "qcom,i2c-qup-v2.2.1";
|
||||
reg = <0x0c1b5000 0x600>;
|
||||
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>,
|
||||
<&gcc GCC_BLSP2_AHB_CLK>;
|
||||
clock-names = "core", "iface";
|
||||
clock-frequency = <400000>;
|
||||
|
||||
status = "disabled";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
blsp2_i2c1: i2c@c1b6000 {
|
||||
compatible = "qcom,i2c-qup-v2.2.1";
|
||||
reg = <0x0c1b6000 0x600>;
|
||||
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>,
|
||||
<&gcc GCC_BLSP2_AHB_CLK>;
|
||||
clock-names = "core", "iface";
|
||||
clock-frequency = <400000>;
|
||||
|
||||
status = "disabled";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
blsp2_i2c2: i2c@c1b7000 {
|
||||
compatible = "qcom,i2c-qup-v2.2.1";
|
||||
reg = <0x0c1b7000 0x600>;
|
||||
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>,
|
||||
<&gcc GCC_BLSP2_AHB_CLK>;
|
||||
clock-names = "core", "iface";
|
||||
clock-frequency = <400000>;
|
||||
|
||||
status = "disabled";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
blsp2_i2c3: i2c@c1b8000 {
|
||||
compatible = "qcom,i2c-qup-v2.2.1";
|
||||
reg = <0x0c1b8000 0x600>;
|
||||
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>,
|
||||
<&gcc GCC_BLSP2_AHB_CLK>;
|
||||
clock-names = "core", "iface";
|
||||
clock-frequency = <400000>;
|
||||
|
||||
status = "disabled";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
blsp2_i2c4: i2c@c1b9000 {
|
||||
compatible = "qcom,i2c-qup-v2.2.1";
|
||||
reg = <0x0c1b9000 0x600>;
|
||||
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>,
|
||||
<&gcc GCC_BLSP2_AHB_CLK>;
|
||||
clock-names = "core", "iface";
|
||||
clock-frequency = <400000>;
|
||||
|
||||
status = "disabled";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
blsp2_i2c5: i2c@c1ba000 {
|
||||
compatible = "qcom,i2c-qup-v2.2.1";
|
||||
reg = <0x0c175000 0x600>;
|
||||
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>,
|
||||
<&gcc GCC_BLSP2_AHB_CLK>;
|
||||
clock-names = "core", "iface";
|
||||
clock-frequency = <400000>;
|
||||
|
||||
status = "disabled";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
blsp2_uart1: serial@c1b0000 {
|
||||
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
|
||||
reg = <0xc1b0000 0x1000>;
|
||||
|
||||
@ -32,6 +32,12 @@ pwrkey {
|
||||
bias-pull-up;
|
||||
linux,code = <KEY_POWER>;
|
||||
};
|
||||
|
||||
watchdog {
|
||||
compatible = "qcom,pm8916-wdt";
|
||||
interrupts = <0x0 0x8 6 IRQ_TYPE_EDGE_RISING>;
|
||||
timeout-sec = <60>;
|
||||
};
|
||||
};
|
||||
|
||||
pm8916_gpios: gpios@c000 {
|
||||
|
||||
@ -3,6 +3,32 @@
|
||||
|
||||
#include <dt-bindings/spmi/spmi.h>
|
||||
#include <dt-bindings/input/linux-event-codes.h>
|
||||
#include <dt-bindings/iio/qcom,spmi-vadc.h>
|
||||
#include <dt-bindings/thermal/thermal.h>
|
||||
|
||||
/ {
|
||||
thermal-zones {
|
||||
pms405 {
|
||||
polling-delay-passive = <250>;
|
||||
polling-delay = <1000>;
|
||||
|
||||
thermal-sensors = <&pms405_temp>;
|
||||
|
||||
trips {
|
||||
pms405_alert0: pms405-alert0 {
|
||||
temperature = <105000>;
|
||||
hysteresis = <2000>;
|
||||
type = "passive";
|
||||
};
|
||||
pms405_crit: pms405-crit {
|
||||
temperature = <125000>;
|
||||
hysteresis = <2000>;
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&spmi_bus {
|
||||
pms405_0: pms405@0 {
|
||||
@ -45,6 +71,59 @@ pwrkey {
|
||||
};
|
||||
};
|
||||
|
||||
pms405_temp: temp-alarm@2400 {
|
||||
compatible = "qcom,spmi-temp-alarm";
|
||||
reg = <0x2400>;
|
||||
interrupts = <0 0x24 0 IRQ_TYPE_EDGE_RISING>;
|
||||
io-channels = <&pms405_adc ADC5_DIE_TEMP>;
|
||||
io-channel-names = "thermal";
|
||||
#thermal-sensor-cells = <0>;
|
||||
};
|
||||
|
||||
pms405_adc: adc@3100 {
|
||||
compatible = "qcom,pms405-adc", "qcom,spmi-adc-rev2";
|
||||
reg = <0x3100>;
|
||||
interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
#io-channel-cells = <1>;
|
||||
|
||||
ref_gnd {
|
||||
reg = <ADC5_REF_GND>;
|
||||
qcom,pre-scaling = <1 1>;
|
||||
};
|
||||
|
||||
vref_1p25 {
|
||||
reg = <ADC5_1P25VREF>;
|
||||
qcom,pre-scaling = <1 1>;
|
||||
};
|
||||
|
||||
vph_pwr {
|
||||
reg = <ADC5_VPH_PWR>;
|
||||
qcom,pre-scaling = <1 3>;
|
||||
};
|
||||
|
||||
die_temp {
|
||||
reg = <ADC5_DIE_TEMP>;
|
||||
qcom,pre-scaling = <1 1>;
|
||||
};
|
||||
|
||||
xo_therm_100k_pu {
|
||||
reg = <ADC5_XO_THERM_100K_PU>;
|
||||
qcom,pre-scaling = <1 1>;
|
||||
};
|
||||
|
||||
amux_thm1_100k_pu {
|
||||
reg = <ADC5_AMUX_THM1_100K_PU>;
|
||||
qcom,pre-scaling = <1 1>;
|
||||
};
|
||||
|
||||
amux_thm3_100k_pu {
|
||||
reg = <ADC5_AMUX_THM3_100K_PU>;
|
||||
qcom,pre-scaling = <1 1>;
|
||||
};
|
||||
};
|
||||
|
||||
rtc@6000 {
|
||||
compatible = "qcom,pm8941-rtc";
|
||||
reg = <0x6000>;
|
||||
|
||||
@ -127,6 +127,7 @@ &sdcc1 {
|
||||
status = "ok";
|
||||
|
||||
mmc-ddr-1_8v;
|
||||
mmc-hs400-1_8v;
|
||||
bus-width = <8>;
|
||||
non-removable;
|
||||
|
||||
@ -186,3 +187,21 @@ rclk {
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&wifi {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* PINCTRL - additions to nodes defined in qcs404.dtsi */
|
||||
|
||||
&blsp1_uart2_default {
|
||||
rx {
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
tx {
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
@ -3,6 +3,7 @@
|
||||
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-qcs404.h>
|
||||
#include <dt-bindings/clock/qcom,rpmcc.h>
|
||||
|
||||
/ {
|
||||
interrupt-parent = <&intc>;
|
||||
@ -224,6 +225,11 @@ rpm-glink {
|
||||
rpm_requests: glink-channel {
|
||||
compatible = "qcom,rpm-qcs404";
|
||||
qcom,glink-channels = "rpm_requests";
|
||||
|
||||
rpmcc: clock-controller {
|
||||
compatible = "qcom,rpmcc-qcs404";
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@ -272,6 +278,105 @@ tlmm: pinctrl@1000000 {
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
|
||||
blsp1_i2c0_default: blsp1-i2c0-default {
|
||||
pins = "gpio32", "gpio33";
|
||||
function = "blsp_i2c0";
|
||||
};
|
||||
|
||||
blsp1_i2c1_default: blsp1-i2c1-default {
|
||||
pins = "gpio24", "gpio25";
|
||||
function = "blsp_i2c1";
|
||||
};
|
||||
|
||||
blsp1_i2c2_default: blsp1-i2c2-default {
|
||||
sda {
|
||||
pins = "gpio19";
|
||||
function = "blsp_i2c_sda_a2";
|
||||
};
|
||||
|
||||
scl {
|
||||
pins = "gpio20";
|
||||
function = "blsp_i2c_scl_a2";
|
||||
};
|
||||
};
|
||||
|
||||
blsp1_i2c3_default: blsp1-i2c3-default {
|
||||
pins = "gpio84", "gpio85";
|
||||
function = "blsp_i2c3";
|
||||
};
|
||||
|
||||
blsp1_i2c4_default: blsp1-i2c4-default {
|
||||
pins = "gpio117", "gpio118";
|
||||
function = "blsp_i2c4";
|
||||
};
|
||||
|
||||
blsp1_uart0_default: blsp1-uart0-default {
|
||||
pins = "gpio30", "gpio31", "gpio32", "gpio33";
|
||||
function = "blsp_uart0";
|
||||
};
|
||||
|
||||
blsp1_uart1_default: blsp1-uart1-default {
|
||||
pins = "gpio22", "gpio23";
|
||||
function = "blsp_uart1";
|
||||
};
|
||||
|
||||
blsp1_uart2_default: blsp1-uart2-default {
|
||||
rx {
|
||||
pins = "gpio18";
|
||||
function = "blsp_uart_rx_a2";
|
||||
};
|
||||
|
||||
tx {
|
||||
pins = "gpio17";
|
||||
function = "blsp_uart_tx_a2";
|
||||
};
|
||||
};
|
||||
|
||||
blsp1_uart3_default: blsp1-uart3-default {
|
||||
pins = "gpio82", "gpio83", "gpio84", "gpio85";
|
||||
function = "blsp_uart3";
|
||||
};
|
||||
|
||||
blsp2_i2c0_default: blsp2-i2c0-default {
|
||||
pins = "gpio28", "gpio29";
|
||||
function = "blsp_i2c5";
|
||||
};
|
||||
|
||||
blsp1_spi0_default: blsp1-spi0-default {
|
||||
pins = "gpio30", "gpio31", "gpio32", "gpio33";
|
||||
function = "blsp_spi0";
|
||||
};
|
||||
|
||||
blsp1_spi1_default: blsp1-spi1-default {
|
||||
pins = "gpio22", "gpio23", "gpio24", "gpio25";
|
||||
function = "blsp_spi1";
|
||||
};
|
||||
|
||||
blsp1_spi2_default: blsp1-spi2-default {
|
||||
pins = "gpio17", "gpio18", "gpio19", "gpio20";
|
||||
function = "blsp_spi2";
|
||||
};
|
||||
|
||||
blsp1_spi3_default: blsp1-spi3-default {
|
||||
pins = "gpio82", "gpio83", "gpio84", "gpio85";
|
||||
function = "blsp_spi3";
|
||||
};
|
||||
|
||||
blsp1_spi4_default: blsp1-spi4-default {
|
||||
pins = "gpio37", "gpio38", "gpio117", "gpio118";
|
||||
function = "blsp_spi4";
|
||||
};
|
||||
|
||||
blsp2_spi0_default: blsp2-spi0-default {
|
||||
pins = "gpio26", "gpio27", "gpio28", "gpio29";
|
||||
function = "blsp_spi5";
|
||||
};
|
||||
|
||||
blsp2_uart0_default: blsp2-uart0-default {
|
||||
pins = "gpio26", "gpio27", "gpio28", "gpio29";
|
||||
function = "blsp_uart5";
|
||||
};
|
||||
};
|
||||
|
||||
gcc: clock-controller@1800000 {
|
||||
@ -335,6 +440,32 @@ blsp1_dma: dma@7884000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
blsp1_uart0: serial@78af000 {
|
||||
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
|
||||
reg = <0x078af000 0x200>;
|
||||
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&gcc GCC_BLSP1_UART0_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
|
||||
clock-names = "core", "iface";
|
||||
dmas = <&blsp1_dma 1>, <&blsp1_dma 0>;
|
||||
dma-names = "rx", "tx";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&blsp1_uart0_default>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
blsp1_uart1: serial@78b0000 {
|
||||
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
|
||||
reg = <0x078b0000 0x200>;
|
||||
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
|
||||
clock-names = "core", "iface";
|
||||
dmas = <&blsp1_dma 3>, <&blsp1_dma 2>;
|
||||
dma-names = "rx", "tx";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&blsp1_uart1_default>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
blsp1_uart2: serial@78b1000 {
|
||||
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
|
||||
reg = <0x078b1000 0x200>;
|
||||
@ -343,9 +474,237 @@ blsp1_uart2: serial@78b1000 {
|
||||
clock-names = "core", "iface";
|
||||
dmas = <&blsp1_dma 5>, <&blsp1_dma 4>;
|
||||
dma-names = "rx", "tx";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&blsp1_uart2_default>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
wifi: wifi@a000000 {
|
||||
compatible = "qcom,wcn3990-wifi";
|
||||
reg = <0xa000000 0x800000>;
|
||||
reg-names = "membase";
|
||||
memory-region = <&wlan_msa_mem>;
|
||||
interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
blsp1_uart3: serial@78b2000 {
|
||||
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
|
||||
reg = <0x078b2000 0x200>;
|
||||
interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
|
||||
clock-names = "core", "iface";
|
||||
dmas = <&blsp1_dma 7>, <&blsp1_dma 6>;
|
||||
dma-names = "rx", "tx";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&blsp1_uart3_default>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
blsp1_i2c0: i2c@78b5000 {
|
||||
compatible = "qcom,i2c-qup-v2.2.1";
|
||||
reg = <0x078b5000 0x600>;
|
||||
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
|
||||
<&gcc GCC_BLSP1_QUP0_I2C_APPS_CLK>;
|
||||
clock-names = "iface", "core";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&blsp1_i2c0_default>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
blsp1_spi0: spi@78b5000 {
|
||||
compatible = "qcom,spi-qup-v2.2.1";
|
||||
reg = <0x078b5000 0x600>;
|
||||
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
|
||||
<&gcc GCC_BLSP1_QUP0_SPI_APPS_CLK>;
|
||||
clock-names = "iface", "core";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&blsp1_spi0_default>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
blsp1_i2c1: i2c@78b6000 {
|
||||
compatible = "qcom,i2c-qup-v2.2.1";
|
||||
reg = <0x078b6000 0x600>;
|
||||
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
|
||||
<&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>;
|
||||
clock-names = "iface", "core";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&blsp1_i2c1_default>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
blsp1_spi1: spi@78b6000 {
|
||||
compatible = "qcom,spi-qup-v2.2.1";
|
||||
reg = <0x078b6000 0x600>;
|
||||
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
|
||||
<&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>;
|
||||
clock-names = "iface", "core";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&blsp1_spi1_default>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
blsp1_i2c2: i2c@78b7000 {
|
||||
compatible = "qcom,i2c-qup-v2.2.1";
|
||||
reg = <0x078b7000 0x600>;
|
||||
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
|
||||
<&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
|
||||
clock-names = "iface", "core";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&blsp1_i2c2_default>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
blsp1_spi2: spi@78b7000 {
|
||||
compatible = "qcom,spi-qup-v2.2.1";
|
||||
reg = <0x078b7000 0x600>;
|
||||
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
|
||||
<&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>;
|
||||
clock-names = "iface", "core";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&blsp1_spi2_default>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
blsp1_i2c3: i2c@78b8000 {
|
||||
compatible = "qcom,i2c-qup-v2.2.1";
|
||||
reg = <0x078b8000 0x600>;
|
||||
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
|
||||
<&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
|
||||
clock-names = "iface", "core";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&blsp1_i2c3_default>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
blsp1_spi3: spi@78b8000 {
|
||||
compatible = "qcom,spi-qup-v2.2.1";
|
||||
reg = <0x078b8000 0x600>;
|
||||
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
|
||||
<&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>;
|
||||
clock-names = "iface", "core";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&blsp1_spi3_default>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
blsp1_i2c4: i2c@78b9000 {
|
||||
compatible = "qcom,i2c-qup-v2.2.1";
|
||||
reg = <0x078b9000 0x600>;
|
||||
interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
|
||||
<&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
|
||||
clock-names = "iface", "core";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&blsp1_i2c4_default>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
blsp1_spi4: spi@78b9000 {
|
||||
compatible = "qcom,spi-qup-v2.2.1";
|
||||
reg = <0x078b9000 0x600>;
|
||||
interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
|
||||
<&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>;
|
||||
clock-names = "iface", "core";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&blsp1_spi4_default>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
blsp2_dma: dma@7ac4000 {
|
||||
compatible = "qcom,bam-v1.7.0";
|
||||
reg = <0x07ac4000 0x17000>;
|
||||
interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&gcc GCC_BLSP2_AHB_CLK>;
|
||||
clock-names = "bam_clk";
|
||||
#dma-cells = <1>;
|
||||
qcom,controlled-remotely = <1>;
|
||||
qcom,ee = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
blsp2_uart0: serial@7aef000 {
|
||||
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
|
||||
reg = <0x07aef000 0x200>;
|
||||
interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&gcc GCC_BLSP2_UART0_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
|
||||
clock-names = "core", "iface";
|
||||
dmas = <&blsp2_dma 1>, <&blsp2_dma 0>;
|
||||
dma-names = "rx", "tx";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&blsp2_uart0_default>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
blsp2_i2c0: i2c@7af5000 {
|
||||
compatible = "qcom,i2c-qup-v2.2.1";
|
||||
reg = <0x07af5000 0x600>;
|
||||
interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&gcc GCC_BLSP2_AHB_CLK>,
|
||||
<&gcc GCC_BLSP2_QUP0_I2C_APPS_CLK>;
|
||||
clock-names = "iface", "core";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&blsp2_i2c0_default>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
blsp2_spi0: spi@7af5000 {
|
||||
compatible = "qcom,spi-qup-v2.2.1";
|
||||
reg = <0x07af5000 0x600>;
|
||||
interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&gcc GCC_BLSP2_AHB_CLK>,
|
||||
<&gcc GCC_BLSP2_QUP0_SPI_APPS_CLK>;
|
||||
clock-names = "iface", "core";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&blsp2_spi0_default>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
intc: interrupt-controller@b000000 {
|
||||
compatible = "qcom,msm-qgic2";
|
||||
interrupt-controller;
|
||||
|
||||
@ -7,6 +7,7 @@
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
|
||||
#include "sdm845.dtsi"
|
||||
|
||||
@ -346,7 +347,9 @@ vreg_s3c_0p6: smps3 {
|
||||
&gcc {
|
||||
protected-clocks = <GCC_QSPI_CORE_CLK>,
|
||||
<GCC_QSPI_CORE_CLK_SRC>,
|
||||
<GCC_QSPI_CNOC_PERIPH_AHB_CLK>;
|
||||
<GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
|
||||
<GCC_LPASS_Q6_AXI_CLK>,
|
||||
<GCC_LPASS_SWAY_CLK>;
|
||||
};
|
||||
|
||||
&i2c10 {
|
||||
@ -358,14 +361,36 @@ &qupv3_id_1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tlmm {
|
||||
gpio-reserved-ranges = <0 4>, <81 4>;
|
||||
&sdhc_2 {
|
||||
status = "okay";
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdc2_clk &sdc2_cmd &sdc2_data &sd_card_det_n>;
|
||||
|
||||
vmmc-supply = <&vreg_l21a_2p95>;
|
||||
vqmmc-supply = <&vddpx_2>;
|
||||
|
||||
cd-gpios = <&tlmm 126 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
&uart9 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ufs_mem_hc {
|
||||
status = "okay";
|
||||
|
||||
vcc-supply = <&vreg_l20a_2p95>;
|
||||
vcc-max-microamp = <600000>;
|
||||
};
|
||||
|
||||
&ufs_mem_phy {
|
||||
status = "okay";
|
||||
|
||||
vdda-phy-supply = <&vdda_ufs1_core>;
|
||||
vdda-pll-supply = <&vdda_ufs1_1p2>;
|
||||
};
|
||||
|
||||
&usb_1 {
|
||||
status = "okay";
|
||||
};
|
||||
@ -427,6 +452,14 @@ &usb_2_qmpphy {
|
||||
vdda-pll-supply = <&vdda_usb2_ss_core>;
|
||||
};
|
||||
|
||||
&wifi {
|
||||
status = "okay";
|
||||
vdd-0.8-cx-mx-supply = <&vreg_l5a_0p8>;
|
||||
vdd-1.8-xo-supply = <&vreg_l7a_1p8>;
|
||||
vdd-1.3-rfa-supply = <&vreg_l17a_1p3>;
|
||||
vdd-3.3-ch0-supply = <&vreg_l25a_3p3>;
|
||||
};
|
||||
|
||||
/* PINCTRL - additions to nodes defined in sdm845.dtsi */
|
||||
|
||||
&qup_i2c10_default {
|
||||
@ -450,3 +483,48 @@ pinconf-rx {
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
&tlmm {
|
||||
gpio-reserved-ranges = <0 4>, <81 4>;
|
||||
|
||||
sdc2_clk: sdc2-clk {
|
||||
pinconf {
|
||||
pins = "sdc2_clk";
|
||||
bias-disable;
|
||||
|
||||
/*
|
||||
* It seems that mmc_test reports errors if drive
|
||||
* strength is not 16 on clk, cmd, and data pins.
|
||||
*/
|
||||
drive-strength = <16>;
|
||||
};
|
||||
};
|
||||
|
||||
sdc2_cmd: sdc2-cmd {
|
||||
pinconf {
|
||||
pins = "sdc2_cmd";
|
||||
bias-pull-up;
|
||||
drive-strength = <16>;
|
||||
};
|
||||
};
|
||||
|
||||
sdc2_data: sdc2-data {
|
||||
pinconf {
|
||||
pins = "sdc2_data";
|
||||
bias-pull-up;
|
||||
drive-strength = <16>;
|
||||
};
|
||||
};
|
||||
|
||||
sd_card_det_n: sd-card-det-n {
|
||||
pinmux {
|
||||
pins = "gpio126";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
pinconf {
|
||||
pins = "gpio126";
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue
Block a user