Adds support for Tegra210, which allows the SMMU to be used on this new
SoC generation.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2
iQIcBAABCAAGBQJVzfK2AAoJEN0jrNd/PrOhR2cP/RYqGcXQMbHPnDY4Za7dXtGW
nG+NFNLBdVsyPk7ol9p1WRNKVkWSObJ4RN669CyRbk6JvBf7xYXSp9i0mh7FSMow
WBCk3sraN8L8txXOYMnut2+b/3xNGrVxgh8RmQ4aRZY+UDMXlX+cAyuEBhGTDR1G
N0KhIO3SYDGRMCJ6w3sV0lT+Ac0I5+iG94kRxoqyaO/mi/EA3I3rOaYaiHujCQxJ
1LrQAY35NTC0Pwsdqq7ivPEHkL9Ki4/rvPnVocZea4H+MSZ/gTSHpe7rPOF4vGPS
imERpyN4eJwZlQnOC8ism3TQPHGiKux8xEtNBV76IHmB27O7A+cJhQWFzdKGQpGB
tMcqyr5aJGFwJ2Rba0NKo61xyIqXgE4pW85DKAuN6cnWlZ5+J8Mjv5788tMShwMI
aMPm3na6gtiH2zhkE0MEt0qizDM9BUnlF3be5gVQejr4jNDOFe62opvyzq42iO2z
8NQ9amgMQXfwql7Wr6T+Fa5VgTPRS2VEjf7knJaYFXVih5nP5SGK6fvkLIb2MN07
DKZ5rbrXBxx4kpZiftnE1wPwQC6EHg5FT+4MDW877Lw1dbDllM179cOgRJowLo0G
zkPOvHKiQFLx/32MZJfXp5vbDeX11Q2LOgNc+/D46dSm7ElnuEXylnc4vOuvFDU9
AkuPLVT4wos1SsvtL8v6
=H73u
-----END PGP SIGNATURE-----
Merge tag 'tegra-for-4.3-memory' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/drivers
ARM: tegra: Memory controller updates for v4.3-rc1
Adds support for Tegra210, which allows the SMMU to be used on this new
SoC generation.
* tag 'tegra-for-4.3-memory' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
memory: tegra: Add Tegra210 support
memory: tegra: Add support for a variable-size client ID bitfield
memory: tegra: Expose supported rates via debugfs
Signed-off-by: Olof Johansson <olof@lixom.net>
This adds CPU frequency scaling support for Tegra124.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2
iQIcBAABCAAGBQJVzfGWAAoJEN0jrNd/PrOhHAkQAJZdh0UBT+El2iBdfpNYKOOT
qwr22GBNN5lKcOoWm03te8VeTsZxVZ3TJTXp2BRfDRm8gGTufXH267dCLckfgcZd
VdYIMQ4Eh18m2SZK2mPksaZvh9qrsGsOdeL4CY6rPmXYGbTU1EWWXQ02tnNfV2sw
BD2G+X14KsNmIGCmoPC5SeRsg8tBpkFxQqzz1/R4NLOMMpPJ/xkAo7K1JVU8+bYo
O1e6lUEIIyj/cBpdF0u0bSPiSmJO5HY6O5XKU4VyjWm+V0Tz2BKRcWJozft/y+yH
j3RSvM5uhVSQTfpQqwjUWFr8kgsooLQhVqaaT0NSS/whFN8fCbs+yT5GHKNrymFD
Z6qkEmQdUM6vhf7IgKv0cSBVLwqQ+q8zPiOxFBFZ6boJpzroEds+y4+nGJVikFn9
3Uzy1j7M0xjH9/Qsi5+qz0efvfpp5DAAEnxJycC/1nLbi5yd11rRY/bMchtNkqDC
39zy63cwhM8ls2/6OT1eknS/4OSjMURuX192KY480biujwQpVEBrcgv+3VIK3iLr
XnccvMzO4GHUA0TzvnHGG9I2uauO/t6d2sPGGCJZbASVJ8ZpG1sxSgO6Nq7/nDbs
NFpsIN9+zMhAOvZV8b0/Ed3Ehzh1ZGrb8gkZ3MVjdGjg+OT1kmaAHtjCRHpBJwxe
O0mU6V3E3QcMI0PPuoU1
=TghG
-----END PGP SIGNATURE-----
Merge tag 'tegra-for-4.3-cpufreq' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/drivers
ARM: tegra: CPU frequency scaling for v4.3-rc1
This adds CPU frequency scaling support for Tegra124.
* tag 'tegra-for-4.3-cpufreq' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
cpufreq: Add cpufreq driver for Tegra124
cpufreq: tegra: Rename tegra-cpufreq to tegra20-cpufreq
cpufreq: tegra124: Add device tree bindings
Signed-off-by: Olof Johansson <olof@lixom.net>
This contains a bit more of Tegra210 support, which is shaping up pretty
nicely. Other than that there are a couple of cleanup patches here, too.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2
iQIcBAABCAAGBQJVzfFHAAoJEN0jrNd/PrOhvF0QAK6TZ/mSuK5sWsF2LWY/yCk1
sbS5NpOkP0Js+39CZFfRJXOeAlopyeA8UEAnmobyUIprYQWoK0iE4y0q+Iy6nn72
tZdsZlz87dUM/CYjT+AyPK7aUILB1s3dLjul+Lua5mAhUCwju+HHdHgm6OI5c/GN
4W5T3ysfF7aDy+o8a85YLPaPwhP36yTy6x3cx9lLvmFIKVgwWIn+cuOJOpaziy3W
frh7v26Vjl5Ja8Ml1LZd5TQhWJBzsSAIr81PJnk8nNliKspASw6a+hWvTkd2vMll
4qN9sekg55xeGk9lDJeesOmc2dmE4m1r0kg1aVcnpno/oy1k3VicHXfrI/AoN96w
cwRPHwAny9V5wW9vR5WojyGEuGojr/tbHVPGVMAhv+nw1Vod2A9iO5yNJyOs5a96
G6+YZNWwKJRecvQu+3SbhKKjSJoe66Ac36qTlTYjCiwVdcBceBMiqHl4sEslxLd9
pzrI6xjBlyqBcxdBeunKi6CoSeXRVv8HqO7lKLSBDMeMJQD3utYBhGgR59B0sI6P
sSyzPmPpv91YuXXJ2xhtRkFmBrW3KmN9ot8JgsfmzCxgef3zUa6vxOVrSGIbmWGB
qzB4V0X8GOVoZNejFLx+LGLHXeW6wdOJ3n6vqvZjaFTTeYz9kDm9Y3EUBXxX6hzs
ULBUWV18Nh/YDUIZIaV8
=xo46
-----END PGP SIGNATURE-----
Merge tag 'tegra-for-4.3-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/drivers
ARM: tegra: Core SoC changes for v4.3-rc1
This contains a bit more of Tegra210 support, which is shaping up pretty
nicely. Other than that there are a couple of cleanup patches here, too.
* tag 'tegra-for-4.3-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
ARM: tegra: cpuidle: implement cpuidle_state.enter_freeze()
ARM: tegra: Disable cpuidle if PSCI is available
soc/tegra: pmc: Use existing pclk reference
soc/tegra: pmc: Remove unnecessary return statement
soc: tegra: Remove redundant $(CONFIG_ARCH_TEGRA) in Makefile
soc/tegra: fuse: Add spare bit offset for Tegra210
soc/tegra: fuse: Add spare bit offset for Tegra124
soc/tegra: fuse: Add spare bit offset for Tegra114
soc/tegra: fuse: Rename core_* to soc_*
soc/tegra: fuse: Add Tegra210 support
soc/tegra: fuse: Unify Tegra20 and Tegra30 drivers
soc/tegra: fuse: Restrict legacy code to 32-bit ARM
soc/tegra: pmc: Add Tegra210 support
soc/tegra: pmc: Restrict legacy code to 32-bit ARM
soc/tegra: pmc: Avoid usage of uninitialized variable
soc/tegra: Add Tegra210 support
soc/tegra: Add Tegra132 support
Signed-off-by: Olof Johansson <olof@lixom.net>
- moved the DT reset binding includes from
include/dt-bindings/reset-controller to include/dt-bindings/reset
- new driver for LPC18xx Reset Generation Unit (RGU)
- of_device_id array in the STi driver changed to const.
- extend SoCFPGA reset driver to support Arria10
- new ath79 reset controller driver for AR71XX/AR9XXX
- new driver for Xilinx Zynq reset controller
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJV0Km0AAoJEFDCiBxwnmDrOUgQAMkd/AF+Kl2cLpU0am/7yDZE
eO4UgnlQ50L3+bXjOdgX0Ge24S6yQRpe66Nj1vpK0lfxzPM+K2/sTfXso0iAhtGd
7OqapeQv+/hlBq2mmPT1smEbDucOFffFmQAq9sV3PbAYgGRn2CD8GYvSoS//0EMm
39KbocTEsuZErf0hmNlhtIwa6vg+Q9H1eWN0A3CZrGOy3zMMGEypyKOyJznIpBZv
HccpVN4y3D3BTf2HIWa5p9dHueWv5BdmudM2IypO3EVXOULhu4Jzqt1Fizu9F+yR
jvxbB96W8gNDRT5c49vFshkVWfNJAkYnKcXISjWUb0bM9V1l5V62R8f4OJWj24rh
GXgT8spdqjze38YYT8VQx7SWXjm6H2aMnrYNMLQsHunJbEbboqCb/JHTTCOrzMSZ
FgHWCp0uodNYo/VGWx8GgMKPwrfYpY8iMtm16WSucPZA/ppx21oD8VLzIY1Bd0CW
JM5oHG4uYB90EFxQS5XJoAxa9HbIlV6UbHdt44bVPcaQGw9ID+j978Djsjalqqf7
uhA+8wVYGcopOcUWJ8ISsMerQqCiJfMwczhwDh0yEd9NshGv76NbycgsVP/4De6f
c8xCEkuADYtWPtaQQakU+l8TfctmrsakNmD5DbkUgoLut+FnkfN1cmHHGnFlI36d
DTaKtOAddWkrWebdpXW1
=GBec
-----END PGP SIGNATURE-----
Merge tag 'reset-for-4.3' of git://git.pengutronix.de/git/pza/linux into next/drivers
Reset controller changes for v4.3
- moved the DT reset binding includes from
include/dt-bindings/reset-controller to include/dt-bindings/reset
- new driver for LPC18xx Reset Generation Unit (RGU)
- of_device_id array in the STi driver changed to const.
- extend SoCFPGA reset driver to support Arria10
- new ath79 reset controller driver for AR71XX/AR9XXX
- new driver for Xilinx Zynq reset controller
* tag 'reset-for-4.3' of git://git.pengutronix.de/git/pza/linux:
reset: reset-zynq: Adding support for Xilinx Zynq reset controller.
docs: dts: Added documentation for Xilinx Zynq Reset Controller bindings.
MIPS: ath79: Add the reset controller to the AR9132 dtsi
reset: Add a driver for the reset controller on the AR71XX/AR9XXX
devicetree: Add bindings for the ATH79 reset controller
reset: socfpga: Update reset-socfpga to read the altr,modrst-offset property
doc: dt: add documentation for lpc1850-rgu reset driver
reset: add driver for lpc18xx rgu
reset: sti: constify of_device_id array
ARM: STi: DT: Move reset controller constants into common location
MAINTAINERS: add include/dt-bindings/reset path to reset controller entry
Signed-off-by: Olof Johansson <olof@lixom.net>
This callback is expected to do the same as enter() but it has to
guarantee that interrupts aren't enabled at any point in its execution,
as the tick is frozen.
It will be called when the system goes to suspend-to-idle and will
reduce power usage because CPUs won't be awaken for unnecessary IRQs.
By setting the CPUIDLE_FLAG_TIMER_STOP flag, we can reuse the same code
for both the enter() and enter_freeze() callbacks.
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Cc: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
This is only relevant on Tegra114 and Tegra124, because earlier Tegra
generations used Cortex-A9 without secure extensions.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The driver requests the pclk clock at probe time already and stores its
reference to it in struct tegra_pmc, so there is no need to look it up
everytime it is needed. Use the existing reference instead.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Kbuild descends into drivers/soc/tegra/ only when CONFIG_ARCH_TEGRA
is enabled. (see drivers/soc/Makefile)
$(CONFIG_ARCH_TEGRA) in drivers/soc/tegra/Makefile always evaluates
to 'y'.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Recent versions of the Tegra MC hardware extend the size of the client
ID bitfield in the MC_ERR_STATUS register by one bit. While one could
simply extend the bitfield for older hardware, that would allow data
from reserved bits into the driver code, which is generally a bad idea
on principle. So this patch instead passes in the client ID mask from
from the per-SoC MC data.
There's no MC support for T210 (yet), but when that support winds up
in the kernel, the appropriate soc->client_id_mask value for that chip
will be 0xff.
Based on an original patch by David Ung <davidu@nvidia.com>.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Paul Walmsley <pwalmsley@nvidia.com>
Cc: Thierry Reding <treding@nvidia.com>
Cc: David Ung <davidu@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
SoC part of the Dove PMU series
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iEYEABECAAYFAlXE0fgACgkQCwYYjhRyO9XUKwCeIOTx172942DUMzGwO3feDGZn
zCgAn2yxrZaFqUo/EfVqgieeTGBmY6gh
=gfKo
-----END PGP SIGNATURE-----
Merge tag 'mvebu-soc-4.3-2' of git://git.infradead.org/linux-mvebu into next/drivers
mvebu soc changes for v4.3 (part #2)
SoC part of the Dove PMU series
* tag 'mvebu-soc-4.3-2' of git://git.infradead.org/linux-mvebu:
ARM: dove: create a proper PMU driver for power domains, PMU IRQs and resets
Signed-off-by: Olof Johansson <olof@lixom.net>
Add Clock Domain support to the RZ Clock Pulse Generator (CPG) driver
using the generic PM Domain. This allows to power-manage the module
clocks of SoC devices that are part of the CPG/MSTP Clock Domain using
Runtime PM, or for system suspend/resume.
SoC devices that are part of the CPG/MSTP Clock Domain and can be
power-managed through an MSTP clock should be tagged in DT with a proper
"power-domains" property.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add Clock Domain support to the R-Car Gen2 Clock Pulse Generator (CPG)
driver using the generic PM Domain. This allows to power-manage the
module clocks of SoC devices that are part of the CPG/MSTP Clock Domain
using Runtime PM, or for system suspend/resume.
SoC devices that are part of the CPG/MSTP Clock Domain and can be
power-managed through an MSTP clock should be tagged in DT with a proper
"power-domains" property.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add Clock Domain support to the R-Car H1 Clock Pulse Generator (CPG)
driver using the generic PM Domain. This allows to power-manage the
module clocks of SoC devices that are part of the CPG/MSTP Clock Domain
using Runtime PM, or for system suspend/resume.
SoC devices that are part of the CPG/MSTP Clock Domain and can be
power-managed through an MSTP clock should be tagged in DT with a proper
"power-domains" property.
Also update the reg property in the DT binding doc example to match the
actual dtsi, which uses #address-cells and #size-cells == 1, not 2.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add Clock Domain support to the R-Car M1A Clock Pulse Generator (CPG)
driver using the generic PM Domain. This allows to power-manage the
module clocks of SoC devices that are part of the CPG/MSTP Clock Domain
using Runtime PM, or for system suspend/resume.
SoC devices that are part of the CPG/MSTP Clock Domain and can be
power-managed through an MSTP clock should be tagged in DT with a proper
"power-domains" property.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add Clock Domain support to the Clock Pulse Generator (CPG) Module Stop
(MSTP) Clocks driver using the generic PM Domain. This allows to
power-manage the module clocks of SoC devices that are part of the
CPG/MSTP Clock Domain using Runtime PM, or for system suspend/resume.
SoC devices that are part of the CPG/MSTP Clock Domain and can be
power-managed through an MSTP clock should be tagged in DT with a
proper "power-domains" property.
The CPG/MSTP Clock Domain code will scan such devices for clocks that
are suitable for power-managing the device, by looking for a clock that
is compatible with "renesas,cpg-mstp-clocks".
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Reviewed-by: Kevin Hilman <khilman@linaro.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The PMU device contains an interrupt controller, power control and
resets. The interrupt controller is a little sub-standard in that
there is no race free way to clear down pending interrupts, so we try
to avoid problems by reducing the window as much as possible, and
clearing as infrequently as possible.
The interrupt support is implemented using an IRQ domain, and the
parent interrupt referenced in the standard DT way.
The power domains and reset support is closely related - there is a
defined sequence for powering down a domain which is tightly coupled
with asserting the reset. Hence, it makes sense to group these two
together, and in order to avoid any locking contention disrupting this
sequence, we avoid the use of syscon or regmap.
This patch adds the core PMU driver: power domains must be defined in
the DT file in order to make use of them. The reset controller can
be referenced in the standard way for reset controllers.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
This adds a reset controller driver to control the Xilinx Zynq
AP-SoC's various resets.
Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
Reviewed-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
The AR71XX/AR9XXX SoC have a simple reset controller with one bit per
reset line.
Signed-off-by: Alban Bedel <albeu@free.fr>
Acked-by: Ralf Baechle <ralf@linux-mips.org>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
In order for the Arria10 to be able to re-use the reset driver for SoCFPGA
Cyclone5/Arria5, we need to read the 'altr,modrst-offset' property from the
device tree entry. The 'altr,modrst-offset' property is the first register
into the reset manager that is used for bringing peripherals out of reset.
The driver assumes a modrst-offset of 0x10 in order to support legacy
Cyclone5/Arria5 hardware.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Add device tree binding documentation for the Reset Generation Unit
(RGU) found on NXP LPC18xx and LPC43xx devies.
This documentation also includes a table which shows the RGU reset
number and the connected peripheral.
Signed-off-by: Joachim Eastwood <manabian@gmail.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Add reset driver for the Reset Generation Unit (RGU) found on NXP
LPC18xx and LPC43xx devies. This reset controller features up to 64
reset lines connected to different blocks and peripheral in the SoC.
Most reset lines on the controller are self clearing except for
those dealing with the Cortex-M0 cores on LPC43xx devices.
This driver also registers a restart handler that can be used to
reset the entire device.
Signed-off-by: Joachim Eastwood <manabian@gmail.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
of_device_id is always used as const.
(See driver.of_match_table and open firmware functions)
Signed-off-by: Fabian Frederick <fabf@skynet.be>
Acked-by: Maxime Coquelin <maxime.coquelin@st.com>
Acked-by: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
By popular vote, the DT binding includes for reset controllers are located
in include/dt-bindings/reset/. Move the STi reset constants in there, too,
to avoid confusion.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Acked-by: Patrice Chotard <patrice.chotard@st.com>
This is the path for reset definitions to be used in both device tree and
reset controller drivers.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Add binding documentation for the Qualcomm Resource Power Manager (RPM)
using shared memory (Qualcomm SMD) as transport mechanism. This is found
in 8974 and newer based devices.
The binding currently describes the rpm itself and the regulator
subnodes.
Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Andy Gross <agross@codeaurora.org>
Driver for the Resource Power Manager (RPM) found in Qualcomm 8974 based
devices.
The driver exposes resources that child drivers can operate on; to
implementing regulator, clock and bus frequency drivers.
Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Andy Gross <agross@codeaurora.org>
This adds the Qualcomm Shared Memory Driver (SMD) providing
communication channels to remote processors, ontop of SMEM.
Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Andy Gross <agross@codeaurora.org>
Add device tree binding documentation for the Qualcomm Shared Memory
Device, used for communication between the various CPUs in the Qualcomm
SoCs.
Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Andy Gross <agross@codeaurora.org>
Enable QCOM_SCM for QCOM power management driver
Signed-off-by: Lina Iyer <lina.iyer@linaro.org>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Acked-by: Andy Gross <agross@codeaurora.org>
Signed-off-by: Andy Gross <agross@codeaurora.org>
The Shared Memory Manager driver implements an interface for allocating
and accessing items in the memory area shared among all of the
processors in a Qualcomm platform.
Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Acked-by: Andy Gross <agross@codeaurora.org>
Signed-off-by: Andy Gross <agross@codeaurora.org>
On the Armada 370/XP/38x/39x SoCs when the suspend to ram feature is
supported, the SoCs are shutdown and will be woken up by an external
micro-controller, so there is no possibility to setup wake-up sources
from Linux. However, in standby mode, the SoCs stay powered and it is
possible to wake-up from any interrupt sources. Since when the users
configures the enabled wake-up sources there is no way to know if the
user will be doing suspend to RAM or standby, we just allow all
wake-up sources to be enabled, and only warn when entering suspend to
RAM
The purpose of this patch is to inform the user that in suspend to ram
mode, the wake-up sources won't be taken into consideration.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Until now only one Armada XP and one Armada 388 based board supported
suspend to ram. However, most of the recent mvebu SoCs can support the
standby mode. Unlike for the suspend to ram, nothing special has to be
done for these SoCs. This patch allows the system to use the standby
mode on Armada 370, 38x, 39x and XP SoCs. There are issues with the
Armada 375, and the support might be added (if possible) in a future
patch.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
mvebu_pm_init and mvebu_armada_pm_init are only called during boot, so
flag them with __init and save some memory.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
The pm-board.c code contains the board-specific logic to enter suspend
to RAM. Until now, the code supported only the Armada XP GP board, so
all functions and symbols were named with armada_xp_gp. However, it
turns out that the Armada 388 GP also uses the same 3 GPIOs protocol
to talk to the PIC microcontroller that controls the power supply.
Since we are going to re-use the same code with no change for Armada
38x, this commit renames the functions and symbols to use just
"armada" instead of "armada_xp_gp". Better names can be found if one
day other boards having a different protocol/mechanism are supported
in the kernel.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
As we are going to introduce support for Armada 38x in pm.c, split out
the Armada XP part of mvebu_pm_store_bootinfo() into
mvebu_pm_store_armadaxp_bootinfo(), and make the former retunr an
error when an unsupported SoC is used.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
The mvebu_pm_init() initializes the support for suspend/resume, and
before doing that, it checks if we are on a board on which
suspend/resume is actually supported. However, this check is already
done by mvebu_armada_xp_gp_pm_init(), and there is no need to
duplicate the check: callers of mvebu_pm_init() should now what they
are doing.
This commit is done in preparation to the addition of suspend/resume
support on Armada 38x.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
This patch prepares the set_cpu_coherent() function in coherency.c to
be extended to support other SoCs than Armada XP. It will be needed on
Armada 38x to re-enable the coherency after exiting from suspend to
RAM.
This preparation simply moves the function further down in coherency.c
so that it can use coherency_type(), and uses that function to only do
the Armada XP specific work if we are on Armada XP.
Signed-off-by: Nadav Haklai <nadavh@marvell.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Building pl172 as a module fails with:
> ERROR: "of_default_bus_match_table" [drivers/memory/pl172.ko] undefined!
Because the symbol of_default_bus_match_table isn't exported by the OF
core code so can't be referenced from modules. Fix this by removing
the usage of of_default_bus_match_table for now. The side effect of
this is that child nodes can't use "simple-bus" or "simple-mfd".
Reported-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Joachim Eastwood <manabian@gmail.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
Add documentation for configuration and timing setup of
static memory devices on the ARM PL172 controller.
Signed-off-by: Joachim Eastwood <manabian@gmail.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
This driver makes it possible to configure the static memory
chip selects on the ARM PL172 MultiPort Memory Controller
from a set of properties in DT. Configuration of dynamic
memory is not supported and is left to the boot loader.
The intended usage is to setup timing and configuration for
static memory devices like NAND and NOR Flash before they
are probed by a driver.
Signed-off-by: Joachim Eastwood <manabian@gmail.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
The offset of the first spare bit register on Tegra210 is 0x380, but
account for the fixed offset of 0x100 in the fuse accessor.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The offset of the first spare bit register on Tegra124 is 0x300, but
account for the fixed offset of 0x100 in the fuse accessor.
Signed-off-by: Thierry Reding <treding@nvidia.com>
