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clk: shmobile: r8a7779: Add CPG/MSTP Clock Domain support
Add Clock Domain support to the R-Car H1 Clock Pulse Generator (CPG) driver using the generic PM Domain. This allows to power-manage the module clocks of SoC devices that are part of the CPG/MSTP Clock Domain using Runtime PM, or for system suspend/resume. SoC devices that are part of the CPG/MSTP Clock Domain and can be power-managed through an MSTP clock should be tagged in DT with a proper "power-domains" property. Also update the reg property in the DT binding doc example to match the actual dtsi, which uses #address-cells and #size-cells == 1, not 2. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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@ -1,7 +1,9 @@
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* Renesas R8A7779 Clock Pulse Generator (CPG)
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The CPG generates core clocks for the R8A7779. It includes one PLL and
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several fixed ratio dividers
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several fixed ratio dividers.
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The CPG also provides a Clock Domain for SoC devices, in combination with the
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CPG Module Stop (MSTP) Clocks.
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Required Properties:
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@ -12,16 +14,36 @@ Required Properties:
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- #clock-cells: Must be 1
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- clock-output-names: The names of the clocks. Supported clocks are "plla",
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"z", "zs", "s", "s1", "p", "b", "out".
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- #power-domain-cells: Must be 0
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SoC devices that are part of the CPG/MSTP Clock Domain and can be power-managed
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through an MSTP clock should refer to the CPG device node in their
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"power-domains" property, as documented by the generic PM domain bindings in
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Documentation/devicetree/bindings/power/power_domain.txt.
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Example
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-------
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Examples
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--------
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- CPG device node:
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cpg_clocks: cpg_clocks@ffc80000 {
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compatible = "renesas,r8a7779-cpg-clocks";
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reg = <0 0xffc80000 0 0x30>;
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reg = <0xffc80000 0x30>;
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clocks = <&extal_clk>;
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#clock-cells = <1>;
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clock-output-names = "plla", "z", "zs", "s", "s1", "p",
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"b", "out";
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#power-domain-cells = <0>;
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};
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- CPG/MSTP Clock Domain member device node:
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sata: sata@fc600000 {
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compatible = "renesas,sata-r8a7779", "renesas,rcar-sata";
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reg = <0xfc600000 0x2000>;
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interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp1_clks R8A7779_CLK_SATA>;
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power-domains = <&cpg_clocks>;
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};
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@ -168,6 +168,8 @@ static void __init r8a7779_cpg_clocks_init(struct device_node *np)
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}
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of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);
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cpg_mstp_add_clk_domain(np);
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}
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CLK_OF_DECLARE(r8a7779_cpg_clks, "renesas,r8a7779-cpg-clocks",
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r8a7779_cpg_clocks_init);
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