Commit Graph

590000 Commits

Author SHA1 Message Date
David Daney
182a6d1cd3 MIPS: OCTEON: Add model checking support for cn73xx, cnf75xx and cn78xx
Follow on patchs need to be able to distinguish the new models.

Signed-off-by: David Daney <david.daney@cavium.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/12498/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-05-13 14:01:40 +02:00
David Daney
2df11221bd MIPS: OCTEON: Add register definitions for cn73xx, cnf75xx and cn78xx.
These new members of the OCTEON III family have some new registers,
update some of the definitions for use in follow on patches.

Signed-off-by: David Daney <david.daney@cavium.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/12497/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-05-13 14:01:40 +02:00
David Daney
1d2753a66a MIPS: Select CONFIG_HANDLE_DOMAIN_IRQ and make it work.
Per the subject, always select HANDLE_DOMAIN_IRQ, and implement
set_irq_regs() so that it actually works.

Signed-off-by: David Daney <david.daney@cavium.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/12496/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-05-13 14:01:40 +02:00
David Daney
2253e0b9d9 MIPS: OCTEON: Remove some code limiting NR_IRQS to 255
Follow-on patches for OCTEON III will increase the number of irqs to
potentially more than 256.

Increase the width of the octeon_irq_ciu_to_irq to int to be able to
handle this case.  Remove the hacky code that verified that u8 would
not be overflowed.

Signed-off-by: David Daney <david.daney@cavium.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/12495/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-05-13 14:01:39 +02:00
David Daney
7d52ab163c MIPS: OCTEON: Extend number of supported CPUs past 32
To support more than 48 CPUs, the bootinfo structure grows a new
coremask structure.  Add the definition of the structure and add it to
struct cvmx_bootinfo.  In prom_init(), copy the new coremask data into
the sysinfo structure, and use it in smp_setup().

Signed-off-by: David Daney <david.daney@cavium.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/12319/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-05-13 14:01:39 +02:00
David Daney
58546e3b73 MIPS: OCTEON: Remove dead code from cvmx-sysinfo.
Get rid of the long unused code.

Signed-off-by: David Daney <david.daney@cavium.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/12318/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-05-13 14:01:39 +02:00
David Daney
b8c8f66507 MIPS: Add CPU identifiers and probing for Cavium CN73xx and CNF75xx processors.
Add new processor identifiers for Cavium CN73xx and CNF75xx
processors, and probe for them in cpu-probe.c

Signed-off-by: David Daney <david.daney@cavium.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/12311/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-05-13 14:01:38 +02:00
Ralf Baechle
34ae8e3688 MIPS: highmem: Turn flush_cache_kmaps into a no-op.
It was calling flush_cache_all() which is a no-op since a long time anyway
and which was overkill in the old days when it was actually doing something
because only the D-cache needs to be flushed, never the I-cache, never
the S-cache.  Since however highmem on MIPS is still only supported on
processors that don't suffer from cache aliases, we could turn
flush_cache_kmaps() into a no-op - but for paranoia's sake we rather make
it BUG_ON(cpu_has_dc_aliases()).

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-05-13 14:01:38 +02:00
Ralf Baechle
429365b2a1 MIPS: Loongson64: Remove call to flush_cache_all().
flush_cache_all() is a nop and loongson 3 is fully coherent.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-05-13 14:01:38 +02:00
Ralf Baechle
a48ac3a131 MIPS: VR41xx: Use __flush_cache_all instead of flush_cache_all.
It's probably a good idea to flush caches before reset and by the time
this code was written flush_cache_all did actually still do something.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-05-13 14:01:38 +02:00
Ralf Baechle
7c8196fd43 MIPS: MSP71xx: Use __flush_cache_all instead of flush_cache_all.
Flushing caches is probably sensible on reset but flush_cache_all has been
a no-op for a very long time.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-05-13 14:01:38 +02:00
Ralf Baechle
9329c154e4 MIPS: Octeon: Use __flush_cache_all instead of flush_cache_all.
flush_cache_all will go away.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-05-13 14:01:37 +02:00
Alban Bedel
81424d0ad0 MIPS: ath79: Use the reset controller to restart OF machines
Don't set _machine_restart() on OF machines as the reset driver
now provides a system restart handler.

Signed-off-by: Alban Bedel <albeu@free.fr>
Cc: Felix Fietkau <nbd@openwrt.org>
Cc: Antony Pavlov <antonynpavlov@gmail.com>
Cc: Gabor Juhos <juhosg@openwrt.org>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/12235/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-05-13 14:01:37 +02:00
Alban Bedel
b3f0a250d6 MIPS: ath79: Add zboot debug serial support
Reuse the early printk code to support the serial in zboot. We copy
early_printk.c instead of referencing it because we need to build a
different object file for the normal kernel and zboot.

Signed-off-by: Alban Bedel <albeu@free.fr>
Cc: Andrew Bresticker <abrestic@chromium.org>
Cc: Alex Smith <alex.smith@imgtec.com>
Cc: Wu Zhangjin <wuzhangjin@gmail.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/12234/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-05-13 14:01:37 +02:00
Alban Bedel
ea3a7085bf MIPS: ath79: Remove the builtin DTB support
Now that appended DTB is usable we can drop the builtin DTB support.

Signed-off-by: Alban Bedel <albeu@free.fr>
Cc: Felix Fietkau <nbd@openwrt.org>
Cc: Antony Pavlov <antonynpavlov@gmail.com>
Cc: Gabor Juhos <juhosg@openwrt.org>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/12231/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-05-13 14:01:37 +02:00
Alban Bedel
8f4d4d1bfb MIPS: ath79: Add support for DTB passed using the UHI boot protocol
This is needed for bootloader supporting UHI and to support appended
DTB.

Signed-off-by: Alban Bedel <albeu@free.fr>
Cc: Felix Fietkau <nbd@openwrt.org>
Cc: Antony Pavlov <antonynpavlov@gmail.com>
Cc: Gabor Juhos <juhosg@openwrt.org>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/12230/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-05-13 14:01:37 +02:00
James Hogan
32eb6e8bee MIPS: Netlogic: Fix CP0_EBASE redefinition warnings
A couple of netlogic assembly files define CP0_EBASE to $15, the same as
CP0_PRID in mipsregs.h, and use it for accessing both CP0_PRId and
CP0_EBase registers. However commit 609cf6f229 ("MIPS: CPS: Early
debug using an ns16550-compatible UART") added a different definition of
CP0_EBASE to mipsregs.h, which included a register select of 1. This
causes harmless build warnings like the following:

  arch/mips/netlogic/common/reset.S:53:0: warning: "CP0_EBASE" redefined
  #define CP0_EBASE $15
  ^
  In file included from arch/mips/netlogic/common/reset.S:41:0:
  ./arch/mips/include/asm/mipsregs.h:63:0: note: this is the location of the previous definition
  #define CP0_EBASE $15, 1
  ^

Update the code to use the definitions from mipsregs.h for accessing
both registers.

Fixes: 609cf6f229 ("MIPS: CPS: Early debug using an ns16550-compatible UART")
Signed-off-by: James Hogan <james.hogan@imgtec.com>
Acked-by: Jayachandran C <jchandra@broadcom.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/13183/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-05-09 12:00:05 +02:00
Joshua Kinard
128639395b MIPS: Adjust set_pte() SMP fix to handle R10000_LLSC_WAR
Update the recent changes to set_pte() that were added in 46011e6ea3
to handle R10000_LLSC_WAR, and format the assembly to match other areas
of the MIPS tree using the same WAR.

This also incorporates a patch recently sent in my Markos Chandras,
"Remove local LL/SC preprocessor variants", so that patch doesn't need
to be applied if this one is accepted.

Signed-off-by: Joshua Kinard <kumba@gentoo.org>
Fixes: 46011e6ea3 ("MIPS: Make set_pte() SMP safe.)
Cc: David Daney <david.daney@cavium.com>
Cc: Linux/MIPS <linux-mips@linux-mips.org>
Patchwork: https://patchwork.linux-mips.org/patch/11103/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-05-09 12:00:05 +02:00
Ralf Baechle
05490626d5 MIPS: Move definitions for 32/64-bit agonstic inline assembler to new file.
Inspired by Markos Chandras' patch.  I just didn't want do pull bitsops.h
into pgtable.h.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
References: https://patchwork.linux-mips.org/patch/11052/
2016-05-09 12:00:05 +02:00
James Hogan
92e9953c58 MIPS: Fix MSA assembly warnings
Building an MSA capable kernel with a toolchain that supports MSA
produces warnings such as this:

arch/mips/kernel/r4k_fpu.S:229: Warning: the `msa' extension requires 64-bit FPRs

This is due to ".set msa" without ".set fp=64" in the non doubleword MSA
load/store macros, since MSA requires the 64-bit FPU registers (FR=1).
Add the missing fp=64 in these macros to silence the warnings.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/13063/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-05-09 12:00:05 +02:00
James Hogan
143e93d74e MIPS: Fix MSA assembly with big thread offsets
When lockdep is enabled on a 64-bit kernel the FPR offset into the
thread structure exceeds the maximum range of the MSA ld.d/st.d
instructions. For example THREAD_FPR31 = 4644 (instead of 2448), while
the signed immediate field is only 10 bits with an implicit multiply by
8, giving a maximum offset of 511*8 = 4088.

This isn't a problem when the toolchain doesn't support MSA as the
ld_*/st_* macros perform the addition separately into $1 with [d]addui
which has a 16bit signed immediate field.

Fix the case where the toolchain does support MSA by doing a single
addition of THREAD_FPR0 into $1 with [d]addui, and doing the ld_*/st_*
relative to that.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/13064/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-05-09 12:00:05 +02:00
James Hogan
ea16885734 MIPS: Fix MSA ld_*/st_* asm macros to use PTR_ADDU
The MSA ld_*/st_* assembler macros for when the toolchain doesn't
support MSA use addu to offset the base address. However it is a virtual
memory pointer so fix it to use PTR_ADDU which expands to daddu for
64-bit kernels.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: <stable@vger.kernel.org> # 4.3.y-
Patchwork: https://patchwork.linux-mips.org/patch/13062/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-05-09 12:00:04 +02:00
Paul Burton
8a3c8b48ac MIPS: Use copy_s.fmt rather than copy_u.fmt
In revision 1.12 of the MSA specification, the copy_u.w instruction has
been removed for MIPS32 & the copy_u.d instruction has been removed for
MIPS64. Newer toolchains (eg. Codescape SDK essentials 2015.10) will
complain about this like so:

arch/mips/kernel/r4k_fpu.S:290: Error: opcode not supported on this
processor: mips32r2 (mips32r2) `copy_u.w $1,$w26[3]'

Since we always copy to the width of a GPR, simply use copy_s instead of
copy_u to fix this.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: <stable@vger.kernel.org> # 4.3.x+
Patchwork: https://patchwork.linux-mips.org/patch/13061/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-05-09 12:00:04 +02:00
Maciej W. Rozycki
8e85f275e9 MIPS: memset.S: Disable code unused with non-R6 MIPS configs
This complements commit 8c56208aff ("MIPS: lib: memset: Add MIPS R6
support").

Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/12452/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-05-09 12:00:04 +02:00
Leonid Yegoshin
41fa29e4d8 MIPS64: R6: R2 emulation bugfix
Error recovery pointers for fixups was improperly set as ".word"
which is unsuitable for MIPS64.

Replaced by STR(PTR)

[ralf@linux-mips.org: Apply changes as requested in the review process.]

Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Reviewed-by: James Hogan <james.hogan@imgtec.com>
Reviewed-by: Markos Chandras <markos.chandras@imgtec.com>
Fixes: b0a668fb20 ("MIPS: kernel: mips-r2-to-r6-emul: Add R2 emulator for MIPS R6")
Cc: macro@linux-mips.org
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: <stable@vger.kernel.org> # 4.0+
Patchwork: https://patchwork.linux-mips.org/patch/9911/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-05-09 12:00:04 +02:00
Matt Redfearn
8d4925e9a5 MIPS: dma-default: Defend against NULL dev in massage_gfp_flags
This patch ensures that the dev parameter is checked for NULL before it
is dereferenced in massage_gfp_flags. If dev is NULL, then fall back
setting the GFP flag requested and available.

Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/11919/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-05-09 12:00:04 +02:00
Yanjiang Jin
fa0c879ffc MIPS: oprofile: Fix a preemption issue
Use boot_cpu_type() instead of current_cpu_type() in oprofile_arch_init()
to avoid the below warning, cpu_type is normally consistent in a MIPS SMP
system.  There are a few exceptions such as SGI servers where it is
possible to mix R10000, R12000, R14000 and R16000 within certain
constraints.  Let's not worry about those now.

BUG: using smp_processor_id() in preemptible [00000000] code: insmod/952
caller is oprofile_arch_init+0x30/0x194 [oprofile]
CPU: 5 PID: 952 Comm: insmod Not tainted 4.1.13-WR8.0.0.0_standard #1
Stack : ffffffff80c10000 0000000000000001 8000000025bf0790 ffffffff80e10000
	  ffffffff80e50000 ffffffff80254e2c ffffffff80b64428 ffffffff80e10790
	  0000000000000000 ffffffff801caeb8 0000000000000045 0000000000000005
	  ffffffff80c10000 ffffffff801cb798 0000000000000000 ffffffff80e30000
	  0000000000000000 ffffffff801ff1c0 ffffffff80e2d2f8 000000000000000b
	  ffffffff801cbba0 ffffffff80e107b0 ffffffff80a77828 0000000000000005
	  00000000000003b8 ffffffff80e2d2f8 800000040ad39960 ffffffff801f9950
	  0000000000000124 80000004093b7990 80000004093b7ab8 ffffffff80925108
	  ffffffff80b69a07 ffffffff80a6f0d0 8000000407240e00 ffffffff801cc934
	  000000000000005d ffffffff80159080 0000000000000005 00000000000003b8
	  ...
Call Trace:
[<ffffffff80159080>] show_stack+0xe8/0x108
[<ffffffff80925108>] dump_stack+0x8c/0xd8
[<ffffffff80606570>] check_preemption_disabled+0x110/0x118
[<ffffffffc0086104>] oprofile_arch_init+0x30/0x194 [oprofile]
[<ffffffffc008602c>] oprofile_init+0x2c/0xc0 [oprofile]
[<ffffffff80100550>] do_one_initcall+0xa0/0x1c0
[<ffffffff80921e04>] do_init_module+0x80/0x1d8
[<ffffffff801fd0d4>] load_module+0x1b74/0x2278
[<ffffffff801fdab4>] SyS_finit_module+0xcc/0xf0
[<ffffffff80165884>] handle_sysn32+0x44/0x70

[ralf@linux-mips.org: Correct commit message.]

Signed-off-by: Yanjiang Jin <yanjiang.jin@windriver.com>
Cc: rric@kernel.org
Cc: jinyanjiang@gmail.com
Cc: linux-mips@linux-mips.org
Cc: oprofile-list@lists.sf.net
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/11769/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-05-09 12:00:03 +02:00
Huacai Chen
820880cdba MIPS: Loongson-3: Fix build error after ld-version.sh modification
Commit d5ece1cb07 ("Fix ld-version.sh to handle large 3rd version
part") modifies the ld version description. This causes a build error
on Loongson-3, so fix it.

Signed-off-by: Huacai Chen <chenhc@lemote.com>
Cc: Aurelien Jarno <aurelien@aurel32.net>
Cc: Steven J . Hill <sjhill@realitydiluted.com>
Cc: Fuxin Zhang <zhangfx@lemote.com>
Cc: Zhangjin Wu <wuzhangjin@gmail.com>
Cc: Huacai Chen <chenhc@lemote.com>
Cc: linux-mips@linux-mips.org
Cc: stable@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/12890/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-05-09 12:00:03 +02:00
Huacai Chen
3484de7bcb MIPS: Loongson-3: Reserve 32MB for RS780E integrated GPU
Due to datasheet, reserving 0xff800000~0xffffffff (8MB below 4GB) is
not enough for RS780E integrated GPU's TOM (top of memory) registers
and MSI/MSI-x memory region, so we reserve 0xfe000000~0xffffffff (32MB
below 4GB).

Signed-off-by: Huacai Chen <chenhc@lemote.com>
Cc: Aurelien Jarno <aurelien@aurel32.net>
Cc: Steven J . Hill <sjhill@realitydiluted.com>
Cc: Fuxin Zhang <zhangfx@lemote.com>
Cc: Zhangjin Wu <wuzhangjin@gmail.com>
Cc: linux-mips@linux-mips.org
Cc: stable@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/12889/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-05-09 12:00:03 +02:00
Huacai Chen
a95d069204 MIPS: Reserve nosave data for hibernation
After commit 92923ca3aa ("mm: meminit: only set page reserved
in the memblock region"), the MIPS hibernation is broken. Because pages
in nosave data section should be "reserved", but currently they aren't
set to "reserved" at initialization. This patch makes hibernation work
again.

Signed-off-by: Huacai Chen <chenhc@lemote.com>
Cc: Aurelien Jarno <aurelien@aurel32.net>
Cc: Steven J . Hill <sjhill@realitydiluted.com>
Cc: Fuxin Zhang <zhangfx@lemote.com>
Cc: Zhangjin Wu <wuzhangjin@gmail.com>
Cc: linux-mips@linux-mips.org
Cc: stable@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/12888/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-05-09 12:00:03 +02:00
Andreas Ruprecht
54292850e8 MIPS: Sibyte: Fix Kconfig dependencies of SIBYTE_BUS_WATCHER
Commit 6793f55cbc ("MIPS: sibyte: Amend dependencies for
SIBYTE_BUS_WATCHER") changed the dependencies for
SIBYTE_BUS_WATCHER to make it visible only if SIBYTE_BCM112X
or SIBYTE_SB1250 are enabled.

In the code in arch/mips/sibyte/common/bus_watcher, however,
a #if defined() check suggests that this functionality should
also be available for SIBYTE_BCM1x55 and SIBYTE_BCM1x80.

Make it selectable by extending the dependencies of
SIBYTE_BUS_WATCHER in arch/mips/sibyte/Kconfig.

Reported-by: Jonas Rabenstein <jonas.rabenstein@studium.uni-erlangen.de>
Signed-off-by: Andreas Ruprecht <andreas.ruprecht@fau.de>
Cc: valentinrothberg@gmail.com
Cc: stefan.hengelein@fau.de
Cc: pebolle@tiscali.nl
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/10736/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-05-09 12:00:03 +02:00
James Hogan
47f2ac5058 MIPS: I6400: Icache fills from dcache
Coherence Manager 3 (CM3) as present in I6400 can fill icache lines
effectively from dirty dcaches, so there is no need to flush dirty lines
from dcaches through to L2 prior to icache invalidation.

Set the MIPS_CACHE_IC_F_DC flag such that cpu_has_ic_fills_f_dc
evaluates to true, which avoids those dcache flushes.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Leonid Yegoshin <leonid.yegoshin@imgtec.com>
Cc: Manuel Lauss <manuel.lauss@gmail.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/12180/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-05-09 12:00:03 +02:00
James Hogan
b2a3c5be4d MIPS: c-r4k: Sync icache when it fills from dcache
It is still necessary to handle icache coherency in flush_cache_range()
and copy_to_user_page() when the icache fills from the dcache, even
though the dcache does not need to be written back. However when this
handling was added in commit 2eaa7ec286 ("[MIPS] Handle I-cache
coherency in flush_cache_range()"), it did not do any icache flushing
when it fills from dcache.

Therefore fix r4k_flush_cache_range() to run
local_r4k_flush_cache_range() without taking into account whether icache
fills from dcache, so that the icache coherency gets handled. Checks are
also added in local_r4k_flush_cache_range() so that the dcache blast
doesn't take place when icache fills from dcache.

A test to mmap a page PROT_READ|PROT_WRITE, modify code in it, and
mprotect it to VM_READ|VM_EXEC (similar to case described in above
commit) can hit this case quite easily to verify the fix.

A similar check was added in commit f8829caee3 ("[MIPS] Fix aliasing
bug in copy_to_user_page / copy_from_user_page"), so also fix
copy_to_user_page() similarly, to call flush_cache_page() without taking
into account whether icache fills from dcache, since flush_cache_page()
already takes that into account to avoid performing a dcache flush.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Leonid Yegoshin <leonid.yegoshin@imgtec.com>
Cc: Manuel Lauss <manuel.lauss@gmail.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/12179/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-05-09 12:00:02 +02:00
James Hogan
679eb63779 MIPS: Enable ptrace hw watchpoints on MIPS R6
HARDWARE_WATCHPOINTS isn't being enabled for CPU_MIPSR6, even though it
has an identical hardware watchpoint interface to CPU_MIPSR2, which
prevents ptrace watchpoints from being loaded when executing a ptraced
process even though the watchpoints are described in /proc/cpuinfo.

Enable HARDWARE_WATCHPOINTS for CPU_MIPSR6 too.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/12727/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-05-09 12:00:02 +02:00
James Hogan
a7e89326b4 MIPS: Fix watchpoint restoration
Commit f51246efee ("MIPS: Get rid of finish_arch_switch().") moved the
__restore_watch() call from finish_arch_switch() (i.e. after resume()
returns) to before the resume() call in switch_to(). This results in
watchpoints only being restored when a task is descheduled, preventing
the watchpoints from being effective most of the time, except due to
chance before the watchpoints are lazily removed.

Fix the call sequence from switch_to() through to
mips_install_watch_registers() to pass the task_struct pointer of the
next task, instead of using current. This allows the watchpoints for the
next (non-current) task to be restored without reintroducing
finish_arch_switch().

Fixes: f51246efee ("MIPS: Get rid of finish_arch_switch().")
Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: <stable@vger.kernel.org> # 4.3.x-
Patchwork: https://patchwork.linux-mips.org/patch/12726/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-05-09 12:00:02 +02:00
James Hogan
81a76d7119 MIPS: Avoid using unwind_stack() with usermode
When showing backtraces in response to traps, for example crashes and
address errors (usually unaligned accesses) when they are set in debugfs
to be reported, unwind_stack will be used if the PC was in the kernel
text address range. However since EVA it is possible for user and kernel
address ranges to overlap, and even without EVA userland can still
trigger an address error by jumping to a KSeg0 address.

Adjust the check to also ensure that it was running in kernel mode. I
don't believe any harm can come of this problem, since unwind_stack() is
sufficiently defensive, however it is only meant for unwinding kernel
code, so to be correct it should use the raw backtracing instead.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Reviewed-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: <stable@vger.kernel.org> # 3.15+
Patchwork: https://patchwork.linux-mips.org/patch/11701/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
(cherry picked from commit d2941a975ac745c607dfb590e92bb30bc352dad9)
2016-05-09 12:00:02 +02:00
James Hogan
a816b306c6 MIPS: Don't unwind to user mode with EVA
When unwinding through IRQs and exceptions, the unwinding only continues
if the PC is a kernel text address, however since EVA it is possible for
user and kernel address ranges to overlap, potentially allowing
unwinding to continue to user mode if the user PC happens to be in the
kernel text address range.

Adjust the check to also ensure that the register state from before the
exception is actually running in kernel mode, i.e. !user_mode(regs).

I don't believe any harm can come of this problem, since the PC is only
output, the stack pointer is checked to ensure it resides within the
task's stack page before it is dereferenced in search of the return
address, and the return address register is similarly only output (if
the PC is in a leaf function or the beginning of a non-leaf function).

However unwind_stack() is only meant for unwinding kernel code, so to be
correct the unwind should stop there.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Reviewed-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: <stable@vger.kernel.org> # 3.15+
Patchwork: https://patchwork.linux-mips.org/patch/11700/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-05-09 12:00:02 +02:00
Florian Fainelli
f6cc0ee98b MIPS: BMIPS: Fill in current_cpu_data.core
Read the core ID in bmips_smp_finish() for BMIPS5000 CPUs to get appropriate
processor parenting in set_cpu_sibling_map().

Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Cc: john@phrozen.org
Cc: cernekee@gmail.com
Cc: jon.fraser@broadcom.com
Cc: jaedon.shin@gmail.com
Cc: dragan.stancevic@gmail.com
Cc: jogo@openwrt.org
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/12380/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-05-09 12:00:01 +02:00
Florian Fainelli
904c3b4952 MIPS: BMIPS: Remove maxcpus from BCM97435SVMB DTS
Now that SMP properly works on 7435, do not restrict the number of core,
unleash them all.

Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Cc: john@phrozen.org
Cc: cernekee@gmail.com
Cc: jon.fraser@broadcom.com
Cc: jaedon.shin@gmail.com
Cc: dragan.stancevic@gmail.com
Cc: jogo@openwrt.org
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/12379/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-05-09 12:00:01 +02:00
Florian Fainelli
a5b143ec51 MIPS: BMIPS: Add missing 7038 L1 register cells to BCM7435
7435 has 4 7038 L1 base register address for each of its Core + TP (for a total
of 4 threads of execution), add the two missing cells for Core 1. We are
providing HW interrupts 2/3 even for Core 1/TP0/TP1 because that's what they
are, and we can later decide to remap these in software to provide proper
interrupt affinity/parenting.

Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Cc: john@phrozen.org
Cc: cernekee@gmail.com
Cc: jon.fraser@broadcom.com
Cc: jaedon.shin@gmail.com
Cc: dragan.stancevic@gmail.com
Cc: jogo@openwrt.org
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/12378/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-05-09 12:00:01 +02:00
Ralf Baechle
f241265fdc MIPS: BMIPS: Make whitespacely correct.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-05-09 12:00:01 +02:00
Florian Fainelli
21b30c00f3 MIPS: BMIPS: Add Whirlwind (BMIPS5200) initialization code
Import bmips_5xxx_init.S from the stblinux-3.3 tree, and to make sure that this
would work nicely with a BMIPS multiplatform kernel (with BMIPS330, BMIPS43XX
and BMIPS5000 enabled), update soft_reset to check for the BMIPS5200 processor
id (PRID_IMP_BMIPS5200) and execute bmips_5xxx_init for these processors to
bring them online.

Tested on 7425, 7429 and 7435 with CPU hotplug. 7435 SMP still needs some
additional changes in the L1 interrupt area to work properly with interrupt
affinity.

Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Cc: linux-mips@linux-mips.org
Cc: john@phrozen.org
Cc: cernekee@gmail.com
Cc: jon.fraser@broadcom.com
Cc: jaedon.shin@gmail.com
Cc: dragan.stancevic@gmail.com
Cc: jogo@openwrt.org
Patchwork: https://patchwork.linux-mips.org/patch/12377/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-05-09 12:00:01 +02:00
Florian Fainelli
cbbda6e7c9 MIPS: BMIPS: Fix PRID_IMP_BMIPS5000 masking for BMIPS5200
BMIPS5000 have a PrID value of 0x5A00 and BMIPS5200 have a PrID value of
0x5B00, which, masked with 0x5A00, returns 0x5A00. Update all conditionals on
the PrID to cover both variants since we are going to need this to enable
BMIPS5200 SMP. The existing check, masking with 0xFF00 would not cover
BMIPS5200 at all.

Fixes: 68e6a78373 ("MIPS: BMIPS: Add PRId for BMIPS5200 (Whirlwind)")
Fixes: 6465460c92 ("MIPS: BMIPS: change compile time checks to runtime checks")
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Cc: john@phrozen.org
Cc: cernekee@gmail.com
Cc: jogo@openwrt.org
Cc: jaedon.shin@gmail.com
Cc: jfraser@broadcom.com
Cc: pgynther@google.com
Cc: dragan.stancevic@gmail.com
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/12279/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-05-09 12:00:01 +02:00
Paul Burton
578bffc82e MIPS: Don't BUG_ON when no IPI domain is found
Commit fbde2d7d82 ("MIPS: Add generic SMP IPI support") introduced
code that BUG_ON's in the case of a kernel that supports IPI domains but
does not have one at runtime. This case is possible on Malta where for
IPIs we may use either the GIC (which has an IPI IRQ domain
implementation) or core-local software interrupts between VPEs (which do
not currently have an IPI IRQ domain implementation). We can not know
which will be used until runtime when we know whether a GIC is actually
present, and if we run on a system with multiple VPEs and no GIC then
the BUG_ON is hit.

Commit 19fb5818ed ("IPS: Fix broken malta qemu") worked around this
for the single-core single-VPE case typically seen using QEMU, but does
not catch the multi-VPE case. This patch removes the insufficient CPU
presence check that was added and works around the bug differently,
effectively reverting that commit.

A simple way to reproduce this bug is by using QEMU, which partially
implements the MT ASE but does not implement the GIC as of version 2.5.
Using "-cpu 34Kf -smp 2" will present a system with 2 VPEs in one core &
no GIC, hitting the BUG_ON.

Given that we're post-merge-window on the way to v4.6, avoid this by
just returning from mips_smp_ipi_init when no IPI IRQ domain is found.
Ideally at some point all IPI implementations would be converted to the
same IPI IRQ domain interface & we'd be able to restore the check.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Qais Yousef <qsyousef@gmail.com>
Fixes: fbde2d7d82 ("MIPS: Add generic SMP IPI support")
Fixes: 19fb5818ed ("IPS: Fix broken malta qemu")
Reverts: 19fb5818ed ("IPS: Fix broken malta qemu")
Cc: Qais Yousef <qsyousef@gmail.com>
Cc: James Hogan <james.hogan@imgtec.com>
Cc: Alex Smith <alex.smith@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/13007/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-05-09 12:00:00 +02:00
James Hogan
5daebc477d MIPS: Fix siginfo.h to use strict posix types
Commit 85efde6f4e ("make exported headers use strict posix types")
changed the asm-generic siginfo.h to use the __kernel_* types, and
commit 3a471cbc08 ("remove __KERNEL_STRICT_NAMES") make the internal
types accessible only to the kernel, but the MIPS implementation hasn't
been updated to match.

Switch to proper types now so that the exported asm/siginfo.h won't
produce quite so many compiler errors when included alone by a user
program.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Christopher Ferris <cferris@google.com>
Cc: linux-mips@linux-mips.org
Cc: <stable@vger.kernel.org> # 2.6.30-
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/12477/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-05-09 12:00:00 +02:00
Corey Minyard
c80e1b62ff MIPS: Fix crash registers on non-crashing CPUs
As part of handling a crash on an SMP system, an IPI is send to
all other CPUs to save their current registers and stop.  It was
using task_pt_regs(current) to get the registers, but that will
only be accurate if the CPU was interrupted running in userland.
Instead allow the architecture to pass in the registers (all
pass NULL now, but allow for the future) and then use get_irq_regs()
which should be accurate as we are in an interrupt.  Fall back to
task_pt_regs(current) if nothing else is available.

Signed-off-by: Corey Minyard <cminyard@mvista.com>
Cc: David Daney <ddaney@caviumnetworks.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/13050/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-05-09 12:00:00 +02:00
Nikolay Martynov
e03ac9f0c3 mips: Fix CPC_BASE_ADDR mask to match datasheet
According to 'MIPS32® interAptivTM Multiprocessing
System Programmer’s Guide' CPC_BASE_ADDR takes bits [31:15].

This change is tested ith mt7621 which wasn't working without it.

Signed-off-by: Nikolay Martynov <mar.kolya@gmail.com>
Reviewed-by: James Hogan <james.hogan@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/11766/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-05-09 12:00:00 +02:00
Linus Torvalds
44549e8f5e Linux 4.6-rc7 2016-05-08 14:38:32 -07:00
Linus Torvalds
32cf95db22 Char/Misc driver fixes for 4.6-rc7
Here are 3 small fixes for some driver problems that were reported.
 Full details in the shortlog below.
 
 All of these have been in linux-next with no reported issues.
 
 Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v2
 
 iEYEABECAAYFAlcuKUQACgkQMUfUDdst+yk8qgCguPDODcYzOWiH1+RtIXTH5kXG
 /1EAoIx7+uhzX9pt9E635NsrcNJqefWx
 =9Uhc
 -----END PGP SIGNATURE-----

Merge tag 'char-misc-4.6-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc

Pull misc driver fixes from Gfreg KH:
 "Here are three small fixes for some driver problems that were
  reported.  Full details in the shortlog below.

  All of these have been in linux-next with no reported issues"

* tag 'char-misc-4.6-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc:
  nvmem: mxs-ocotp: fix buffer overflow in read
  Drivers: hv: vmbus: Fix signaling logic in hv_need_to_signal_on_read()
  misc: mic: Fix for double fetch security bug in VOP driver
2016-05-07 10:53:32 -07:00
Linus Torvalds
630aac5ab6 Staging/IIO driver fixes for 4.6-rc7
Well, it's really just IIO drivers here, some small fixes that resolve
 some "crash on boot" errors that have shown up in the -rc series, and
 other bugfixes that are required.
 
 All have been in linux-next with no reported problems.
 
 Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v2
 
 iEYEABECAAYFAlcuKBgACgkQMUfUDdst+ynALgCgh4QWOZ/vnLQvx/r1ZOIW1xqm
 QdAAn1eJ1/KzwbM+WmmfXu1dKykfs7YS
 =tGM3
 -----END PGP SIGNATURE-----

Merge tag 'staging-4.6-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging

Pull IIO driver fixes from Grek KH:
 "It's really just IIO drivers here, some small fixes that resolve some
  'crash on boot' errors that have shown up in the -rc series, and other
  bugfixes that are required.

  All have been in linux-next with no reported problems"

* tag 'staging-4.6-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging:
  iio: imu: mpu6050: Fix name/chip_id when using ACPI
  iio: imu: mpu6050: fix possible NULL dereferences
  iio:adc:at91-sama5d2: Repair crash on module removal
  iio: ak8975: fix maybe-uninitialized warning
  iio: ak8975: Fix NULL pointer exception on early interrupt
2016-05-07 10:50:48 -07:00