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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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MIPS: OCTEON: Add model checking support for cn73xx, cnf75xx and cn78xx
Follow on patchs need to be able to distinguish the new models. Signed-off-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/12498/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
David Daney
Ralf Baechle
parent
2df11221bd
commit
182a6d1cd3
@ -71,11 +71,11 @@ static const char *__init octeon_model_get_string_buffer(uint32_t chip_id,
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uint32_t fuse_data = 0;
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fus3.u64 = 0;
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if (!OCTEON_IS_MODEL(OCTEON_CN6XXX))
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if (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX))
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fus3.u64 = cvmx_read_csr(CVMX_L2D_FUS3);
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fus_dat2.u64 = cvmx_read_csr(CVMX_MIO_FUS_DAT2);
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fus_dat3.u64 = cvmx_read_csr(CVMX_MIO_FUS_DAT3);
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num_cores = cvmx_pop(cvmx_read_csr(CVMX_CIU_FUSE));
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num_cores = cvmx_octeon_num_cores();
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/* Make sure the non existent devices look disabled */
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switch ((chip_id >> 8) & 0xff) {
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@ -121,6 +121,15 @@ static const char *__init octeon_model_get_string_buffer(uint32_t chip_id,
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* later.
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*/
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switch (num_cores) {
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case 48:
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core_model = "90";
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break;
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case 44:
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core_model = "88";
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break;
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case 40:
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core_model = "85";
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break;
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case 32:
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core_model = "80";
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break;
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@ -297,7 +306,7 @@ static const char *__init octeon_model_get_string_buffer(uint32_t chip_id,
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if (fus_dat3.s.nozip)
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suffix = "SCP";
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if (fus_dat3.s.bar2_en)
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if (fus_dat3.cn56xx.bar2_en)
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suffix = "NSPB2";
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}
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if (fus3.cn56xx.crip_1024k)
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@ -369,6 +378,73 @@ static const char *__init octeon_model_get_string_buffer(uint32_t chip_id,
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else
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suffix = "AAP";
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break;
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case 0x94: /* CNF71XX */
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family = "F71";
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if (fus_dat3.cnf71xx.nozip)
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suffix = "SCP";
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else
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suffix = "AAP";
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break;
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case 0x95: /* CN78XX */
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if (num_cores == 6) /* Other core counts match generic */
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core_model = "35";
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if (OCTEON_IS_MODEL(OCTEON_CN76XX))
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family = "76";
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else
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family = "78";
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if (fus_dat3.cn78xx.l2c_crip == 2)
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family = "77";
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if (fus_dat3.cn78xx.nozip
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&& fus_dat3.cn78xx.nodfa_dte
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&& fus_dat3.cn78xx.nohna_dte) {
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if (fus_dat3.cn78xx.nozip &&
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!fus_dat2.cn78xx.raid_en &&
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fus_dat3.cn78xx.nohna_dte) {
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suffix = "CP";
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} else {
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suffix = "SCP";
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}
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} else if (fus_dat2.cn78xx.raid_en == 0)
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suffix = "HCP";
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else
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suffix = "AAP";
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break;
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case 0x96: /* CN70XX */
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family = "70";
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if (cvmx_read_csr(CVMX_MIO_FUS_PDF) & (0x1ULL << 32))
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family = "71";
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if (fus_dat2.cn70xx.nocrypto)
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suffix = "CP";
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else if (fus_dat3.cn70xx.nodfa_dte)
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suffix = "SCP";
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else
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suffix = "AAP";
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break;
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case 0x97: /* CN73XX */
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if (num_cores == 6) /* Other core counts match generic */
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core_model = "35";
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family = "73";
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if (fus_dat3.cn73xx.l2c_crip == 2)
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family = "72";
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if (fus_dat3.cn73xx.nozip
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&& fus_dat3.cn73xx.nodfa_dte
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&& fus_dat3.cn73xx.nohna_dte) {
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if (!fus_dat2.cn73xx.raid_en)
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suffix = "CP";
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else
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suffix = "SCP";
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} else
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suffix = "AAP";
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break;
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case 0x98: /* CN75XX */
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family = "F75";
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if (fus_dat3.cn78xx.nozip
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&& fus_dat3.cn78xx.nodfa_dte
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&& fus_dat3.cn78xx.nohna_dte)
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suffix = "SCP";
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else
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suffix = "AAP";
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break;
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default:
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family = "XX";
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core_model = "XX";
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@ -57,6 +57,7 @@ enum cvmx_mips_space {
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#include <asm/octeon/cvmx-sysinfo.h>
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#include <asm/octeon/cvmx-ciu-defs.h>
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#include <asm/octeon/cvmx-ciu3-defs.h>
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#include <asm/octeon/cvmx-gpio-defs.h>
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#include <asm/octeon/cvmx-iob-defs.h>
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#include <asm/octeon/cvmx-ipd-defs.h>
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@ -341,6 +342,21 @@ static inline unsigned int cvmx_get_core_num(void)
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return core_num;
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}
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/* Maximum # of bits to define core in node */
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#define CVMX_NODE_NO_SHIFT 7
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#define CVMX_NODE_MASK 0x3
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static inline unsigned int cvmx_get_node_num(void)
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{
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unsigned int core_num = cvmx_get_core_num();
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return (core_num >> CVMX_NODE_NO_SHIFT) & CVMX_NODE_MASK;
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}
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static inline unsigned int cvmx_get_local_core_num(void)
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{
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return cvmx_get_core_num() & ((1 << CVMX_NODE_NO_SHIFT) - 1);
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}
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/**
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* Returns the number of bits set in the provided value.
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* Simple wrapper for POP instruction.
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@ -448,8 +464,15 @@ static inline uint64_t cvmx_get_cycle_global(void)
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/* Return the number of cores available in the chip */
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static inline uint32_t cvmx_octeon_num_cores(void)
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{
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uint32_t ciu_fuse = (uint32_t) cvmx_read_csr(CVMX_CIU_FUSE) & 0xffff;
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return cvmx_pop(ciu_fuse);
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u64 ciu_fuse_reg;
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u64 ciu_fuse;
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if (OCTEON_IS_OCTEON3() && !OCTEON_IS_MODEL(OCTEON_CN70XX))
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ciu_fuse_reg = CVMX_CIU3_FUSE;
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else
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ciu_fuse_reg = CVMX_CIU_FUSE;
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ciu_fuse = cvmx_read_csr(ciu_fuse_reg);
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return cvmx_dpop(ciu_fuse);
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}
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#endif /* __CVMX_H__ */
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@ -81,6 +81,10 @@ enum octeon_feature {
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OCTEON_FEATURE_HFA,
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OCTEON_FEATURE_DFM,
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OCTEON_FEATURE_CIU2,
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OCTEON_FEATURE_CIU3,
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/* Octeon has FPA first seen on 78XX */
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OCTEON_FEATURE_FPA3,
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OCTEON_FEATURE_FAU,
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OCTEON_MAX_FEATURE
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};
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@ -110,7 +114,7 @@ static inline int octeon_has_crypto(void)
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* Returns Non zero if the feature exists. Zero if the feature does not
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* exist.
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*/
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static inline int octeon_has_feature(enum octeon_feature feature)
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static inline bool octeon_has_feature(enum octeon_feature feature)
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{
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switch (feature) {
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case OCTEON_FEATURE_SAAD:
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@ -122,7 +126,7 @@ static inline int octeon_has_feature(enum octeon_feature feature)
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fus_2.u64 = cvmx_read_csr(CVMX_MIO_FUS_DAT2);
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return !fus_2.s.nocrypto && !fus_2.s.nomul && fus_2.s.dorm_crypto;
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} else {
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return 0;
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return false;
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}
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case OCTEON_FEATURE_PCIE:
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@ -190,11 +194,20 @@ static inline int octeon_has_feature(enum octeon_feature feature)
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case OCTEON_FEATURE_CIU2:
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return OCTEON_IS_MODEL(OCTEON_CN68XX);
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case OCTEON_FEATURE_CIU3:
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case OCTEON_FEATURE_FPA3:
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return OCTEON_IS_MODEL(OCTEON_CN78XX)
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|| OCTEON_IS_MODEL(OCTEON_CNF75XX)
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|| OCTEON_IS_MODEL(OCTEON_CN73XX);
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case OCTEON_FEATURE_FAU:
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return !(OCTEON_IS_MODEL(OCTEON_CN78XX)
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|| OCTEON_IS_MODEL(OCTEON_CNF75XX)
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|| OCTEON_IS_MODEL(OCTEON_CN73XX));
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default:
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break;
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}
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return 0;
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return false;
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}
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#endif /* __OCTEON_FEATURE_H__ */
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@ -74,7 +74,12 @@
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* CN7XXX models with new revision encoding
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*/
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#define OCTEON_CNF75XX_PASS1_0 0x000d9800
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#define OCTEON_CNF75XX (OCTEON_CNF75XX_PASS1_0 | OM_IGNORE_REVISION)
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#define OCTEON_CNF75XX_PASS1_X (OCTEON_CNF75XX_PASS1_0 | OM_IGNORE_MINOR_REVISION)
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#define OCTEON_CN73XX_PASS1_0 0x000d9700
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#define OCTEON_CN73XX_PASS1_1 0x000d9701
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#define OCTEON_CN73XX (OCTEON_CN73XX_PASS1_0 | OM_IGNORE_REVISION)
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#define OCTEON_CN73XX_PASS1_X (OCTEON_CN73XX_PASS1_0 | \
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OM_IGNORE_MINOR_REVISION)
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