Commit Graph

710 Commits

Author SHA1 Message Date
Arnd Bergmann
0df88121fb mvebu dt64 for 4.8 (part 1)
- update dt with mv-xor-v2 found in the Armada 7K/8K SoCs
 - update dt with the clocks found in the Armada 3700 SoCs
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Merge tag 'mvebu-dt64-4.8-1' of git://git.infradead.org/linux-mvebu into next/dt64

Merge "mvebu dt64 for 4.8 (part 1)" from Gregory CLEMENT:

- update dt with mv-xor-v2 found in the Armada 7K/8K SoCs
- update dt with the clocks found in the Armada 3700 SoCs

* tag 'mvebu-dt64-4.8-1' of git://git.infradead.org/linux-mvebu:
  arm64: dts: marvell: add peripherals clocks for Armada 37xx
  arm64: dts: marvell: add tbg clocks for Armada 37xx
  arm64: dts: marvell: Add xtal clock support for Armada 3700
  arm64: dts: marvell: add XOR engine description for Armada 7K/8K CP
  arm64: dts: marvell: adjust to the latest mv-xor-v2 DT binding
2016-07-07 14:18:17 +02:00
Arnd Bergmann
c8a12c063b - Add nodes for the DISP function ports
- Add dt-bindings for mt6755
 - Add basic support for mt6755 SoC
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Merge tag 'v4.7-next-dts' of https://github.com/mbgg/linux-mediatek into next/dt64

Merge "ARM: mediatek: dts 64 bit updates for v4.8" from Matthias Brugger:

- Add nodes for the DISP function ports
- Add dt-bindings for mt6755
- Add basic support for mt6755 SoC

* tag 'v4.7-next-dts' of https://github.com/mbgg/linux-mediatek:
  arm64: dts: mediatek: add mt6755 support
  Document: DT: Add bindings for mediatek MT6755 SoC Platform
  arm64: dts: mt8173: Add display subsystem related nodes
2016-07-07 13:58:44 +02:00
Olof Johansson
135a2f38fa The rk3399 gets support for its emmc controller as well as thermal,
i2c and core io-domain nodes and some reasonable default rates
 for core clocks. The rk3368 also gets io-domains for its r88 board
 as well as a small fix for the gic's memory regions.
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Merge tag 'v4.8-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/dt64

The rk3399 gets support for its emmc controller as well as thermal,
i2c and core io-domain nodes and some reasonable default rates
for core clocks. The rk3368 also gets io-domains for its r88 board
as well as a small fix for the gic's memory regions.

* tag 'v4.8-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  arm64: dts: rockchip: add ap_pwroff and ddrio_pwroff pins for rk3399
  arm64: dts: rockchip: Provide emmcclk to PHY for rk3399
  arm64: dts: rockchip: Add soc-ctl-syscon to sdhci for rk3399
  arm64: dts: rockchip: fixes the gic400 2nd region size for rk3368
  arm64: dts: rockchip: add i2c nodes for rk3399
  arm64: dts: rockchip: add thermal nodes for rk3399 SoCs
  arm64: dts: rockchip: add rk3399 io-domain core nodes
  arm64: dts: rockchip: add rk3368-r88 iodomains
  arm64: dts: rockchip: add rk3368 io-domain core nodes
  arm64: dts: rockchip: make rk3368 grf syscons simple-mfds
  arm64: dts: rockchip: enable eMMC for rk3399 EVB
  arm64: dts: rockchip: add sdhci/emmc for rk3399
  arm64: dts: rockchip: make rk3399's grf a "simple-mfd"
  arm64: dts: rockchip: assign default rates for core rk3399 clocks

Signed-off-by: Olof Johansson <olof@lixom.net>
2016-07-06 22:23:27 -07:00
Olof Johansson
7f95b51d54 ARM64: DT: Hisilicon Hi6220 hikey board updates for 4.8
- name the GPIO lines
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Merge tag 'hi6220-dt-for-4.8' of git://github.com/hisilicon/linux-hisi into next/dt64

ARM64: DT: Hisilicon Hi6220 hikey board updates for 4.8

- name the GPIO lines

* tag 'hi6220-dt-for-4.8' of git://github.com/hisilicon/linux-hisi:
  arm64: dts: hikey: name the GPIO lines

Signed-off-by: Olof Johansson <olof@lixom.net>
2016-07-05 21:47:46 -07:00
Olof Johansson
1fa04d923c The Freescale arm64 device tree updates for 4.8:
- Update address-cells and reg properties of cpu nodes, considering
    MPIDR_EL1[63:32] bits are not used for CPUs identification on ls1043a
    and ls2080a
  - Adds the cache nodes and next-level-cache property for ls1043a and
    ls2080a to get cacheinfo work on these platforms
  - Add dma-coherent for ls1043a PCI nodes to utilize the hardware
    capability on data coherency
  - Add dis_rxdet_inp3_quirk property for USB3 device to disable rx
    detection in P3 PHY mode
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Merge tag 'imx-dt64-4.8' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/dt64

The Freescale arm64 device tree updates for 4.8:
 - Update address-cells and reg properties of cpu nodes, considering
   MPIDR_EL1[63:32] bits are not used for CPUs identification on ls1043a
   and ls2080a
 - Adds the cache nodes and next-level-cache property for ls1043a and
   ls2080a to get cacheinfo work on these platforms
 - Add dma-coherent for ls1043a PCI nodes to utilize the hardware
   capability on data coherency
 - Add dis_rxdet_inp3_quirk property for USB3 device to disable rx
   detection in P3 PHY mode

* tag 'imx-dt64-4.8' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
  arm64: dts: ls2080a: Add cache nodes for cacheinfo support
  arm64: dts: ls1043a: Add cache nodes for cacheinfo support
  arm64: dts: ls1043a: Add 'dma-coherent' for ls1043a PCI nodes
  bindings: PCI: layerscape: Add 'dma-coherent' property
  arm64: dts: ls1043a: Add dis_rxdet_inp3_quirk property to USB3 node
  arm64: dts: ls2080a: Add dis_rxdet_inp3_quirk property to USB3 node
  arm64: dts: fsl: Update address-cells and reg properties of cpu nodes

Signed-off-by: Olof Johansson <olof@lixom.net>
2016-07-05 21:10:09 -07:00
Olof Johansson
87040f7c96 Qualcomm ARM64 Updates for v4.8
* Enable assorted peripherals on APQ8016 SBC
 * Update reserved memory on MSM8916
 * Add MSM8996 peripheral support
 * Add SCM firmware node on MSM8916
 * Add PMU node on MSM8916
 * Add PSCI cpuidle support on MSM8916
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Merge tag 'qcom-arm64-for-4.8' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux into next/dt64

Qualcomm ARM64 Updates for v4.8

* Enable assorted peripherals on APQ8016 SBC
* Update reserved memory on MSM8916
* Add MSM8996 peripheral support
* Add SCM firmware node on MSM8916
* Add PMU node on MSM8916
* Add PSCI cpuidle support on MSM8916

* tag 'qcom-arm64-for-4.8' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux: (22 commits)
  arm64: dts: msm8996: add sdc2 support
  arm64: dts: msm8996: add sdc2 pinctrl
  arm64: dts: msm8996: add support to blsp2_spi5
  arm64: dts: msm8996: add support to blsp2_spi5 pinctrl
  arm64: dts: msm8996: add support to blsp1_spi0
  arm64: dts: msm8996: add support to blsp1_spi0 pinctrl
  arm64: dts: msm8996: add support to blsp2_i2c0
  arm64: dts: msm8996: add support to blsp2_i2c0 pinctrl
  arm64: dts: msm8996: add support to blsp2_i2c1
  arm64: dts: msm8996: add blsp2_i2c1 pinctrl
  arm64: dts: msm8996: add support to blsp1_i2c2 device
  arm64: dts: msm8996: add blsp1_i2c2 pinctrl nodes.
  arm64: dts: msm8996: add support blsp2_uart2
  arm64: dts: msm8996: add blsp2_uart2 pinctrl nodes.
  arm64: dts: msm8996: add blsp2_uart1 pinctrl
  arm64: dts: msm8996: add msmgpio label
  ARM: dts: msm8916: Update reserved-memory
  arm64: dts: msm8916: Add SCM firmware node
  arm64: dts: qcom: Add msm8916 PMU node
  ARM64: dts: Add PSCI cpuidle support for MSM8916
  ...

Signed-off-by: Olof Johansson <olof@lixom.net>
2016-07-04 22:24:30 -07:00
Olof Johansson
b6aec2b94d First part of X-Gene DTS changes queued for v4.8
The changes include:
 + 2 clean-up and style-fix patches from Bjorn
 + Correct timer interrupt polarity for X-Gene 2
 + Remove unused qmlclk node on X-Gene 1
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Merge tag 'xgene-dts-for-v4.8-part1' of https://github.com/AppliedMicro/xgene-next into next/dt64

First part of X-Gene DTS changes queued for v4.8

The changes include:
+ 2 clean-up and style-fix patches from Bjorn
+ Correct timer interrupt polarity for X-Gene 2
+ Remove unused qmlclk node on X-Gene 1

* tag 'xgene-dts-for-v4.8-part1' of https://github.com/AppliedMicro/xgene-next:
  arm64: dts: apm: Remove unused qmlclk node on X-Gene 1
  arm64: dts: apm: Fix timer interrupt polarity for X-Gene 2 SoC
  arm64: dts: apm: Remove leading '0x' from unit addresses
  arm64: dts: apm: Use lowercase consistently for hex constants

Signed-off-by: Olof Johansson <olof@lixom.net>
2016-07-04 21:33:31 -07:00
Gregory CLEMENT
5f4beef6db arm64: dts: marvell: add peripherals clocks for Armada 37xx
Add two new blocks of clocks. The peripheral clocks are the source clocks
of the peripheral of the Armada 3700 SoC.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2016-07-04 22:21:13 +02:00
Gregory CLEMENT
e3e1a55eda arm64: dts: marvell: add tbg clocks for Armada 37xx
Add a new block of clocks. The Time Base Generators clocks can be the
parent of the peripheral clocks.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2016-07-04 22:21:03 +02:00
Gregory CLEMENT
ddeba40b05 arm64: dts: marvell: Add xtal clock support for Armada 3700
The configuration of the clock depend of the gpio latch. This information
is stored in the gpio block registers. That's why the block is shared
using a syscon node.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2016-07-04 22:19:34 +02:00
Mars Cheng
aea1c315b6 arm64: dts: mediatek: add mt6755 support
This adds basic chip support for MT6755 SoC.

Signed-off-by: Mars Cheng <mars.cheng@mediatek.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2016-07-03 07:57:21 +02:00
Thomas Petazzoni
c7f2735547 arm64: dts: marvell: add XOR engine description for Armada 7K/8K CP
This commit adds the Device Tree description for the two XOR engines
found in the CP part of the Armada 7K/8K SoC.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2016-06-30 13:50:30 +02:00
Thomas Petazzoni
7eec659478 arm64: dts: marvell: adjust to the latest mv-xor-v2 DT binding
As suggested by Rob Herring, we should:

 1/ Use a SoC-specific compatible string in addition to the more generic
    one.

 2/ The generic compatible string has been changed from
    "marvell,mv-xor-v2" to "marvell,xor-v2".

We simply reflect the changes made to the Device Tree bindings to the
relevant Marvell 7K/8K Device Tree files.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2016-06-30 13:49:55 +02:00
Linus Walleij
bbaf867e2d arm64: dts: hikey: name the GPIO lines
This names the GPIO lines on the HiKey board in accordance with
the 96Board Specification for especially the Low Speed External
Connector: "GPIO-A" thru "GPIO-L".

This will make these line names reflect through to userspace
so that they can easily be identified and used with the new
character device ABI.

Some care has been taken to name all lines, not just those used
by the external connectors, also lines that are muxed into some
other function than GPIO: these are named "[FOO]" so that users
can see with lsgpio what all lines are used for.

Cc: devicetree@vger.kernel.org
Cc: John Stultz <john.stultz@linaro.org>
Cc: Rob Herring <robh@kernel.org>
Cc: David Mandala <david.mandala@linaro.org>
Cc: Haojian Zhuang <haojian.zhuang@linaro.org>
Cc: Wei Xu <xuwei5@hisilicon.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2016-06-28 17:36:04 +01:00
Douglas Anderson
5d26ad9cfb arm64: dts: rockchip: add ap_pwroff and ddrio_pwroff pins for rk3399
There are two sleep related pins on rk3399: ap_pwroff and ddrio_pwroff.
Let's add the definition of these two pins to rk3399's main dtsi file so
that boards can use them.

These two pins are similar to the global_pwroff and ddrio_pwroff pins in
rk3288 and are expected to be used in the same way: boards will likely
want to configure these pinctrl settings in their global pinctrl hog
list.

Note that on rk3288 there were two additional pins in the "sleep"
section: "ddr0_retention" and "ddr1_retention".  On rk3288 designs these
pins appeared to actually route from rk3288 back to rk3288.  Presumably
on rk3399 this is simply not needed since the pins don't appear to exist
there.

Signed-off-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-06-27 01:07:40 +02:00
Srinivas Kandagatla
a670279898 arm64: dts: msm8996: add sdc2 support
This patch adds support to sdc2 sdhci controller, which is used on some
of the boards.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
2016-06-24 22:30:17 -05:00
Srinivas Kandagatla
84ddf1ee1e arm64: dts: msm8996: add sdc2 pinctrl
This patch adds pinctrl required for sdhci for external sd card
controller.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
2016-06-24 22:30:17 -05:00
Srinivas Kandagatla
db6c8c8325 arm64: dts: msm8996: add support to blsp2_spi5
This patch adds support to blsp2_spi5 device, which is used in some of
the APQ8096 based boards.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
2016-06-24 22:30:17 -05:00
Srinivas Kandagatla
7dba64a23e arm64: dts: msm8996: add support to blsp2_spi5 pinctrl
This patch adds pinctrl required for blsp2_spi5 device.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
2016-06-24 22:30:17 -05:00
Srinivas Kandagatla
604677b415 arm64: dts: msm8996: add support to blsp1_spi0
This patch adds support to blsp1_spi0 which is used on some of APQ8096
based boards.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
2016-06-24 22:30:17 -05:00
Srinivas Kandagatla
9f05d8ff8a arm64: dts: msm8996: add support to blsp1_spi0 pinctrl
This patch adds pinctrl nodes required for blsp1_spi0.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
2016-06-24 22:30:17 -05:00
Srinivas Kandagatla
bf5443bcaa arm64: dts: msm8996: add support to blsp2_i2c0
This patch adds support to blsp2_i2c0, which is used on some of the
APQ8096 based boards.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
2016-06-24 22:30:17 -05:00
Srinivas Kandagatla
e25d57c106 arm64: dts: msm8996: add support to blsp2_i2c0 pinctrl
This patch adds support to blsp2_i2c0 pinctrl.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
2016-06-24 22:30:17 -05:00
Srinivas Kandagatla
d41d0cee9a arm64: dts: msm8996: add support to blsp2_i2c1
This patch adds support to blsp2_i2c1, which is used in one of the
apq8096 based boards.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
2016-06-24 22:30:16 -05:00
Srinivas Kandagatla
0e7f196083 arm64: dts: msm8996: add blsp2_i2c1 pinctrl
This patch adds support to blsp2_i2c1 pinctrl nodes.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
2016-06-24 22:30:16 -05:00
Srinivas Kandagatla
21a4038461 arm64: dts: msm8996: add support to blsp1_i2c2 device
This patch adds blsp1_i2c2 support, as this bus is used on some of the
apq8096 boards.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
2016-06-24 22:30:16 -05:00
Srinivas Kandagatla
5f9d54ffc1 arm64: dts: msm8996: add blsp1_i2c2 pinctrl nodes.
This patch adds pinctrl nodes required for blsp1_i2c2.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
2016-06-24 22:30:16 -05:00
Srinivas Kandagatla
fda48e6109 arm64: dts: msm8996: add support blsp2_uart2
This patch adds bslp2_uart2 node in soc so that boards that use this
uart can enable it.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
2016-06-24 22:30:16 -05:00
Srinivas Kandagatla
96f86b7d68 arm64: dts: msm8996: add blsp2_uart2 pinctrl nodes.
This patch adds blsp2_uart2 pinctrl nodes.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
2016-06-24 22:30:16 -05:00
Srinivas Kandagatla
22e6789f94 arm64: dts: msm8996: add blsp2_uart1 pinctrl
This patch adds 2pin and 4 pin uart pinctrl support for blsp2_uart1

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
2016-06-24 22:30:16 -05:00
Srinivas Kandagatla
84361086df arm64: dts: msm8996: add msmgpio label
This patch adds msmgpio label for pin and gpio controller so that
it can referenced in dedicated pins file and other board level gpios.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
2016-06-24 22:30:16 -05:00
Douglas Anderson
ed388cdd2e arm64: dts: rockchip: Provide emmcclk to PHY for rk3399
Previous changes in this series allowed exposing the card clock from the
rk3399 SDHCI device and allowed consuming the card clock in the rk3399
eMMC PHY.  Hook things up in the main rk3399 dtsi file.

Signed-off-by: Douglas Anderson <dianders@chromium.org>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-06-22 18:24:33 +02:00
Douglas Anderson
64e3481c8a arm64: dts: rockchip: Add soc-ctl-syscon to sdhci for rk3399
On rk3399 we'd like to be able to properly set corecfg registers in the
Arasan SDHCI component.  Specify the syscon to enable that.

Signed-off-by: Douglas Anderson <dianders@chromium.org>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-06-22 18:24:05 +02:00
Li Yang
2983e625bf arm64: dts: ls2080a: Add cache nodes for cacheinfo support
Adds the cache nodes and next-level-cache property for the
cacheinfo to work.

Signed-off-by: Li Yang <leoyang.li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-06-21 14:33:34 +08:00
Li Yang
ec049f3348 arm64: dts: ls1043a: Add cache nodes for cacheinfo support
Adds the cache nodes and next-level-cache property for the
cacheinfo to work.

Signed-off-by: Li Yang <leoyang.li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-06-21 14:33:30 +08:00
Duc Dang
ddbc71d960 arm64: dts: apm: Remove unused qmlclk node on X-Gene 1
Node qmlclk has no consumer, so remove it.

Signed-off-by: Duc Dang <dhdang@apm.com>
2016-06-20 18:41:49 -07:00
Duc Dang
f0a78909bd arm64: dts: apm: Fix timer interrupt polarity for X-Gene 2 SoC
Correct X-Gene 2 timer interrupt polarity as low-level triggered.

Signed-off-by: Duc Dang <dhdang@apm.com>
2016-06-20 18:26:35 -07:00
Bjorn Helgaas
0e999c79c0 arm64: dts: apm: Remove leading '0x' from unit addresses
Unit addresses should not have a leading '0x'.  Remove them.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Duc Dang <dhdang@apm.com>
2016-06-20 18:15:25 -07:00
Bjorn Helgaas
cafc4cd0c8 arm64: dts: apm: Use lowercase consistently for hex constants
The convention in these files is to use lowercase for "0x" prefixes and for
the hex constants themselves, but a few changes didn't follow that
convention, which makes the file annoying to read.

Use lowercase consistently for the hex constants.  No functional change
intended.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Duc Dang <dhdang@apm.com>
2016-06-20 18:13:54 -07:00
Olof Johansson
7a4fad480d This pull request contains Device Tree changes for Broadcom ARM64-based SoCS:
- Anup adds nodes for the AHCI and SATA3 PHY peripherals to the Northstar2 SoCs
 
 - Dhanajay enables pinctrl for the Northstar2 SoCs
 
 - Jon Mason enables all of the UART peripherals found in the NS2 SVK and
   finally adds the CCI-400 and PMU nodes
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Merge tag 'arm-soc/for-4.8/devicetree-arm64' of http://github.com/Broadcom/stblinux into next/dt64

This pull request contains Device Tree changes for Broadcom ARM64-based SoCS:

- Anup adds nodes for the AHCI and SATA3 PHY peripherals to the Northstar2 SoCs

- Dhanajay enables pinctrl for the Northstar2 SoCs

- Jon Mason enables all of the UART peripherals found in the NS2 SVK and
  finally adds the CCI-400 and PMU nodes

* tag 'arm-soc/for-4.8/devicetree-arm64' of http://github.com/Broadcom/stblinux:
  arm64: dts: NS2: Add CCI-400 PMU support
  arm64: dts: NS2: Add all of the UARTs
  arm64: dts: Enable GPIO for Broadcom NS2 SoC
  arm64: dts: enable pinctrl for Broadcom NS2 SoC
  arm64: dts: Add SATA3 AHCI and SATA3 PHY DT nodes for NS2
  dt-bindings: ata: add compatible string for iProc AHCI controller

Signed-off-by: Olof Johansson <olof@lixom.net>
2016-06-19 22:48:17 -07:00
Olof Johansson
4fb92c60eb Amlogic DT 64-bit changes for v4.8
- add pinctrl driver and pins for several devices
 - add reset driver
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Merge tag 'amlogic-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into next/dt64

Amlogic DT 64-bit changes for v4.8
- add pinctrl driver and pins for several devices
- add reset driver

* tag 'amlogic-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic:
  ARM64: dts: amlogic: Enable Reset Controller on GXBB-based platforms
  ARM64: dts: amlogic: gxbb: add ethernet
  ARM64: dts: amlogic: gxbb: pinctrl: add/update UART
  ARM64: dts: amlogic: add pins for EMMC, SD
  ARM64: dts: amlogic: Enable pin controller on GXBB-based platforms
  documentation: Add compatibles for Amlogic Meson GXBB pin controllers
  ARM64: dts: amlogic: Add hiu and periphs buses

Signed-off-by: Olof Johansson <olof@lixom.net>
2016-06-19 22:30:16 -07:00
Caesar Wang
ad1cfdf518 arm64: dts: rockchip: fixes the gic400 2nd region size for rk3368
The 2nd additional region is the GIC virtual cpu interface register
base and size.

As the gic400 of rk3368 says, the cpu interface register map as below

:

-0x0000 GICC_CTRL
.
.
.
-0x00fc GICC_IIDR
-0x1000 GICC_IDR

Obviously, the region size should be greater than 0x1000.
So we should make sure to include the GICC_IDR since the kernel will access
it in some cases.

Fixes: b790c2cab5 ("arm64: dts: add Rockchip rk3368 core dtsi and board dts for the r88 board")
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com>
Cc: stable@vger.kernel.org

[added Fixes and stable-cc]
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-06-18 14:54:23 +02:00
David Wu
69e5a8fe8c arm64: dts: rockchip: add i2c nodes for rk3399
We've got 9 (count em!) i2c controllers on rk3399, some of which are in
the PMU power domain and some of which are normal peripherals.  Add them
all to the main rk3399 dtsi file so future patches can turn them on in
the board dts files.

Note: by default we try to set the i2c clock rate to 200 MHz so that we
can achieve good i2c functional clock rates.  200 MHz gives us the
ability to make very close to 100 kHz / 400 kHz / 1 MHz rates.  If
boards want to tune clock rates further they can always override.
Possibly boards could want to tune this if:
- they wanted to save an infinitesimal amount of power and they knew
  their i2c bus was slow anyway.  Since we gate the functional clock
  when the i2c bus is not active, power savings would only be while i2c
  transfers were happening and probably won't be very big anyway.
- they wanted to eek out a bit more speed by carefully tuning the source
  clock to make divisions work out perfectly, accounting for the rise /
  fall time measured on an actual board.

Note also that we still request 200 MHz for the PMU i2c busses even
though we expect that we won't make that exactly (currently PPLL is 676
MHz which gives us 169 MHz).

Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
[dianders: wrote desc; put in assigned-clocks; reordered nodes]
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-06-18 14:00:23 +02:00
Liu Gang
f8ed1d9b0f arm64: dts: ls1043a: Add 'dma-coherent' for ls1043a PCI nodes
The 'dma-coherent' indicates that the hardware IP block can ensure
the coherency of the data transferred from/to the IP block. This
can avoid the software cache flush/invalid actions, and improve
the performance significantly.

The PCI IP block of ls1043a has this capability, so adding this
feature to improve the PCI performance.

Signed-off-by: Liu Gang <Gang.Liu@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-06-16 08:43:10 +08:00
Masahiro Yamada
ffd8a5ed57 arm64: dts: uniphier: add /memreserve/ for spin-table release address
As Documentation/arm64/booting.txt says, the cpu-release-addr
location should be reserved.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
2016-06-14 10:40:31 -07:00
Masahiro Yamada
1388ea2a8d arm64: dts: uniphier: change cpu-release-address
At first, 256 byte of the head of DRAM space was reserved for some
reasons.  However, as the progress of development, it turned out
unnecessary, and it was never used in the end.  Move the CPU release
address to leave no space.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
2016-06-14 10:40:29 -07:00
Masahiro Yamada
ed6cca5f9a arm64: dts: uniphier: add SoC-Glue node to UniPhier 64bit SoCs
This node consists of various system-level configuration registers.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
2016-06-14 10:40:15 -07:00
Olof Johansson
045ab0c54c Renesas ARM64 Based SoC DT Updates for v4.8
* Fix W=1 dtc warnings and other cleanups
 * Enable watchdog timer
 * Enable DMA for I2C
 * Increase the size of GIC-400 mapped registers: be nicer to hypervisors
 * Support RTS/CTS hardware flow control
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Merge tag 'renesas-arm64-dt-for-v4.8' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt64

Renesas ARM64 Based SoC DT Updates for v4.8

* Fix W=1 dtc warnings and other cleanups
* Enable watchdog timer
* Enable DMA for I2C
* Increase the size of GIC-400 mapped registers: be nicer to hypervisors
* Support RTS/CTS hardware flow control

* tag 'renesas-arm64-dt-for-v4.8' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
  arm64: dts: r8a7795: Drop 0x from unit address of gic
  arm64: dts: salvator-x: Fix W=1 dtc warnings
  arm64: dts: r8a7795: Fix W=1 dtc warnings
  arm64: dts: r8a7795: Use SYSC "always-on" PM Domain for RWDT node
  arm64: dts: salvator-x: Enable watchdog timer
  arm64: dts: r8a7795: Add RWDT node
  arm64: dts: r8a7795: enable DMA for I2C
  arm64: dts: r8a7795: Increase the size of GIC-400 mapped registers
  arm64: dts: salvator-x: SCIF1 supports RTS/CTS hardware flow control

Signed-off-by: Olof Johansson <olof@lixom.net>
2016-06-13 15:29:12 -07:00
Bjorn Andersson
7258e10e6a ARM: dts: msm8916: Update reserved-memory
Update reserved-memory in accordance with memory the detailed memory map
for 8916, so that we will be able to reference the firmware memory
regions.

Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
2016-06-12 00:48:11 -05:00
Andy Gross
ea49e164b5 arm64: dts: msm8916: Add SCM firmware node
This adds the devicetree node for the SCM firmware.

Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
2016-06-12 00:48:11 -05:00