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SoCFPGA DTS updates for v4.3

Browse Source 
- Update clocking for DTS nodes
 - Add DTS board file for Terasic DE0 Atlas board
 - Use stdout-patch for chosen node
 - Enable prefetch-data and prefetch-instr
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Merge tag 'socfpga_dts_for_v4.3' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into next/dt

SoCFPGA DTS updates for v4.3
- Update clocking for DTS nodes
- Add DTS board file for Terasic DE0 Atlas board
- Use stdout-patch for chosen node
- Enable prefetch-data and prefetch-instr

* tag 'socfpga_dts_for_v4.3' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux:
  ARM: socfpga: dts: add osc1 as a possible parent for dbg_base_clk
  ARM: socfpga: dts: add missing clock gates to socfpga.dtsi
  ARM: socfpga: dts: Fix gpio dts entry for the correct clock
  ARM: socfpga: dts: Correct the parent clock for l3_sp_clk and dbg_clk
  ARM: dts: socfpga: Add support of Terasic DE0 Atlas board
  ARM: dts: socfpga: use stdout-path for chosen node
  ARM: dts: socfpga: enable the data and instruction prefetch for the l2 cache

Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson 2015-07-28 18:25:39 +02:00
commit 46a51abbda
8 changed files with 163 additions and 11 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
arch/arm/boot/dts/Makefile
View File

@ -536,6 +536,7 @@ dtb-$(CONFIG_ARCH_SOCFPGA) += \
socfpga_arria5_socdk.dtb \
socfpga_arria10_socdk_sdmmc.dtb \
socfpga_cyclone5_socdk.dtb \
socfpga_cyclone5_de0_sockit.dtb \
socfpga_cyclone5_sockit.dtb \
socfpga_cyclone5_socrates.dtb \
socfpga_vt.dtb

45
arch/arm/boot/dts/socfpga.dtsi
View File

@ -164,7 +164,7 @@ mainclk: mainclk {
dbg_base_clk: dbg_base_clk {
#clock-cells = <0>;
compatible = "altr,socfpga-perip-clk";
clocks = <&main_pll>;
clocks = <&main_pll>, <&osc1>;
div-reg = <0xe8 0 9>;
reg = <0x50>;
};
@ -318,7 +318,7 @@ l3_mp_clk: l3_mp_clk {
l3_sp_clk: l3_sp_clk {
#clock-cells = <0>;
compatible = "altr,socfpga-gate-clk";
clocks = <&mainclk>;
clocks = <&l3_mp_clk>;
div-reg = <0x64 2 2>;
};
@ -349,7 +349,7 @@ dbg_at_clk: dbg_at_clk {
dbg_clk: dbg_clk {
#clock-cells = <0>;
compatible = "altr,socfpga-gate-clk";
clocks = <&dbg_base_clk>;
clocks = <&dbg_at_clk>;
div-reg = <0x68 2 2>;
clk-gate = <0x60 5>;
};
@ -481,8 +481,37 @@ qspi_clk: qspi_clk {
clocks = <&f2s_periph_ref_clk>, <&main_qspi_clk>, <&per_qspi_clk>;
clk-gate = <0xa0 11>;
};
ddr_dqs_clk_gate: ddr_dqs_clk_gate {
#clock-cells = <0>;
compatible = "altr,socfpga-gate-clk";
clocks = <&ddr_dqs_clk>;
clk-gate = <0xd8 0>;
};
ddr_2x_dqs_clk_gate: ddr_2x_dqs_clk_gate {
#clock-cells = <0>;
compatible = "altr,socfpga-gate-clk";
clocks = <&ddr_2x_dqs_clk>;
clk-gate = <0xd8 1>;
};
ddr_dq_clk_gate: ddr_dq_clk_gate {
#clock-cells = <0>;
compatible = "altr,socfpga-gate-clk";
clocks = <&ddr_dq_clk>;
clk-gate = <0xd8 2>;
};
h2f_user2_clk: h2f_user2_clk {
#clock-cells = <0>;
compatible = "altr,socfpga-gate-clk";
clocks = <&h2f_usr2_clk>;
clk-gate = <0xd8 3>;
};
};
};
};
gmac0: ethernet@ff700000 {
compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
@ -565,7 +594,7 @@ gpio0: gpio@ff708000 {
#size-cells = <0>;
compatible = "snps,dw-apb-gpio";
reg = <0xff708000 0x1000>;
clocks = <&per_base_clk>;
clocks = <&l4_mp_clk>;
status = "disabled";
porta: gpio-controller@0 {
@ -585,7 +614,7 @@ gpio1: gpio@ff709000 {
#size-cells = <0>;
compatible = "snps,dw-apb-gpio";
reg = <0xff709000 0x1000>;
clocks = <&per_base_clk>;
clocks = <&l4_mp_clk>;
status = "disabled";
portb: gpio-controller@0 {
@ -605,7 +634,7 @@ gpio2: gpio@ff70a000 {
#size-cells = <0>;
compatible = "snps,dw-apb-gpio";
reg = <0xff70a000 0x1000>;
clocks = <&per_base_clk>;
clocks = <&l4_mp_clk>;
status = "disabled";
portc: gpio-controller@0 {
@ -639,6 +668,8 @@ L2: l2-cache@fffef000 {
cache-level = <2>;
arm,tag-latency = <1 1 1>;
arm,data-latency = <2 1 1>;
prefetch-data = <1>;
prefetch-instr = <1>;
};
mmc: dwmmc0@ff704000 {

5
arch/arm/boot/dts/socfpga_arria10.dtsi
View File

@ -21,6 +21,11 @@ / {
#address-cells = <1>;
#size-cells = <1>;
aliases {
serial0 = &uart0;
serial1 = &uart1;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;

3
arch/arm/boot/dts/socfpga_arria10_socdk.dtsi
View File

@ -21,7 +21,8 @@ / {
compatible = "altr,socfpga-arria10", "altr,socfpga";
chosen {
bootargs = "console=ttyS0,115200 rootwait";
bootargs = "earlyprintk";
stdout-path = "serial1:115200n8";
};
memory {

3
arch/arm/boot/dts/socfpga_arria5_socdk.dts
View File

@ -22,7 +22,8 @@ / {
compatible = "altr,socfpga-arria5", "altr,socfpga";
chosen {
bootargs = "console=ttyS0,115200";
bootargs = "earlyprintk";
stdout-path = "serial0:115200n8";
};
memory {

111
arch/arm/boot/dts/socfpga_cyclone5_de0_sockit.dts Normal file
View File

@ -0,0 +1,111 @@
/*
* Copyright Altera Corporation (C) 2015. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include "socfpga_cyclone5.dtsi"
/ {
model = "Terasic DE-0(Atlas)";
compatible = "altr,socfpga-cyclone5", "altr,socfpga";
chosen {
bootargs = "earlyprintk";
stdout-path = "serial0:115200n8";
};
memory {
name = "memory";
device_type = "memory";
reg = <0x0 0x40000000>; /* 1GB */
};
aliases {
ethernet0 = &gmac1;
};
regulator_3_3v: 3-3-v-regulator {
compatible = "regulator-fixed";
regulator-name = "3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
leds {
compatible = "gpio-leds";
hps0 {
label = "hps_led0";
gpios = <&portb 24 0>;
linux,default-trigger = "heartbeat";
};
};
};
&gmac1 {
status = "okay";
phy-mode = "rgmii";
txd0-skew-ps = <0>; /* -420ps */
txd1-skew-ps = <0>; /* -420ps */
txd2-skew-ps = <0>; /* -420ps */
txd3-skew-ps = <0>; /* -420ps */
rxd0-skew-ps = <420>; /* 0ps */
rxd1-skew-ps = <420>; /* 0ps */
rxd2-skew-ps = <420>; /* 0ps */
rxd3-skew-ps = <420>; /* 0ps */
txen-skew-ps = <0>; /* -420ps */
txc-skew-ps = <1860>; /* 960ps */
rxdv-skew-ps = <420>; /* 0ps */
rxc-skew-ps = <1680>; /* 780ps */
max-frame-size = <3800>;
};
&gpio0 {
status = "okay";
};
&gpio1 {
status = "okay";
};
&gpio2 {
status = "okay";
};
&i2c0 {
status = "okay";
speed-mode = <0>;
adxl345: adxl345@0 {
compatible = "adi,adxl345";
reg = <0x53>;
interrupt-parent = <&portc>;
interrupts = <3 2>;
};
};
&mmc0 {
vmmc-supply = <&regulator_3_3v>;
vqmmc-supply = <&regulator_3_3v>;
};
&uart0 {
status = "okay";
};
&usb1 {
status = "okay";
};

3
arch/arm/boot/dts/socfpga_cyclone5_socdk.dts
View File

@ -22,7 +22,8 @@ / {
compatible = "altr,socfpga-cyclone5", "altr,socfpga";
chosen {
bootargs = "console=ttyS0,115200";
bootargs = "earlyprintk";
stdout-path = "serial0:115200n8";
};
memory {

3
arch/arm/boot/dts/socfpga_cyclone5_sockit.dts
View File

@ -22,7 +22,8 @@ / {
compatible = "altr,socfpga-cyclone5", "altr,socfpga";
chosen {
bootargs = "console=ttyS0,115200";
bootargs = "earlyprintk";
stdout-path = "serial0:115200n8";
};
memory {