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ARM: socfpga: dts: add osc1 as a possible parent for dbg_base_clk
The dbg_base_clk can also have osc1 has a parent. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
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@ -164,7 +164,7 @@ mainclk: mainclk {
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dbg_base_clk: dbg_base_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-perip-clk";
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clocks = <&main_pll>;
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clocks = <&main_pll>, <&osc1>;
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div-reg = <0xe8 0 9>;
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reg = <0x50>;
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};
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