From 2211a658620a35f3b3eabdfa2587f46b7abf3ee7 Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Thu, 16 Jul 2015 15:48:50 -0500 Subject: [PATCH 1/7] ARM: dts: socfpga: enable the data and instruction prefetch for the l2 cache Just in case the firmware did not enable data and instruction prefetch in the L2 cache controller, we enable it in the kernel. Signed-off-by: Dinh Nguyen --- arch/arm/boot/dts/socfpga.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi index 80f924deed37..1e3c833dfbd2 100644 --- a/arch/arm/boot/dts/socfpga.dtsi +++ b/arch/arm/boot/dts/socfpga.dtsi @@ -639,6 +639,8 @@ L2: l2-cache@fffef000 { cache-level = <2>; arm,tag-latency = <1 1 1>; arm,data-latency = <2 1 1>; + prefetch-data = <1>; + prefetch-instr = <1>; }; mmc: dwmmc0@ff704000 { From efc1985c8f79ee8259d19a9b6e3df6a07d063669 Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Tue, 14 Jul 2015 17:19:02 -0500 Subject: [PATCH 2/7] ARM: dts: socfpga: use stdout-path for chosen node Use stdout-path dts property for kernel console. Signed-off-by: Dinh Nguyen --- arch/arm/boot/dts/socfpga_arria10.dtsi | 5 +++++ arch/arm/boot/dts/socfpga_arria10_socdk.dtsi | 3 ++- arch/arm/boot/dts/socfpga_arria5_socdk.dts | 3 ++- arch/arm/boot/dts/socfpga_cyclone5_socdk.dts | 3 ++- arch/arm/boot/dts/socfpga_cyclone5_sockit.dts | 3 ++- 5 files changed, 13 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi index 4779b07310df..a25290505aa3 100644 --- a/arch/arm/boot/dts/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/socfpga_arria10.dtsi @@ -21,6 +21,11 @@ / { #address-cells = <1>; #size-cells = <1>; + aliases { + serial0 = &uart0; + serial1 = &uart1; + }; + cpus { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi b/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi index 94a0709b2fe6..99aa9a1c8af0 100644 --- a/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi +++ b/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi @@ -21,7 +21,8 @@ / { compatible = "altr,socfpga-arria10", "altr,socfpga"; chosen { - bootargs = "console=ttyS0,115200 rootwait"; + bootargs = "earlyprintk"; + stdout-path = "serial1:115200n8"; }; memory { diff --git a/arch/arm/boot/dts/socfpga_arria5_socdk.dts b/arch/arm/boot/dts/socfpga_arria5_socdk.dts index ccaf41742fc3..a75a666032b2 100644 --- a/arch/arm/boot/dts/socfpga_arria5_socdk.dts +++ b/arch/arm/boot/dts/socfpga_arria5_socdk.dts @@ -22,7 +22,8 @@ / { compatible = "altr,socfpga-arria5", "altr,socfpga"; chosen { - bootargs = "console=ttyS0,115200"; + bootargs = "earlyprintk"; + stdout-path = "serial0:115200n8"; }; memory { diff --git a/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts b/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts index 258865da8f6a..d4d0a28fb331 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts +++ b/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts @@ -22,7 +22,8 @@ / { compatible = "altr,socfpga-cyclone5", "altr,socfpga"; chosen { - bootargs = "console=ttyS0,115200"; + bootargs = "earlyprintk"; + stdout-path = "serial0:115200n8"; }; memory { diff --git a/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts b/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts index 71468a7eb28f..42d60923d52b 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts +++ b/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts @@ -22,7 +22,8 @@ / { compatible = "altr,socfpga-cyclone5", "altr,socfpga"; chosen { - bootargs = "console=ttyS0,115200"; + bootargs = "earlyprintk"; + stdout-path = "serial0:115200n8"; }; memory { From 57c0f8c9c45365d167f8606dad7fde9565432b7a Mon Sep 17 00:00:00 2001 From: Dalon Westergreen Date: Wed, 8 Jul 2015 16:48:49 -0700 Subject: [PATCH 3/7] ARM: dts: socfpga: Add support of Terasic DE0 Atlas board The Terasic DE0 Atlas board is also known as the DE0-Nano board. This patch adds the DTS board file for the DE0-Nano Sockit board, and not the DE0 Nano "Development Board". Signed-off-by: Dalon Westergreen Signed-off-by: Dinh Nguyen --- v3: Updated skew settings for the gmac1 node as this board is using the KSZ9031 PHY instead of the 9021 PHY. v2: use stdpath-out for console and remove comment regarding u-boot ethaddr --- arch/arm/boot/dts/Makefile | 1 + .../boot/dts/socfpga_cyclone5_de0_sockit.dts | 111 ++++++++++++++++++ 2 files changed, 112 insertions(+) create mode 100644 arch/arm/boot/dts/socfpga_cyclone5_de0_sockit.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 246473a244f6..29e33aa3094d 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -522,6 +522,7 @@ dtb-$(CONFIG_ARCH_SOCFPGA) += \ socfpga_arria5_socdk.dtb \ socfpga_arria10_socdk_sdmmc.dtb \ socfpga_cyclone5_socdk.dtb \ + socfpga_cyclone5_de0_sockit.dtb \ socfpga_cyclone5_sockit.dtb \ socfpga_cyclone5_socrates.dtb \ socfpga_vt.dtb diff --git a/arch/arm/boot/dts/socfpga_cyclone5_de0_sockit.dts b/arch/arm/boot/dts/socfpga_cyclone5_de0_sockit.dts new file mode 100644 index 000000000000..555e9caf21e1 --- /dev/null +++ b/arch/arm/boot/dts/socfpga_cyclone5_de0_sockit.dts @@ -0,0 +1,111 @@ +/* + * Copyright Altera Corporation (C) 2015. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +#include "socfpga_cyclone5.dtsi" + +/ { + model = "Terasic DE-0(Atlas)"; + compatible = "altr,socfpga-cyclone5", "altr,socfpga"; + + chosen { + bootargs = "earlyprintk"; + stdout-path = "serial0:115200n8"; + }; + + memory { + name = "memory"; + device_type = "memory"; + reg = <0x0 0x40000000>; /* 1GB */ + }; + + aliases { + ethernet0 = &gmac1; + }; + + regulator_3_3v: 3-3-v-regulator { + compatible = "regulator-fixed"; + regulator-name = "3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + leds { + compatible = "gpio-leds"; + hps0 { + label = "hps_led0"; + gpios = <&portb 24 0>; + linux,default-trigger = "heartbeat"; + }; + }; +}; + +&gmac1 { + status = "okay"; + phy-mode = "rgmii"; + + txd0-skew-ps = <0>; /* -420ps */ + txd1-skew-ps = <0>; /* -420ps */ + txd2-skew-ps = <0>; /* -420ps */ + txd3-skew-ps = <0>; /* -420ps */ + rxd0-skew-ps = <420>; /* 0ps */ + rxd1-skew-ps = <420>; /* 0ps */ + rxd2-skew-ps = <420>; /* 0ps */ + rxd3-skew-ps = <420>; /* 0ps */ + txen-skew-ps = <0>; /* -420ps */ + txc-skew-ps = <1860>; /* 960ps */ + rxdv-skew-ps = <420>; /* 0ps */ + rxc-skew-ps = <1680>; /* 780ps */ + + max-frame-size = <3800>; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + speed-mode = <0>; + + adxl345: adxl345@0 { + compatible = "adi,adxl345"; + reg = <0x53>; + + interrupt-parent = <&portc>; + interrupts = <3 2>; + }; +}; + +&mmc0 { + vmmc-supply = <®ulator_3_3v>; + vqmmc-supply = <®ulator_3_3v>; +}; + +&uart0 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; From c5dab6e2c1f7bbf33ec855cebae92a1566ed6d04 Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Wed, 20 Nov 2013 09:39:17 -0600 Subject: [PATCH 4/7] ARM: socfpga: dts: Correct the parent clock for l3_sp_clk and dbg_clk The l3_sp_clk's parent should be the l3_mp_clk. This will account for the extra divider that is present for the l3_mp_clk. The dbg_clk's parent should be the dbg_at_clk. This will account for the extra divider that is present for the dbg_at_clk. Signed-off-by: Dinh Nguyen --- arch/arm/boot/dts/socfpga.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi index 1e3c833dfbd2..7860935ae3a2 100644 --- a/arch/arm/boot/dts/socfpga.dtsi +++ b/arch/arm/boot/dts/socfpga.dtsi @@ -318,7 +318,7 @@ l3_mp_clk: l3_mp_clk { l3_sp_clk: l3_sp_clk { #clock-cells = <0>; compatible = "altr,socfpga-gate-clk"; - clocks = <&mainclk>; + clocks = <&l3_mp_clk>; div-reg = <0x64 2 2>; }; @@ -349,7 +349,7 @@ dbg_at_clk: dbg_at_clk { dbg_clk: dbg_clk { #clock-cells = <0>; compatible = "altr,socfpga-gate-clk"; - clocks = <&dbg_base_clk>; + clocks = <&dbg_at_clk>; div-reg = <0x68 2 2>; clk-gate = <0x60 5>; }; From e9f9fe35f8940c9a4c5deba091d532e3a02bf78b Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Wed, 28 May 2014 22:40:13 -0500 Subject: [PATCH 5/7] ARM: socfpga: dts: Fix gpio dts entry for the correct clock The correct clock for the HPS gpio(s) should be the l4_mp_clk. Signed-off-by: Dinh Nguyen --- arch/arm/boot/dts/socfpga.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi index 7860935ae3a2..b0acaec3b81a 100644 --- a/arch/arm/boot/dts/socfpga.dtsi +++ b/arch/arm/boot/dts/socfpga.dtsi @@ -565,7 +565,7 @@ gpio0: gpio@ff708000 { #size-cells = <0>; compatible = "snps,dw-apb-gpio"; reg = <0xff708000 0x1000>; - clocks = <&per_base_clk>; + clocks = <&l4_mp_clk>; status = "disabled"; porta: gpio-controller@0 { @@ -585,7 +585,7 @@ gpio1: gpio@ff709000 { #size-cells = <0>; compatible = "snps,dw-apb-gpio"; reg = <0xff709000 0x1000>; - clocks = <&per_base_clk>; + clocks = <&l4_mp_clk>; status = "disabled"; portb: gpio-controller@0 { @@ -605,7 +605,7 @@ gpio2: gpio@ff70a000 { #size-cells = <0>; compatible = "snps,dw-apb-gpio"; reg = <0xff70a000 0x1000>; - clocks = <&per_base_clk>; + clocks = <&l4_mp_clk>; status = "disabled"; portc: gpio-controller@0 { From 7db85dd0828803f44f50ed6953f3f7cb762b830d Mon Sep 17 00:00:00 2001 From: Matthew Gerlach Date: Mon, 3 Feb 2014 14:22:59 -0800 Subject: [PATCH 6/7] ARM: socfpga: dts: add missing clock gates to socfpga.dtsi The gates for the clocks coming out of the sdram pll were missing. The change adds the missing nodes to the device tree. Signed-off-by: Matthew Gerlach Signed-off-by: Dinh Nguyen --- arch/arm/boot/dts/socfpga.dtsi | 31 ++++++++++++++++++++++++++++++- 1 file changed, 30 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi index b0acaec3b81a..86e0fb6fff9c 100644 --- a/arch/arm/boot/dts/socfpga.dtsi +++ b/arch/arm/boot/dts/socfpga.dtsi @@ -481,8 +481,37 @@ qspi_clk: qspi_clk { clocks = <&f2s_periph_ref_clk>, <&main_qspi_clk>, <&per_qspi_clk>; clk-gate = <0xa0 11>; }; + + ddr_dqs_clk_gate: ddr_dqs_clk_gate { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&ddr_dqs_clk>; + clk-gate = <0xd8 0>; + }; + + ddr_2x_dqs_clk_gate: ddr_2x_dqs_clk_gate { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&ddr_2x_dqs_clk>; + clk-gate = <0xd8 1>; + }; + + ddr_dq_clk_gate: ddr_dq_clk_gate { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&ddr_dq_clk>; + clk-gate = <0xd8 2>; + }; + + h2f_user2_clk: h2f_user2_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&h2f_usr2_clk>; + clk-gate = <0xd8 3>; + }; + }; - }; + }; gmac0: ethernet@ff700000 { compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac"; From 2e4c7588f6c1d24ae991a85140e05139e953c9b5 Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Fri, 24 Jul 2015 22:10:59 -0500 Subject: [PATCH 7/7] ARM: socfpga: dts: add osc1 as a possible parent for dbg_base_clk The dbg_base_clk can also have osc1 has a parent. Signed-off-by: Dinh Nguyen --- arch/arm/boot/dts/socfpga.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi index 86e0fb6fff9c..01bdaaa50854 100644 --- a/arch/arm/boot/dts/socfpga.dtsi +++ b/arch/arm/boot/dts/socfpga.dtsi @@ -164,7 +164,7 @@ mainclk: mainclk { dbg_base_clk: dbg_base_clk { #clock-cells = <0>; compatible = "altr,socfpga-perip-clk"; - clocks = <&main_pll>; + clocks = <&main_pll>, <&osc1>; div-reg = <0xe8 0 9>; reg = <0x50>; };