2019-10-21 21:34:37 +07:00
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/* SPDX-License-Identifier: MIT */
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/*
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* Copyright (C) 2013-2019 NVIDIA Corporation.
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* Copyright (C) 2015 Rob Clark
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*/
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#ifndef DRM_TEGRA_DP_H
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#define DRM_TEGRA_DP_H 1
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2015-12-03 18:45:45 +07:00
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#include <linux/types.h>
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2015-07-21 21:38:11 +07:00
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struct drm_display_info;
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struct drm_display_mode;
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2019-10-21 21:34:37 +07:00
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struct drm_dp_aux;
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2015-07-08 02:21:48 +07:00
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struct drm_dp_link;
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2019-10-21 21:34:37 +07:00
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2015-12-03 18:45:45 +07:00
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/**
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* struct drm_dp_link_caps - DP link capabilities
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*/
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struct drm_dp_link_caps {
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/**
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* @enhanced_framing:
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*
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* enhanced framing capability (mandatory as of DP 1.2)
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*/
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bool enhanced_framing;
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2015-12-03 19:07:43 +07:00
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2015-07-08 01:52:07 +07:00
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/**
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* tps3_supported:
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*
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* training pattern sequence 3 supported for equalization
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*/
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bool tps3_supported;
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2015-12-03 19:07:43 +07:00
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/**
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* @fast_training:
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*
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* AUX CH handshake not required for link training
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*/
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bool fast_training;
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2018-02-05 20:07:57 +07:00
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/**
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* @channel_coding:
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*
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* ANSI 8B/10B channel coding capability
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*/
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bool channel_coding;
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2018-02-05 21:16:18 +07:00
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/**
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* @alternate_scrambler_reset:
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*
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* eDP alternate scrambler reset capability
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*/
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bool alternate_scrambler_reset;
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2015-12-03 18:45:45 +07:00
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};
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void drm_dp_link_caps_copy(struct drm_dp_link_caps *dest,
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const struct drm_dp_link_caps *src);
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2019-10-21 21:34:37 +07:00
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2015-07-08 02:21:48 +07:00
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/**
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* struct drm_dp_link_ops - DP link operations
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*/
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struct drm_dp_link_ops {
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/**
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* @apply_training:
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*/
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int (*apply_training)(struct drm_dp_link *link);
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/**
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* @configure:
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*/
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int (*configure)(struct drm_dp_link *link);
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};
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#define DP_TRAIN_VOLTAGE_SWING_LEVEL(x) ((x) << 0)
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#define DP_TRAIN_PRE_EMPHASIS_LEVEL(x) ((x) << 3)
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#define DP_LANE_POST_CURSOR(i, x) (((x) & 0x3) << (((i) & 1) << 2))
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/**
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* struct drm_dp_link_train_set - link training settings
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* @voltage_swing: per-lane voltage swing
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* @pre_emphasis: per-lane pre-emphasis
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* @post_cursor: per-lane post-cursor
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*/
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struct drm_dp_link_train_set {
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unsigned int voltage_swing[4];
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unsigned int pre_emphasis[4];
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unsigned int post_cursor[4];
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};
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/**
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* struct drm_dp_link_train - link training state information
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* @request: currently requested settings
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* @adjust: adjustments requested by sink
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* @pattern: currently requested training pattern
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* @clock_recovered: flag to track if clock recovery has completed
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* @channel_equalized: flag to track if channel equalization has completed
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*/
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struct drm_dp_link_train {
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struct drm_dp_link_train_set request;
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struct drm_dp_link_train_set adjust;
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unsigned int pattern;
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bool clock_recovered;
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bool channel_equalized;
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};
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2018-02-05 20:31:27 +07:00
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/**
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2015-07-21 21:33:48 +07:00
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* struct drm_dp_link - DP link capabilities and configuration
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2018-02-05 20:31:27 +07:00
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* @revision: DP specification revision supported on the link
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2015-07-21 21:33:48 +07:00
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* @max_rate: maximum clock rate supported on the link
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* @max_lanes: maximum number of lanes supported on the link
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2015-12-03 18:45:45 +07:00
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* @caps: capabilities supported on the link (see &drm_dp_link_caps)
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2015-07-08 02:01:26 +07:00
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* @aux_rd_interval: AUX read interval to use for training (in microseconds)
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2015-07-08 01:59:22 +07:00
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* @edp: eDP revision (0x11: eDP 1.1, 0x12: eDP 1.2, ...)
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2015-07-21 21:33:48 +07:00
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* @rate: currently configured link rate
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* @lanes: currently configured number of lanes
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2018-02-01 23:46:42 +07:00
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* @rates: additional supported link rates in kHz (eDP 1.4)
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* @num_rates: number of additional supported link rates (eDP 1.4)
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2018-02-05 20:31:27 +07:00
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*/
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2019-10-21 21:34:37 +07:00
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struct drm_dp_link {
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unsigned char revision;
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2015-07-21 21:33:48 +07:00
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unsigned int max_rate;
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unsigned int max_lanes;
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2015-12-03 18:45:45 +07:00
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struct drm_dp_link_caps caps;
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2015-07-08 02:01:26 +07:00
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/**
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* @cr: clock recovery read interval
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* @ce: channel equalization read interval
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*/
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struct {
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unsigned int cr;
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unsigned int ce;
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} aux_rd_interval;
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2015-07-08 01:59:22 +07:00
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unsigned char edp;
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2015-07-21 21:33:48 +07:00
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unsigned int rate;
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unsigned int lanes;
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2018-02-01 23:46:42 +07:00
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unsigned long rates[DP_MAX_SUPPORTED_RATES];
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unsigned int num_rates;
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2015-07-08 02:21:48 +07:00
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/**
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* @ops: DP link operations
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*/
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const struct drm_dp_link_ops *ops;
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/**
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* @aux: DP AUX channel
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*/
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struct drm_dp_aux *aux;
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/**
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* @train: DP link training state
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*/
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struct drm_dp_link_train train;
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2019-10-21 21:34:37 +07:00
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};
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2018-02-01 23:46:42 +07:00
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int drm_dp_link_add_rate(struct drm_dp_link *link, unsigned long rate);
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int drm_dp_link_remove_rate(struct drm_dp_link *link, unsigned long rate);
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void drm_dp_link_update_rates(struct drm_dp_link *link);
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2019-10-21 21:34:37 +07:00
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int drm_dp_link_probe(struct drm_dp_aux *aux, struct drm_dp_link *link);
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int drm_dp_link_power_up(struct drm_dp_aux *aux, struct drm_dp_link *link);
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int drm_dp_link_power_down(struct drm_dp_aux *aux, struct drm_dp_link *link);
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int drm_dp_link_configure(struct drm_dp_aux *aux, struct drm_dp_link *link);
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2015-07-21 21:38:11 +07:00
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int drm_dp_link_choose(struct drm_dp_link *link,
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const struct drm_display_mode *mode,
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const struct drm_display_info *info);
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2019-10-21 21:34:37 +07:00
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2015-07-08 02:21:48 +07:00
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void drm_dp_link_train_init(struct drm_dp_link_train *train);
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int drm_dp_link_train(struct drm_dp_link *link);
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2019-10-21 21:34:37 +07:00
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#endif
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