2019-10-21 21:34:37 +07:00
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/* SPDX-License-Identifier: MIT */
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/*
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* Copyright (C) 2013-2019 NVIDIA Corporation.
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* Copyright (C) 2015 Rob Clark
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*/
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#ifndef DRM_TEGRA_DP_H
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#define DRM_TEGRA_DP_H 1
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struct drm_dp_aux;
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#define DP_LINK_CAP_ENHANCED_FRAMING (1 << 0)
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2018-02-05 20:31:27 +07:00
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/**
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* struct drm_dp_link - DP link capabilities
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* @revision: DP specification revision supported on the link
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* @rate: maximum clock rate supported on the link
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* @num_lanes: maximum number of lanes supported on the link
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* @capabilities: bitmask of capabilities supported on the link
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*/
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2019-10-21 21:34:37 +07:00
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struct drm_dp_link {
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unsigned char revision;
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unsigned int rate;
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unsigned int num_lanes;
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unsigned long capabilities;
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};
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int drm_dp_link_probe(struct drm_dp_aux *aux, struct drm_dp_link *link);
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int drm_dp_link_power_up(struct drm_dp_aux *aux, struct drm_dp_link *link);
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int drm_dp_link_power_down(struct drm_dp_aux *aux, struct drm_dp_link *link);
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int drm_dp_link_configure(struct drm_dp_aux *aux, struct drm_dp_link *link);
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#endif
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