2019-10-21 21:34:37 +07:00
|
|
|
/* SPDX-License-Identifier: MIT */
|
|
|
|
|
/*
|
|
|
|
|
* Copyright (C) 2013-2019 NVIDIA Corporation.
|
|
|
|
|
* Copyright (C) 2015 Rob Clark
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
#ifndef DRM_TEGRA_DP_H
|
|
|
|
|
#define DRM_TEGRA_DP_H 1
|
|
|
|
|
|
|
|
|
|
struct drm_dp_aux;
|
|
|
|
|
|
|
|
|
|
#define DP_LINK_CAP_ENHANCED_FRAMING (1 << 0)
|
|
|
|
|
|
2018-02-05 20:31:27 +07:00
|
|
|
/**
|
2015-07-21 21:33:48 +07:00
|
|
|
* struct drm_dp_link - DP link capabilities and configuration
|
2018-02-05 20:31:27 +07:00
|
|
|
* @revision: DP specification revision supported on the link
|
2015-07-21 21:33:48 +07:00
|
|
|
* @max_rate: maximum clock rate supported on the link
|
|
|
|
|
* @max_lanes: maximum number of lanes supported on the link
|
2018-02-05 20:31:27 +07:00
|
|
|
* @capabilities: bitmask of capabilities supported on the link
|
2015-07-21 21:33:48 +07:00
|
|
|
* @rate: currently configured link rate
|
|
|
|
|
* @lanes: currently configured number of lanes
|
2018-02-05 20:31:27 +07:00
|
|
|
*/
|
2019-10-21 21:34:37 +07:00
|
|
|
struct drm_dp_link {
|
|
|
|
|
unsigned char revision;
|
2015-07-21 21:33:48 +07:00
|
|
|
unsigned int max_rate;
|
|
|
|
|
unsigned int max_lanes;
|
2019-10-21 21:34:37 +07:00
|
|
|
unsigned long capabilities;
|
2015-07-21 21:33:48 +07:00
|
|
|
|
|
|
|
|
unsigned int rate;
|
|
|
|
|
unsigned int lanes;
|
2019-10-21 21:34:37 +07:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
int drm_dp_link_probe(struct drm_dp_aux *aux, struct drm_dp_link *link);
|
|
|
|
|
int drm_dp_link_power_up(struct drm_dp_aux *aux, struct drm_dp_link *link);
|
|
|
|
|
int drm_dp_link_power_down(struct drm_dp_aux *aux, struct drm_dp_link *link);
|
|
|
|
|
int drm_dp_link_configure(struct drm_dp_aux *aux, struct drm_dp_link *link);
|
|
|
|
|
|
|
|
|
|
#endif
|
