2014-07-17 01:08:55 +07:00
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/*
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* Copyright 2014 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include <linux/bsearch.h>
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#include <linux/pci.h>
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#include <linux/slab.h>
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#include "kfd_priv.h"
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2014-07-17 05:27:00 +07:00
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#include "kfd_device_queue_manager.h"
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2017-08-16 10:00:15 +07:00
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#include "kfd_pm4_headers_vi.h"
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2018-05-02 04:56:06 +07:00
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#include "cwsr_trap_handler.h"
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2017-12-09 07:22:12 +07:00
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#include "kfd_iommu.h"
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2018-10-16 22:36:15 +07:00
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#include "amdgpu_amdkfd.h"
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2014-07-17 01:08:55 +07:00
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2014-07-17 03:25:31 +07:00
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#define MQD_SIZE_ALIGNED 768
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2018-07-12 09:32:56 +07:00
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/*
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* kfd_locked is used to lock the kfd driver during suspend or reset
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* once locked, kfd driver will stop any further GPU execution.
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* create process (open) will return -EAGAIN.
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*/
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static atomic_t kfd_locked = ATOMIC_INIT(0);
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2014-07-17 03:25:31 +07:00
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2017-12-09 07:22:12 +07:00
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#ifdef KFD_SUPPORT_IOMMU_V2
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2014-07-17 01:08:55 +07:00
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static const struct kfd_device_info kaveri_device_info = {
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2015-01-01 22:10:01 +07:00
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.asic_family = CHIP_KAVERI,
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.max_pasid_bits = 16,
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2015-05-20 17:43:04 +07:00
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/* max num of queues for KV.TODO should be a dynamic value */
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.max_no_of_hqd = 24,
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2018-04-11 04:33:03 +07:00
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.doorbell_size = 4,
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2015-01-01 22:10:01 +07:00
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.ih_ring_entry_size = 4 * sizeof(uint32_t),
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2015-05-10 16:15:46 +07:00
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.event_interrupt_class = &event_interrupt_class_cik,
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2015-05-20 17:48:26 +07:00
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.num_of_watch_points = 4,
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2017-11-15 04:41:19 +07:00
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.mqd_size_aligned = MQD_SIZE_ALIGNED,
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.supports_cwsr = false,
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2017-12-09 07:22:12 +07:00
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.needs_iommu_device = true,
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2018-01-05 05:17:41 +07:00
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.needs_pci_atomics = false,
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2018-07-14 03:17:44 +07:00
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.num_sdma_engines = 2,
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2018-02-10 04:29:14 +07:00
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.num_sdma_queues_per_engine = 2,
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2015-01-01 22:10:01 +07:00
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};
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static const struct kfd_device_info carrizo_device_info = {
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.asic_family = CHIP_CARRIZO,
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2014-07-17 01:08:55 +07:00
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.max_pasid_bits = 16,
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2015-06-07 01:45:43 +07:00
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/* max num of queues for CZ.TODO should be a dynamic value */
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.max_no_of_hqd = 24,
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2018-04-11 04:33:03 +07:00
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.doorbell_size = 4,
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2014-07-17 05:37:30 +07:00
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.ih_ring_entry_size = 4 * sizeof(uint32_t),
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2015-06-07 01:45:43 +07:00
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.event_interrupt_class = &event_interrupt_class_cik,
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2014-10-13 20:35:12 +07:00
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.num_of_watch_points = 4,
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2017-11-15 04:41:19 +07:00
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.mqd_size_aligned = MQD_SIZE_ALIGNED,
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.supports_cwsr = true,
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2017-12-09 07:22:12 +07:00
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.needs_iommu_device = true,
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2018-01-05 05:17:41 +07:00
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.needs_pci_atomics = false,
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2018-07-14 03:17:44 +07:00
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.num_sdma_engines = 2,
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2018-02-10 04:29:14 +07:00
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.num_sdma_queues_per_engine = 2,
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2014-07-17 01:08:55 +07:00
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};
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2018-07-14 03:17:48 +07:00
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static const struct kfd_device_info raven_device_info = {
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.asic_family = CHIP_RAVEN,
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.max_pasid_bits = 16,
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.max_no_of_hqd = 24,
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.doorbell_size = 8,
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.ih_ring_entry_size = 8 * sizeof(uint32_t),
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.event_interrupt_class = &event_interrupt_class_v9,
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.num_of_watch_points = 4,
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.mqd_size_aligned = MQD_SIZE_ALIGNED,
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.supports_cwsr = true,
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.needs_iommu_device = true,
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.needs_pci_atomics = true,
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.num_sdma_engines = 1,
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2018-02-10 04:29:14 +07:00
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.num_sdma_queues_per_engine = 2,
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2018-07-14 03:17:48 +07:00
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};
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2017-12-09 07:22:12 +07:00
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#endif
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2014-07-17 01:08:55 +07:00
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2018-01-05 05:17:47 +07:00
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static const struct kfd_device_info hawaii_device_info = {
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.asic_family = CHIP_HAWAII,
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.max_pasid_bits = 16,
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/* max num of queues for KV.TODO should be a dynamic value */
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.max_no_of_hqd = 24,
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2018-04-11 04:33:03 +07:00
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.doorbell_size = 4,
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2018-01-05 05:17:47 +07:00
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.ih_ring_entry_size = 4 * sizeof(uint32_t),
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.event_interrupt_class = &event_interrupt_class_cik,
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.num_of_watch_points = 4,
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.mqd_size_aligned = MQD_SIZE_ALIGNED,
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.supports_cwsr = false,
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2017-12-09 07:22:12 +07:00
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.needs_iommu_device = false,
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2018-01-05 05:17:47 +07:00
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.needs_pci_atomics = false,
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2018-07-14 03:17:44 +07:00
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.num_sdma_engines = 2,
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2018-02-10 04:29:14 +07:00
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.num_sdma_queues_per_engine = 2,
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2018-01-05 05:17:47 +07:00
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};
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static const struct kfd_device_info tonga_device_info = {
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.asic_family = CHIP_TONGA,
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.max_pasid_bits = 16,
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.max_no_of_hqd = 24,
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2018-04-11 04:33:03 +07:00
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.doorbell_size = 4,
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2018-01-05 05:17:47 +07:00
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.ih_ring_entry_size = 4 * sizeof(uint32_t),
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.event_interrupt_class = &event_interrupt_class_cik,
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.num_of_watch_points = 4,
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.mqd_size_aligned = MQD_SIZE_ALIGNED,
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.supports_cwsr = false,
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2017-12-09 07:22:12 +07:00
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.needs_iommu_device = false,
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2018-01-05 05:17:47 +07:00
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.needs_pci_atomics = true,
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2018-07-14 03:17:44 +07:00
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.num_sdma_engines = 2,
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2018-02-10 04:29:14 +07:00
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.num_sdma_queues_per_engine = 2,
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2018-01-05 05:17:47 +07:00
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};
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static const struct kfd_device_info fiji_device_info = {
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.asic_family = CHIP_FIJI,
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.max_pasid_bits = 16,
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.max_no_of_hqd = 24,
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2018-04-11 04:33:03 +07:00
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.doorbell_size = 4,
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2018-01-05 05:17:47 +07:00
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.ih_ring_entry_size = 4 * sizeof(uint32_t),
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.event_interrupt_class = &event_interrupt_class_cik,
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.num_of_watch_points = 4,
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.mqd_size_aligned = MQD_SIZE_ALIGNED,
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.supports_cwsr = true,
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2017-12-09 07:22:12 +07:00
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.needs_iommu_device = false,
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2018-01-05 05:17:47 +07:00
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.needs_pci_atomics = true,
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2018-07-14 03:17:44 +07:00
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.num_sdma_engines = 2,
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2018-02-10 04:29:14 +07:00
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.num_sdma_queues_per_engine = 2,
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2018-01-05 05:17:47 +07:00
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};
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static const struct kfd_device_info fiji_vf_device_info = {
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.asic_family = CHIP_FIJI,
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.max_pasid_bits = 16,
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.max_no_of_hqd = 24,
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2018-04-11 04:33:03 +07:00
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.doorbell_size = 4,
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2018-01-05 05:17:47 +07:00
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.ih_ring_entry_size = 4 * sizeof(uint32_t),
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.event_interrupt_class = &event_interrupt_class_cik,
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.num_of_watch_points = 4,
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.mqd_size_aligned = MQD_SIZE_ALIGNED,
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.supports_cwsr = true,
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2017-12-09 07:22:12 +07:00
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.needs_iommu_device = false,
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2018-01-05 05:17:47 +07:00
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.needs_pci_atomics = false,
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2018-07-14 03:17:44 +07:00
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.num_sdma_engines = 2,
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2018-02-10 04:29:14 +07:00
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.num_sdma_queues_per_engine = 2,
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2018-01-05 05:17:47 +07:00
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};
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static const struct kfd_device_info polaris10_device_info = {
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.asic_family = CHIP_POLARIS10,
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.max_pasid_bits = 16,
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.max_no_of_hqd = 24,
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2018-04-11 04:33:03 +07:00
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.doorbell_size = 4,
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2018-01-05 05:17:47 +07:00
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.ih_ring_entry_size = 4 * sizeof(uint32_t),
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.event_interrupt_class = &event_interrupt_class_cik,
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.num_of_watch_points = 4,
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.mqd_size_aligned = MQD_SIZE_ALIGNED,
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.supports_cwsr = true,
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2017-12-09 07:22:12 +07:00
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.needs_iommu_device = false,
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2018-01-05 05:17:47 +07:00
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.needs_pci_atomics = true,
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2018-07-14 03:17:44 +07:00
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.num_sdma_engines = 2,
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2018-02-10 04:29:14 +07:00
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.num_sdma_queues_per_engine = 2,
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2018-01-05 05:17:47 +07:00
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};
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static const struct kfd_device_info polaris10_vf_device_info = {
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.asic_family = CHIP_POLARIS10,
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.max_pasid_bits = 16,
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.max_no_of_hqd = 24,
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2018-04-11 04:33:03 +07:00
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.doorbell_size = 4,
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2018-01-05 05:17:47 +07:00
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.ih_ring_entry_size = 4 * sizeof(uint32_t),
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.event_interrupt_class = &event_interrupt_class_cik,
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.num_of_watch_points = 4,
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.mqd_size_aligned = MQD_SIZE_ALIGNED,
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.supports_cwsr = true,
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2017-12-09 07:22:12 +07:00
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.needs_iommu_device = false,
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2018-01-05 05:17:47 +07:00
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.needs_pci_atomics = false,
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2018-07-14 03:17:44 +07:00
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.num_sdma_engines = 2,
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2018-02-10 04:29:14 +07:00
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.num_sdma_queues_per_engine = 2,
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2018-01-05 05:17:47 +07:00
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};
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static const struct kfd_device_info polaris11_device_info = {
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.asic_family = CHIP_POLARIS11,
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.max_pasid_bits = 16,
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.max_no_of_hqd = 24,
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2018-04-11 04:33:03 +07:00
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.doorbell_size = 4,
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2018-01-05 05:17:47 +07:00
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.ih_ring_entry_size = 4 * sizeof(uint32_t),
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.event_interrupt_class = &event_interrupt_class_cik,
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.num_of_watch_points = 4,
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.mqd_size_aligned = MQD_SIZE_ALIGNED,
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.supports_cwsr = true,
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2017-12-09 07:22:12 +07:00
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.needs_iommu_device = false,
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2018-01-05 05:17:47 +07:00
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.needs_pci_atomics = true,
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2018-07-14 03:17:44 +07:00
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.num_sdma_engines = 2,
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2018-02-10 04:29:14 +07:00
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.num_sdma_queues_per_engine = 2,
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2018-01-05 05:17:47 +07:00
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};
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2018-09-05 22:27:14 +07:00
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static const struct kfd_device_info polaris12_device_info = {
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.asic_family = CHIP_POLARIS12,
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.max_pasid_bits = 16,
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.max_no_of_hqd = 24,
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.doorbell_size = 4,
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.ih_ring_entry_size = 4 * sizeof(uint32_t),
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.event_interrupt_class = &event_interrupt_class_cik,
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.num_of_watch_points = 4,
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.mqd_size_aligned = MQD_SIZE_ALIGNED,
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.supports_cwsr = true,
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.needs_iommu_device = false,
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.needs_pci_atomics = true,
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.num_sdma_engines = 2,
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.num_sdma_queues_per_engine = 2,
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};
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2018-04-11 04:33:18 +07:00
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static const struct kfd_device_info vega10_device_info = {
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.asic_family = CHIP_VEGA10,
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.max_pasid_bits = 16,
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.max_no_of_hqd = 24,
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.doorbell_size = 8,
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.ih_ring_entry_size = 8 * sizeof(uint32_t),
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.event_interrupt_class = &event_interrupt_class_v9,
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.num_of_watch_points = 4,
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.mqd_size_aligned = MQD_SIZE_ALIGNED,
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.supports_cwsr = true,
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.needs_iommu_device = false,
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.needs_pci_atomics = false,
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2018-07-14 03:17:44 +07:00
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.num_sdma_engines = 2,
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2018-02-10 04:29:14 +07:00
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.num_sdma_queues_per_engine = 2,
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2018-04-11 04:33:18 +07:00
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};
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static const struct kfd_device_info vega10_vf_device_info = {
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.asic_family = CHIP_VEGA10,
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.max_pasid_bits = 16,
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.max_no_of_hqd = 24,
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.doorbell_size = 8,
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.ih_ring_entry_size = 8 * sizeof(uint32_t),
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.event_interrupt_class = &event_interrupt_class_v9,
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.num_of_watch_points = 4,
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.mqd_size_aligned = MQD_SIZE_ALIGNED,
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.supports_cwsr = true,
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.needs_iommu_device = false,
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.needs_pci_atomics = false,
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2018-07-14 03:17:44 +07:00
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.num_sdma_engines = 2,
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2018-02-10 04:29:14 +07:00
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.num_sdma_queues_per_engine = 2,
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2018-04-11 04:33:18 +07:00
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};
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2018-09-05 22:27:14 +07:00
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static const struct kfd_device_info vega12_device_info = {
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.asic_family = CHIP_VEGA12,
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.max_pasid_bits = 16,
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.max_no_of_hqd = 24,
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.doorbell_size = 8,
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.ih_ring_entry_size = 8 * sizeof(uint32_t),
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.event_interrupt_class = &event_interrupt_class_v9,
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|
|
.num_of_watch_points = 4,
|
|
|
|
.mqd_size_aligned = MQD_SIZE_ALIGNED,
|
|
|
|
.supports_cwsr = true,
|
|
|
|
.needs_iommu_device = false,
|
|
|
|
.needs_pci_atomics = false,
|
|
|
|
.num_sdma_engines = 2,
|
|
|
|
.num_sdma_queues_per_engine = 2,
|
|
|
|
};
|
|
|
|
|
2017-11-01 00:32:53 +07:00
|
|
|
static const struct kfd_device_info vega20_device_info = {
|
|
|
|
.asic_family = CHIP_VEGA20,
|
|
|
|
.max_pasid_bits = 16,
|
|
|
|
.max_no_of_hqd = 24,
|
|
|
|
.doorbell_size = 8,
|
|
|
|
.ih_ring_entry_size = 8 * sizeof(uint32_t),
|
|
|
|
.event_interrupt_class = &event_interrupt_class_v9,
|
|
|
|
.num_of_watch_points = 4,
|
|
|
|
.mqd_size_aligned = MQD_SIZE_ALIGNED,
|
|
|
|
.supports_cwsr = true,
|
|
|
|
.needs_iommu_device = false,
|
2018-06-19 01:47:21 +07:00
|
|
|
.needs_pci_atomics = false,
|
2017-11-01 00:32:53 +07:00
|
|
|
.num_sdma_engines = 2,
|
|
|
|
.num_sdma_queues_per_engine = 8,
|
|
|
|
};
|
|
|
|
|
2014-07-17 01:08:55 +07:00
|
|
|
struct kfd_deviceid {
|
|
|
|
unsigned short did;
|
|
|
|
const struct kfd_device_info *device_info;
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct kfd_deviceid supported_devices[] = {
|
2017-12-09 07:22:12 +07:00
|
|
|
#ifdef KFD_SUPPORT_IOMMU_V2
|
2014-07-17 01:08:55 +07:00
|
|
|
{ 0x1304, &kaveri_device_info }, /* Kaveri */
|
|
|
|
{ 0x1305, &kaveri_device_info }, /* Kaveri */
|
|
|
|
{ 0x1306, &kaveri_device_info }, /* Kaveri */
|
|
|
|
{ 0x1307, &kaveri_device_info }, /* Kaveri */
|
|
|
|
{ 0x1309, &kaveri_device_info }, /* Kaveri */
|
|
|
|
{ 0x130A, &kaveri_device_info }, /* Kaveri */
|
|
|
|
{ 0x130B, &kaveri_device_info }, /* Kaveri */
|
|
|
|
{ 0x130C, &kaveri_device_info }, /* Kaveri */
|
|
|
|
{ 0x130D, &kaveri_device_info }, /* Kaveri */
|
|
|
|
{ 0x130E, &kaveri_device_info }, /* Kaveri */
|
|
|
|
{ 0x130F, &kaveri_device_info }, /* Kaveri */
|
|
|
|
{ 0x1310, &kaveri_device_info }, /* Kaveri */
|
|
|
|
{ 0x1311, &kaveri_device_info }, /* Kaveri */
|
|
|
|
{ 0x1312, &kaveri_device_info }, /* Kaveri */
|
|
|
|
{ 0x1313, &kaveri_device_info }, /* Kaveri */
|
|
|
|
{ 0x1315, &kaveri_device_info }, /* Kaveri */
|
|
|
|
{ 0x1316, &kaveri_device_info }, /* Kaveri */
|
|
|
|
{ 0x1317, &kaveri_device_info }, /* Kaveri */
|
|
|
|
{ 0x1318, &kaveri_device_info }, /* Kaveri */
|
|
|
|
{ 0x131B, &kaveri_device_info }, /* Kaveri */
|
|
|
|
{ 0x131C, &kaveri_device_info }, /* Kaveri */
|
2015-01-12 19:37:24 +07:00
|
|
|
{ 0x131D, &kaveri_device_info }, /* Kaveri */
|
|
|
|
{ 0x9870, &carrizo_device_info }, /* Carrizo */
|
|
|
|
{ 0x9874, &carrizo_device_info }, /* Carrizo */
|
|
|
|
{ 0x9875, &carrizo_device_info }, /* Carrizo */
|
|
|
|
{ 0x9876, &carrizo_device_info }, /* Carrizo */
|
2018-01-05 05:17:47 +07:00
|
|
|
{ 0x9877, &carrizo_device_info }, /* Carrizo */
|
2018-07-14 03:17:48 +07:00
|
|
|
{ 0x15DD, &raven_device_info }, /* Raven */
|
2019-04-04 00:30:32 +07:00
|
|
|
{ 0x15D8, &raven_device_info }, /* Raven */
|
2017-12-09 07:22:12 +07:00
|
|
|
#endif
|
2018-01-05 05:17:47 +07:00
|
|
|
{ 0x67A0, &hawaii_device_info }, /* Hawaii */
|
|
|
|
{ 0x67A1, &hawaii_device_info }, /* Hawaii */
|
|
|
|
{ 0x67A2, &hawaii_device_info }, /* Hawaii */
|
|
|
|
{ 0x67A8, &hawaii_device_info }, /* Hawaii */
|
|
|
|
{ 0x67A9, &hawaii_device_info }, /* Hawaii */
|
|
|
|
{ 0x67AA, &hawaii_device_info }, /* Hawaii */
|
|
|
|
{ 0x67B0, &hawaii_device_info }, /* Hawaii */
|
|
|
|
{ 0x67B1, &hawaii_device_info }, /* Hawaii */
|
|
|
|
{ 0x67B8, &hawaii_device_info }, /* Hawaii */
|
|
|
|
{ 0x67B9, &hawaii_device_info }, /* Hawaii */
|
|
|
|
{ 0x67BA, &hawaii_device_info }, /* Hawaii */
|
|
|
|
{ 0x67BE, &hawaii_device_info }, /* Hawaii */
|
|
|
|
{ 0x6920, &tonga_device_info }, /* Tonga */
|
|
|
|
{ 0x6921, &tonga_device_info }, /* Tonga */
|
|
|
|
{ 0x6928, &tonga_device_info }, /* Tonga */
|
|
|
|
{ 0x6929, &tonga_device_info }, /* Tonga */
|
|
|
|
{ 0x692B, &tonga_device_info }, /* Tonga */
|
|
|
|
{ 0x6938, &tonga_device_info }, /* Tonga */
|
|
|
|
{ 0x6939, &tonga_device_info }, /* Tonga */
|
|
|
|
{ 0x7300, &fiji_device_info }, /* Fiji */
|
|
|
|
{ 0x730F, &fiji_vf_device_info }, /* Fiji vf*/
|
|
|
|
{ 0x67C0, &polaris10_device_info }, /* Polaris10 */
|
|
|
|
{ 0x67C1, &polaris10_device_info }, /* Polaris10 */
|
|
|
|
{ 0x67C2, &polaris10_device_info }, /* Polaris10 */
|
|
|
|
{ 0x67C4, &polaris10_device_info }, /* Polaris10 */
|
|
|
|
{ 0x67C7, &polaris10_device_info }, /* Polaris10 */
|
|
|
|
{ 0x67C8, &polaris10_device_info }, /* Polaris10 */
|
|
|
|
{ 0x67C9, &polaris10_device_info }, /* Polaris10 */
|
|
|
|
{ 0x67CA, &polaris10_device_info }, /* Polaris10 */
|
|
|
|
{ 0x67CC, &polaris10_device_info }, /* Polaris10 */
|
|
|
|
{ 0x67CF, &polaris10_device_info }, /* Polaris10 */
|
|
|
|
{ 0x67D0, &polaris10_vf_device_info }, /* Polaris10 vf*/
|
|
|
|
{ 0x67DF, &polaris10_device_info }, /* Polaris10 */
|
|
|
|
{ 0x67E0, &polaris11_device_info }, /* Polaris11 */
|
|
|
|
{ 0x67E1, &polaris11_device_info }, /* Polaris11 */
|
|
|
|
{ 0x67E3, &polaris11_device_info }, /* Polaris11 */
|
|
|
|
{ 0x67E7, &polaris11_device_info }, /* Polaris11 */
|
|
|
|
{ 0x67E8, &polaris11_device_info }, /* Polaris11 */
|
|
|
|
{ 0x67E9, &polaris11_device_info }, /* Polaris11 */
|
|
|
|
{ 0x67EB, &polaris11_device_info }, /* Polaris11 */
|
|
|
|
{ 0x67EF, &polaris11_device_info }, /* Polaris11 */
|
|
|
|
{ 0x67FF, &polaris11_device_info }, /* Polaris11 */
|
2018-09-05 22:27:14 +07:00
|
|
|
{ 0x6980, &polaris12_device_info }, /* Polaris12 */
|
|
|
|
{ 0x6981, &polaris12_device_info }, /* Polaris12 */
|
|
|
|
{ 0x6985, &polaris12_device_info }, /* Polaris12 */
|
|
|
|
{ 0x6986, &polaris12_device_info }, /* Polaris12 */
|
|
|
|
{ 0x6987, &polaris12_device_info }, /* Polaris12 */
|
|
|
|
{ 0x6995, &polaris12_device_info }, /* Polaris12 */
|
|
|
|
{ 0x6997, &polaris12_device_info }, /* Polaris12 */
|
|
|
|
{ 0x699F, &polaris12_device_info }, /* Polaris12 */
|
2018-04-11 04:33:18 +07:00
|
|
|
{ 0x6860, &vega10_device_info }, /* Vega10 */
|
|
|
|
{ 0x6861, &vega10_device_info }, /* Vega10 */
|
|
|
|
{ 0x6862, &vega10_device_info }, /* Vega10 */
|
|
|
|
{ 0x6863, &vega10_device_info }, /* Vega10 */
|
|
|
|
{ 0x6864, &vega10_device_info }, /* Vega10 */
|
|
|
|
{ 0x6867, &vega10_device_info }, /* Vega10 */
|
|
|
|
{ 0x6868, &vega10_device_info }, /* Vega10 */
|
2018-12-08 04:23:19 +07:00
|
|
|
{ 0x6869, &vega10_device_info }, /* Vega10 */
|
|
|
|
{ 0x686A, &vega10_device_info }, /* Vega10 */
|
|
|
|
{ 0x686B, &vega10_device_info }, /* Vega10 */
|
2018-04-11 04:33:18 +07:00
|
|
|
{ 0x686C, &vega10_vf_device_info }, /* Vega10 vf*/
|
2018-12-08 04:23:19 +07:00
|
|
|
{ 0x686D, &vega10_device_info }, /* Vega10 */
|
|
|
|
{ 0x686E, &vega10_device_info }, /* Vega10 */
|
|
|
|
{ 0x686F, &vega10_device_info }, /* Vega10 */
|
2018-04-11 04:33:18 +07:00
|
|
|
{ 0x687F, &vega10_device_info }, /* Vega10 */
|
2018-09-05 22:27:14 +07:00
|
|
|
{ 0x69A0, &vega12_device_info }, /* Vega12 */
|
|
|
|
{ 0x69A1, &vega12_device_info }, /* Vega12 */
|
|
|
|
{ 0x69A2, &vega12_device_info }, /* Vega12 */
|
|
|
|
{ 0x69A3, &vega12_device_info }, /* Vega12 */
|
|
|
|
{ 0x69AF, &vega12_device_info }, /* Vega12 */
|
2017-11-01 00:32:53 +07:00
|
|
|
{ 0x66a0, &vega20_device_info }, /* Vega20 */
|
|
|
|
{ 0x66a1, &vega20_device_info }, /* Vega20 */
|
|
|
|
{ 0x66a2, &vega20_device_info }, /* Vega20 */
|
|
|
|
{ 0x66a3, &vega20_device_info }, /* Vega20 */
|
2018-12-08 04:24:33 +07:00
|
|
|
{ 0x66a4, &vega20_device_info }, /* Vega20 */
|
2017-11-01 00:32:53 +07:00
|
|
|
{ 0x66a7, &vega20_device_info }, /* Vega20 */
|
|
|
|
{ 0x66af, &vega20_device_info } /* Vega20 */
|
2014-07-17 01:08:55 +07:00
|
|
|
};
|
|
|
|
|
2014-10-27 19:36:07 +07:00
|
|
|
static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size,
|
|
|
|
unsigned int chunk_size);
|
|
|
|
static void kfd_gtt_sa_fini(struct kfd_dev *kfd);
|
|
|
|
|
2017-09-21 05:10:13 +07:00
|
|
|
static int kfd_resume(struct kfd_dev *kfd);
|
|
|
|
|
2014-07-17 01:08:55 +07:00
|
|
|
static const struct kfd_device_info *lookup_device_info(unsigned short did)
|
|
|
|
{
|
|
|
|
size_t i;
|
|
|
|
|
|
|
|
for (i = 0; i < ARRAY_SIZE(supported_devices); i++) {
|
|
|
|
if (supported_devices[i].did == did) {
|
2017-08-16 10:00:12 +07:00
|
|
|
WARN_ON(!supported_devices[i].device_info);
|
2014-07-17 01:08:55 +07:00
|
|
|
return supported_devices[i].device_info;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2017-08-16 10:00:13 +07:00
|
|
|
dev_warn(kfd_device, "DID %04x is missing in supported_devices\n",
|
|
|
|
did);
|
|
|
|
|
2014-07-17 01:08:55 +07:00
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
2015-03-17 18:32:53 +07:00
|
|
|
struct kfd_dev *kgd2kfd_probe(struct kgd_dev *kgd,
|
|
|
|
struct pci_dev *pdev, const struct kfd2kgd_calls *f2g)
|
2014-07-17 01:08:55 +07:00
|
|
|
{
|
|
|
|
struct kfd_dev *kfd;
|
2018-04-11 04:33:17 +07:00
|
|
|
int ret;
|
2014-07-17 01:08:55 +07:00
|
|
|
const struct kfd_device_info *device_info =
|
|
|
|
lookup_device_info(pdev->device);
|
|
|
|
|
2017-08-16 10:00:13 +07:00
|
|
|
if (!device_info) {
|
|
|
|
dev_err(kfd_device, "kgd2kfd_probe failed\n");
|
2014-07-17 01:08:55 +07:00
|
|
|
return NULL;
|
2017-08-16 10:00:13 +07:00
|
|
|
}
|
2014-07-17 01:08:55 +07:00
|
|
|
|
2018-06-05 02:22:24 +07:00
|
|
|
kfd = kzalloc(sizeof(*kfd), GFP_KERNEL);
|
|
|
|
if (!kfd)
|
|
|
|
return NULL;
|
|
|
|
|
2018-04-11 04:33:17 +07:00
|
|
|
/* Allow BIF to recode atomics to PCIe 3.0 AtomicOps.
|
|
|
|
* 32 and 64-bit requests are possible and must be
|
|
|
|
* supported.
|
|
|
|
*/
|
|
|
|
ret = pci_enable_atomic_ops_to_root(pdev,
|
|
|
|
PCI_EXP_DEVCAP2_ATOMIC_COMP32 |
|
|
|
|
PCI_EXP_DEVCAP2_ATOMIC_COMP64);
|
|
|
|
if (device_info->needs_pci_atomics && ret < 0) {
|
|
|
|
dev_info(kfd_device,
|
|
|
|
"skipped device %x:%x, PCI rejects atomics\n",
|
|
|
|
pdev->vendor, pdev->device);
|
2018-06-05 02:22:24 +07:00
|
|
|
kfree(kfd);
|
2018-04-11 04:33:17 +07:00
|
|
|
return NULL;
|
2018-06-05 02:22:24 +07:00
|
|
|
} else if (!ret)
|
|
|
|
kfd->pci_atomic_requested = true;
|
2014-07-17 01:08:55 +07:00
|
|
|
|
|
|
|
kfd->kgd = kgd;
|
|
|
|
kfd->device_info = device_info;
|
|
|
|
kfd->pdev = pdev;
|
2014-07-17 03:25:31 +07:00
|
|
|
kfd->init_complete = false;
|
2015-03-17 18:32:53 +07:00
|
|
|
kfd->kfd2kgd = f2g;
|
|
|
|
|
|
|
|
mutex_init(&kfd->doorbell_mutex);
|
|
|
|
memset(&kfd->doorbell_available_index, 0,
|
|
|
|
sizeof(kfd->doorbell_available_index));
|
2014-07-17 01:08:55 +07:00
|
|
|
|
2019-01-12 02:38:51 +07:00
|
|
|
atomic_set(&kfd->sram_ecc_flag, 0);
|
|
|
|
|
2014-07-17 01:08:55 +07:00
|
|
|
return kfd;
|
|
|
|
}
|
|
|
|
|
2017-11-15 04:41:19 +07:00
|
|
|
static void kfd_cwsr_init(struct kfd_dev *kfd)
|
|
|
|
{
|
|
|
|
if (cwsr_enable && kfd->device_info->supports_cwsr) {
|
2018-04-11 04:33:16 +07:00
|
|
|
if (kfd->device_info->asic_family < CHIP_VEGA10) {
|
|
|
|
BUILD_BUG_ON(sizeof(cwsr_trap_gfx8_hex) > PAGE_SIZE);
|
|
|
|
kfd->cwsr_isa = cwsr_trap_gfx8_hex;
|
|
|
|
kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx8_hex);
|
|
|
|
} else {
|
|
|
|
BUILD_BUG_ON(sizeof(cwsr_trap_gfx9_hex) > PAGE_SIZE);
|
|
|
|
kfd->cwsr_isa = cwsr_trap_gfx9_hex;
|
|
|
|
kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx9_hex);
|
|
|
|
}
|
2017-11-15 04:41:19 +07:00
|
|
|
|
|
|
|
kfd->cwsr_enabled = true;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2014-07-17 01:08:55 +07:00
|
|
|
bool kgd2kfd_device_init(struct kfd_dev *kfd,
|
|
|
|
const struct kgd2kfd_shared_resources *gpu_resources)
|
|
|
|
{
|
2014-07-17 03:25:31 +07:00
|
|
|
unsigned int size;
|
|
|
|
|
2019-04-12 22:07:16 +07:00
|
|
|
kfd->mec_fw_version = amdgpu_amdkfd_get_fw_version(kfd->kgd,
|
2018-08-21 07:15:00 +07:00
|
|
|
KGD_ENGINE_MEC1);
|
2019-04-12 22:07:16 +07:00
|
|
|
kfd->sdma_fw_version = amdgpu_amdkfd_get_fw_version(kfd->kgd,
|
2018-08-21 07:15:00 +07:00
|
|
|
KGD_ENGINE_SDMA1);
|
2014-07-17 01:08:55 +07:00
|
|
|
kfd->shared_resources = *gpu_resources;
|
|
|
|
|
2017-09-21 05:10:18 +07:00
|
|
|
kfd->vm_info.first_vmid_kfd = ffs(gpu_resources->compute_vmid_bitmap)-1;
|
|
|
|
kfd->vm_info.last_vmid_kfd = fls(gpu_resources->compute_vmid_bitmap)-1;
|
|
|
|
kfd->vm_info.vmid_num_kfd = kfd->vm_info.last_vmid_kfd
|
|
|
|
- kfd->vm_info.first_vmid_kfd + 1;
|
|
|
|
|
2017-11-28 06:29:45 +07:00
|
|
|
/* Verify module parameters regarding mapped process number*/
|
|
|
|
if ((hws_max_conc_proc < 0)
|
|
|
|
|| (hws_max_conc_proc > kfd->vm_info.vmid_num_kfd)) {
|
|
|
|
dev_err(kfd_device,
|
|
|
|
"hws_max_conc_proc %d must be between 0 and %d, use %d instead\n",
|
|
|
|
hws_max_conc_proc, kfd->vm_info.vmid_num_kfd,
|
|
|
|
kfd->vm_info.vmid_num_kfd);
|
|
|
|
kfd->max_proc_per_quantum = kfd->vm_info.vmid_num_kfd;
|
|
|
|
} else
|
|
|
|
kfd->max_proc_per_quantum = hws_max_conc_proc;
|
|
|
|
|
2014-07-17 03:25:31 +07:00
|
|
|
/* calculate max size of mqds needed for queues */
|
2015-01-18 18:18:01 +07:00
|
|
|
size = max_num_of_queues_per_device *
|
|
|
|
kfd->device_info->mqd_size_aligned;
|
2014-07-17 03:25:31 +07:00
|
|
|
|
2014-10-26 15:12:22 +07:00
|
|
|
/*
|
|
|
|
* calculate max size of runlist packet.
|
|
|
|
* There can be only 2 packets at once
|
|
|
|
*/
|
2017-08-16 10:00:15 +07:00
|
|
|
size += (KFD_MAX_NUM_OF_PROCESSES * sizeof(struct pm4_mes_map_process) +
|
|
|
|
max_num_of_queues_per_device * sizeof(struct pm4_mes_map_queues)
|
|
|
|
+ sizeof(struct pm4_mes_runlist)) * 2;
|
2014-10-26 15:12:22 +07:00
|
|
|
|
|
|
|
/* Add size of HIQ & DIQ */
|
|
|
|
size += KFD_KERNEL_QUEUE_SIZE * 2;
|
|
|
|
|
|
|
|
/* add another 512KB for all other allocations on gart (HPD, fences) */
|
2014-07-17 03:25:31 +07:00
|
|
|
size += 512 * 1024;
|
|
|
|
|
2018-10-19 00:38:19 +07:00
|
|
|
if (amdgpu_amdkfd_alloc_gtt_mem(
|
2015-03-17 18:32:53 +07:00
|
|
|
kfd->kgd, size, &kfd->gtt_mem,
|
2018-09-13 08:42:19 +07:00
|
|
|
&kfd->gtt_start_gpu_addr, &kfd->gtt_start_cpu_ptr,
|
|
|
|
false)) {
|
2017-08-16 10:00:05 +07:00
|
|
|
dev_err(kfd_device, "Could not allocate %d bytes\n", size);
|
2014-07-17 03:25:31 +07:00
|
|
|
goto out;
|
|
|
|
}
|
|
|
|
|
2017-08-16 10:00:05 +07:00
|
|
|
dev_info(kfd_device, "Allocated %d bytes on gart\n", size);
|
2014-10-26 15:12:22 +07:00
|
|
|
|
2014-10-26 14:53:37 +07:00
|
|
|
/* Initialize GTT sa with 512 byte chunk size */
|
|
|
|
if (kfd_gtt_sa_init(kfd, size, 512) != 0) {
|
2017-08-16 10:00:05 +07:00
|
|
|
dev_err(kfd_device, "Error initializing gtt sub-allocator\n");
|
2014-10-26 14:53:37 +07:00
|
|
|
goto kfd_gtt_sa_init_error;
|
|
|
|
}
|
|
|
|
|
2017-08-16 10:00:10 +07:00
|
|
|
if (kfd_doorbell_init(kfd)) {
|
|
|
|
dev_err(kfd_device,
|
|
|
|
"Error initializing doorbell aperture\n");
|
|
|
|
goto kfd_doorbell_error;
|
|
|
|
}
|
2014-07-17 03:25:31 +07:00
|
|
|
|
2018-07-06 22:32:42 +07:00
|
|
|
if (kfd->kfd2kgd->get_hive_id)
|
|
|
|
kfd->hive_id = kfd->kfd2kgd->get_hive_id(kfd->kgd);
|
|
|
|
|
2017-08-16 10:00:06 +07:00
|
|
|
if (kfd_topology_add_device(kfd)) {
|
2017-08-16 10:00:05 +07:00
|
|
|
dev_err(kfd_device, "Error adding device to topology\n");
|
2014-07-17 03:25:31 +07:00
|
|
|
goto kfd_topology_add_device_error;
|
|
|
|
}
|
|
|
|
|
2014-07-17 05:37:30 +07:00
|
|
|
if (kfd_interrupt_init(kfd)) {
|
2017-08-16 10:00:05 +07:00
|
|
|
dev_err(kfd_device, "Error initializing interrupts\n");
|
2014-07-17 05:37:30 +07:00
|
|
|
goto kfd_interrupt_error;
|
|
|
|
}
|
|
|
|
|
2014-07-17 05:27:00 +07:00
|
|
|
kfd->dqm = device_queue_manager_init(kfd);
|
|
|
|
if (!kfd->dqm) {
|
2017-08-16 10:00:05 +07:00
|
|
|
dev_err(kfd_device, "Error initializing queue manager\n");
|
2014-07-17 05:27:00 +07:00
|
|
|
goto device_queue_manager_error;
|
|
|
|
}
|
|
|
|
|
2017-12-09 07:22:12 +07:00
|
|
|
if (kfd_iommu_device_init(kfd)) {
|
|
|
|
dev_err(kfd_device, "Error initializing iommuv2\n");
|
|
|
|
goto device_iommu_error;
|
2014-07-17 05:27:00 +07:00
|
|
|
}
|
|
|
|
|
2017-11-15 04:41:19 +07:00
|
|
|
kfd_cwsr_init(kfd);
|
|
|
|
|
2017-09-21 05:10:13 +07:00
|
|
|
if (kfd_resume(kfd))
|
|
|
|
goto kfd_resume_error;
|
|
|
|
|
2015-05-20 17:48:26 +07:00
|
|
|
kfd->dbgmgr = NULL;
|
|
|
|
|
2014-07-17 01:08:55 +07:00
|
|
|
kfd->init_complete = true;
|
2017-08-16 10:00:05 +07:00
|
|
|
dev_info(kfd_device, "added device %x:%x\n", kfd->pdev->vendor,
|
2014-07-17 01:08:55 +07:00
|
|
|
kfd->pdev->device);
|
|
|
|
|
2017-08-16 10:00:05 +07:00
|
|
|
pr_debug("Starting kfd with the following scheduling policy %d\n",
|
2018-01-05 05:17:43 +07:00
|
|
|
kfd->dqm->sched_policy);
|
2014-07-17 05:27:00 +07:00
|
|
|
|
2014-07-17 03:25:31 +07:00
|
|
|
goto out;
|
|
|
|
|
2017-09-21 05:10:13 +07:00
|
|
|
kfd_resume_error:
|
2017-12-09 07:22:12 +07:00
|
|
|
device_iommu_error:
|
2014-07-17 05:27:00 +07:00
|
|
|
device_queue_manager_uninit(kfd->dqm);
|
|
|
|
device_queue_manager_error:
|
2014-07-17 05:37:30 +07:00
|
|
|
kfd_interrupt_exit(kfd);
|
|
|
|
kfd_interrupt_error:
|
2014-07-17 04:06:27 +07:00
|
|
|
kfd_topology_remove_device(kfd);
|
2014-07-17 03:25:31 +07:00
|
|
|
kfd_topology_add_device_error:
|
2017-08-16 10:00:10 +07:00
|
|
|
kfd_doorbell_fini(kfd);
|
|
|
|
kfd_doorbell_error:
|
2014-10-26 14:53:37 +07:00
|
|
|
kfd_gtt_sa_fini(kfd);
|
|
|
|
kfd_gtt_sa_init_error:
|
2018-10-19 00:38:19 +07:00
|
|
|
amdgpu_amdkfd_free_gtt_mem(kfd->kgd, kfd->gtt_mem);
|
2014-07-17 03:25:31 +07:00
|
|
|
dev_err(kfd_device,
|
2017-08-16 10:00:05 +07:00
|
|
|
"device %x:%x NOT added due to errors\n",
|
2014-07-17 03:25:31 +07:00
|
|
|
kfd->pdev->vendor, kfd->pdev->device);
|
|
|
|
out:
|
|
|
|
return kfd->init_complete;
|
2014-07-17 01:08:55 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
void kgd2kfd_device_exit(struct kfd_dev *kfd)
|
|
|
|
{
|
2014-07-17 04:06:27 +07:00
|
|
|
if (kfd->init_complete) {
|
2017-09-21 05:10:13 +07:00
|
|
|
kgd2kfd_suspend(kfd);
|
2014-07-17 05:27:00 +07:00
|
|
|
device_queue_manager_uninit(kfd->dqm);
|
2014-07-17 05:37:30 +07:00
|
|
|
kfd_interrupt_exit(kfd);
|
2014-07-17 04:06:27 +07:00
|
|
|
kfd_topology_remove_device(kfd);
|
2017-08-16 10:00:10 +07:00
|
|
|
kfd_doorbell_fini(kfd);
|
2014-10-26 14:53:37 +07:00
|
|
|
kfd_gtt_sa_fini(kfd);
|
2018-10-19 00:38:19 +07:00
|
|
|
amdgpu_amdkfd_free_gtt_mem(kfd->kgd, kfd->gtt_mem);
|
2014-07-17 04:06:27 +07:00
|
|
|
}
|
2014-07-17 01:22:32 +07:00
|
|
|
|
2014-07-17 01:08:55 +07:00
|
|
|
kfree(kfd);
|
|
|
|
}
|
|
|
|
|
2018-07-12 09:32:54 +07:00
|
|
|
int kgd2kfd_pre_reset(struct kfd_dev *kfd)
|
|
|
|
{
|
2018-07-12 09:32:56 +07:00
|
|
|
if (!kfd->init_complete)
|
|
|
|
return 0;
|
|
|
|
kgd2kfd_suspend(kfd);
|
|
|
|
|
|
|
|
/* hold dqm->lock to prevent further execution*/
|
|
|
|
dqm_lock(kfd->dqm);
|
|
|
|
|
|
|
|
kfd_signal_reset_event(kfd);
|
2018-07-12 09:32:54 +07:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2018-07-12 09:32:56 +07:00
|
|
|
/*
|
|
|
|
* Fix me. KFD won't be able to resume existing process for now.
|
|
|
|
* We will keep all existing process in a evicted state and
|
|
|
|
* wait the process to be terminated.
|
|
|
|
*/
|
|
|
|
|
2018-07-12 09:32:54 +07:00
|
|
|
int kgd2kfd_post_reset(struct kfd_dev *kfd)
|
|
|
|
{
|
2018-07-12 09:32:56 +07:00
|
|
|
int ret, count;
|
|
|
|
|
|
|
|
if (!kfd->init_complete)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
dqm_unlock(kfd->dqm);
|
|
|
|
|
|
|
|
ret = kfd_resume(kfd);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
count = atomic_dec_return(&kfd_locked);
|
|
|
|
WARN_ONCE(count != 0, "KFD reset ref. error");
|
2019-01-12 02:38:51 +07:00
|
|
|
|
|
|
|
atomic_set(&kfd->sram_ecc_flag, 0);
|
|
|
|
|
2018-07-12 09:32:54 +07:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2018-07-12 09:32:56 +07:00
|
|
|
bool kfd_is_locked(void)
|
|
|
|
{
|
|
|
|
return (atomic_read(&kfd_locked) > 0);
|
|
|
|
}
|
|
|
|
|
2014-07-17 01:08:55 +07:00
|
|
|
void kgd2kfd_suspend(struct kfd_dev *kfd)
|
|
|
|
{
|
2017-09-21 05:10:14 +07:00
|
|
|
if (!kfd->init_complete)
|
|
|
|
return;
|
|
|
|
|
2018-02-07 08:32:45 +07:00
|
|
|
/* For first KFD device suspend all the KFD processes */
|
2018-07-12 09:32:56 +07:00
|
|
|
if (atomic_inc_return(&kfd_locked) == 1)
|
2018-02-07 08:32:45 +07:00
|
|
|
kfd_suspend_all_processes();
|
|
|
|
|
2017-09-21 05:10:14 +07:00
|
|
|
kfd->dqm->ops.stop(kfd->dqm);
|
|
|
|
|
2017-12-09 07:22:12 +07:00
|
|
|
kfd_iommu_suspend(kfd);
|
2014-07-17 01:08:55 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
int kgd2kfd_resume(struct kfd_dev *kfd)
|
|
|
|
{
|
2018-02-07 08:32:45 +07:00
|
|
|
int ret, count;
|
|
|
|
|
2017-09-21 05:10:13 +07:00
|
|
|
if (!kfd->init_complete)
|
|
|
|
return 0;
|
2014-07-17 04:06:27 +07:00
|
|
|
|
2018-02-07 08:32:45 +07:00
|
|
|
ret = kfd_resume(kfd);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2018-07-12 09:32:56 +07:00
|
|
|
count = atomic_dec_return(&kfd_locked);
|
2018-02-07 08:32:45 +07:00
|
|
|
WARN_ONCE(count < 0, "KFD suspend / resume ref. error");
|
|
|
|
if (count == 0)
|
|
|
|
ret = kfd_resume_all_processes();
|
2014-07-17 04:06:27 +07:00
|
|
|
|
2018-02-07 08:32:45 +07:00
|
|
|
return ret;
|
2017-09-21 05:10:13 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
static int kfd_resume(struct kfd_dev *kfd)
|
|
|
|
{
|
|
|
|
int err = 0;
|
|
|
|
|
2017-12-09 07:22:12 +07:00
|
|
|
err = kfd_iommu_resume(kfd);
|
|
|
|
if (err) {
|
|
|
|
dev_err(kfd_device,
|
|
|
|
"Failed to resume IOMMU for device %x:%x\n",
|
|
|
|
kfd->pdev->vendor, kfd->pdev->device);
|
|
|
|
return err;
|
|
|
|
}
|
2017-09-21 05:10:14 +07:00
|
|
|
|
2017-09-21 05:10:13 +07:00
|
|
|
err = kfd->dqm->ops.start(kfd->dqm);
|
|
|
|
if (err) {
|
|
|
|
dev_err(kfd_device,
|
|
|
|
"Error starting queue manager for device %x:%x\n",
|
|
|
|
kfd->pdev->vendor, kfd->pdev->device);
|
|
|
|
goto dqm_start_error;
|
2014-07-17 04:06:27 +07:00
|
|
|
}
|
|
|
|
|
2017-09-21 05:10:13 +07:00
|
|
|
return err;
|
|
|
|
|
|
|
|
dqm_start_error:
|
2017-12-09 07:22:12 +07:00
|
|
|
kfd_iommu_suspend(kfd);
|
2017-09-21 05:10:13 +07:00
|
|
|
return err;
|
2014-07-17 01:08:55 +07:00
|
|
|
}
|
|
|
|
|
2014-07-17 05:37:30 +07:00
|
|
|
/* This is called directly from KGD at ISR. */
|
|
|
|
void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry)
|
2014-07-17 01:08:55 +07:00
|
|
|
{
|
2018-07-12 09:32:51 +07:00
|
|
|
uint32_t patched_ihre[KFD_MAX_RING_ENTRY_SIZE];
|
|
|
|
bool is_patched = false;
|
2018-11-02 20:46:24 +07:00
|
|
|
unsigned long flags;
|
2018-07-12 09:32:51 +07:00
|
|
|
|
2014-07-17 05:37:30 +07:00
|
|
|
if (!kfd->init_complete)
|
|
|
|
return;
|
|
|
|
|
2018-07-12 09:32:51 +07:00
|
|
|
if (kfd->device_info->ih_ring_entry_size > sizeof(patched_ihre)) {
|
|
|
|
dev_err_once(kfd_device, "Ring entry too small\n");
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2018-11-02 20:46:24 +07:00
|
|
|
spin_lock_irqsave(&kfd->interrupt_lock, flags);
|
2014-07-17 05:37:30 +07:00
|
|
|
|
|
|
|
if (kfd->interrupts_active
|
2018-07-12 09:32:51 +07:00
|
|
|
&& interrupt_is_wanted(kfd, ih_ring_entry,
|
|
|
|
patched_ihre, &is_patched)
|
|
|
|
&& enqueue_ih_ring_entry(kfd,
|
|
|
|
is_patched ? patched_ihre : ih_ring_entry))
|
2017-10-28 06:35:34 +07:00
|
|
|
queue_work(kfd->ih_wq, &kfd->interrupt_work);
|
2014-07-17 05:37:30 +07:00
|
|
|
|
2018-11-02 20:46:24 +07:00
|
|
|
spin_unlock_irqrestore(&kfd->interrupt_lock, flags);
|
2014-07-17 01:08:55 +07:00
|
|
|
}
|
2014-10-27 19:36:07 +07:00
|
|
|
|
2018-03-24 02:32:32 +07:00
|
|
|
int kgd2kfd_quiesce_mm(struct mm_struct *mm)
|
|
|
|
{
|
|
|
|
struct kfd_process *p;
|
|
|
|
int r;
|
|
|
|
|
|
|
|
/* Because we are called from arbitrary context (workqueue) as opposed
|
|
|
|
* to process context, kfd_process could attempt to exit while we are
|
|
|
|
* running so the lookup function increments the process ref count.
|
|
|
|
*/
|
|
|
|
p = kfd_lookup_process_by_mm(mm);
|
|
|
|
if (!p)
|
|
|
|
return -ESRCH;
|
|
|
|
|
|
|
|
r = kfd_process_evict_queues(p);
|
|
|
|
|
|
|
|
kfd_unref_process(p);
|
|
|
|
return r;
|
|
|
|
}
|
|
|
|
|
|
|
|
int kgd2kfd_resume_mm(struct mm_struct *mm)
|
|
|
|
{
|
|
|
|
struct kfd_process *p;
|
|
|
|
int r;
|
|
|
|
|
|
|
|
/* Because we are called from arbitrary context (workqueue) as opposed
|
|
|
|
* to process context, kfd_process could attempt to exit while we are
|
|
|
|
* running so the lookup function increments the process ref count.
|
|
|
|
*/
|
|
|
|
p = kfd_lookup_process_by_mm(mm);
|
|
|
|
if (!p)
|
|
|
|
return -ESRCH;
|
|
|
|
|
|
|
|
r = kfd_process_restore_queues(p);
|
|
|
|
|
|
|
|
kfd_unref_process(p);
|
|
|
|
return r;
|
|
|
|
}
|
|
|
|
|
2018-02-07 08:32:45 +07:00
|
|
|
/** kgd2kfd_schedule_evict_and_restore_process - Schedules work queue that will
|
|
|
|
* prepare for safe eviction of KFD BOs that belong to the specified
|
|
|
|
* process.
|
|
|
|
*
|
|
|
|
* @mm: mm_struct that identifies the specified KFD process
|
|
|
|
* @fence: eviction fence attached to KFD process BOs
|
|
|
|
*
|
|
|
|
*/
|
|
|
|
int kgd2kfd_schedule_evict_and_restore_process(struct mm_struct *mm,
|
|
|
|
struct dma_fence *fence)
|
|
|
|
{
|
|
|
|
struct kfd_process *p;
|
|
|
|
unsigned long active_time;
|
|
|
|
unsigned long delay_jiffies = msecs_to_jiffies(PROCESS_ACTIVE_TIME_MS);
|
|
|
|
|
|
|
|
if (!fence)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
if (dma_fence_is_signaled(fence))
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
p = kfd_lookup_process_by_mm(mm);
|
|
|
|
if (!p)
|
|
|
|
return -ENODEV;
|
|
|
|
|
|
|
|
if (fence->seqno == p->last_eviction_seqno)
|
|
|
|
goto out;
|
|
|
|
|
|
|
|
p->last_eviction_seqno = fence->seqno;
|
|
|
|
|
|
|
|
/* Avoid KFD process starvation. Wait for at least
|
|
|
|
* PROCESS_ACTIVE_TIME_MS before evicting the process again
|
|
|
|
*/
|
|
|
|
active_time = get_jiffies_64() - p->last_restore_timestamp;
|
|
|
|
if (delay_jiffies > active_time)
|
|
|
|
delay_jiffies -= active_time;
|
|
|
|
else
|
|
|
|
delay_jiffies = 0;
|
|
|
|
|
|
|
|
/* During process initialization eviction_work.dwork is initialized
|
|
|
|
* to kfd_evict_bo_worker
|
|
|
|
*/
|
|
|
|
schedule_delayed_work(&p->eviction_work, delay_jiffies);
|
|
|
|
out:
|
|
|
|
kfd_unref_process(p);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2014-10-27 19:36:07 +07:00
|
|
|
static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size,
|
|
|
|
unsigned int chunk_size)
|
|
|
|
{
|
2017-08-16 10:00:11 +07:00
|
|
|
unsigned int num_of_longs;
|
2014-10-27 19:36:07 +07:00
|
|
|
|
2017-08-16 10:00:12 +07:00
|
|
|
if (WARN_ON(buf_size < chunk_size))
|
|
|
|
return -EINVAL;
|
|
|
|
if (WARN_ON(buf_size == 0))
|
|
|
|
return -EINVAL;
|
|
|
|
if (WARN_ON(chunk_size == 0))
|
|
|
|
return -EINVAL;
|
2014-10-27 19:36:07 +07:00
|
|
|
|
|
|
|
kfd->gtt_sa_chunk_size = chunk_size;
|
|
|
|
kfd->gtt_sa_num_of_chunks = buf_size / chunk_size;
|
|
|
|
|
2017-08-16 10:00:11 +07:00
|
|
|
num_of_longs = (kfd->gtt_sa_num_of_chunks + BITS_PER_LONG - 1) /
|
|
|
|
BITS_PER_LONG;
|
2014-10-27 19:36:07 +07:00
|
|
|
|
2017-08-16 10:00:11 +07:00
|
|
|
kfd->gtt_sa_bitmap = kcalloc(num_of_longs, sizeof(long), GFP_KERNEL);
|
2014-10-27 19:36:07 +07:00
|
|
|
|
|
|
|
if (!kfd->gtt_sa_bitmap)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
2017-08-16 10:00:05 +07:00
|
|
|
pr_debug("gtt_sa_num_of_chunks = %d, gtt_sa_bitmap = %p\n",
|
2014-10-27 19:36:07 +07:00
|
|
|
kfd->gtt_sa_num_of_chunks, kfd->gtt_sa_bitmap);
|
|
|
|
|
|
|
|
mutex_init(&kfd->gtt_sa_lock);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
static void kfd_gtt_sa_fini(struct kfd_dev *kfd)
|
|
|
|
{
|
|
|
|
mutex_destroy(&kfd->gtt_sa_lock);
|
|
|
|
kfree(kfd->gtt_sa_bitmap);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline uint64_t kfd_gtt_sa_calc_gpu_addr(uint64_t start_addr,
|
|
|
|
unsigned int bit_num,
|
|
|
|
unsigned int chunk_size)
|
|
|
|
{
|
|
|
|
return start_addr + bit_num * chunk_size;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline uint32_t *kfd_gtt_sa_calc_cpu_addr(void *start_addr,
|
|
|
|
unsigned int bit_num,
|
|
|
|
unsigned int chunk_size)
|
|
|
|
{
|
|
|
|
return (uint32_t *) ((uint64_t) start_addr + bit_num * chunk_size);
|
|
|
|
}
|
|
|
|
|
|
|
|
int kfd_gtt_sa_allocate(struct kfd_dev *kfd, unsigned int size,
|
|
|
|
struct kfd_mem_obj **mem_obj)
|
|
|
|
{
|
|
|
|
unsigned int found, start_search, cur_size;
|
|
|
|
|
|
|
|
if (size == 0)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
if (size > kfd->gtt_sa_num_of_chunks * kfd->gtt_sa_chunk_size)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
2018-07-12 09:32:45 +07:00
|
|
|
*mem_obj = kzalloc(sizeof(struct kfd_mem_obj), GFP_KERNEL);
|
|
|
|
if (!(*mem_obj))
|
2014-10-27 19:36:07 +07:00
|
|
|
return -ENOMEM;
|
|
|
|
|
2017-08-16 10:00:05 +07:00
|
|
|
pr_debug("Allocated mem_obj = %p for size = %d\n", *mem_obj, size);
|
2014-10-27 19:36:07 +07:00
|
|
|
|
|
|
|
start_search = 0;
|
|
|
|
|
|
|
|
mutex_lock(&kfd->gtt_sa_lock);
|
|
|
|
|
|
|
|
kfd_gtt_restart_search:
|
|
|
|
/* Find the first chunk that is free */
|
|
|
|
found = find_next_zero_bit(kfd->gtt_sa_bitmap,
|
|
|
|
kfd->gtt_sa_num_of_chunks,
|
|
|
|
start_search);
|
|
|
|
|
2017-08-16 10:00:05 +07:00
|
|
|
pr_debug("Found = %d\n", found);
|
2014-10-27 19:36:07 +07:00
|
|
|
|
|
|
|
/* If there wasn't any free chunk, bail out */
|
|
|
|
if (found == kfd->gtt_sa_num_of_chunks)
|
|
|
|
goto kfd_gtt_no_free_chunk;
|
|
|
|
|
|
|
|
/* Update fields of mem_obj */
|
|
|
|
(*mem_obj)->range_start = found;
|
|
|
|
(*mem_obj)->range_end = found;
|
|
|
|
(*mem_obj)->gpu_addr = kfd_gtt_sa_calc_gpu_addr(
|
|
|
|
kfd->gtt_start_gpu_addr,
|
|
|
|
found,
|
|
|
|
kfd->gtt_sa_chunk_size);
|
|
|
|
(*mem_obj)->cpu_ptr = kfd_gtt_sa_calc_cpu_addr(
|
|
|
|
kfd->gtt_start_cpu_ptr,
|
|
|
|
found,
|
|
|
|
kfd->gtt_sa_chunk_size);
|
|
|
|
|
2017-08-16 10:00:05 +07:00
|
|
|
pr_debug("gpu_addr = %p, cpu_addr = %p\n",
|
2014-10-27 19:36:07 +07:00
|
|
|
(uint64_t *) (*mem_obj)->gpu_addr, (*mem_obj)->cpu_ptr);
|
|
|
|
|
|
|
|
/* If we need only one chunk, mark it as allocated and get out */
|
|
|
|
if (size <= kfd->gtt_sa_chunk_size) {
|
2017-08-16 10:00:05 +07:00
|
|
|
pr_debug("Single bit\n");
|
2014-10-27 19:36:07 +07:00
|
|
|
set_bit(found, kfd->gtt_sa_bitmap);
|
|
|
|
goto kfd_gtt_out;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Otherwise, try to see if we have enough contiguous chunks */
|
|
|
|
cur_size = size - kfd->gtt_sa_chunk_size;
|
|
|
|
do {
|
|
|
|
(*mem_obj)->range_end =
|
|
|
|
find_next_zero_bit(kfd->gtt_sa_bitmap,
|
|
|
|
kfd->gtt_sa_num_of_chunks, ++found);
|
|
|
|
/*
|
|
|
|
* If next free chunk is not contiguous than we need to
|
|
|
|
* restart our search from the last free chunk we found (which
|
|
|
|
* wasn't contiguous to the previous ones
|
|
|
|
*/
|
|
|
|
if ((*mem_obj)->range_end != found) {
|
|
|
|
start_search = found;
|
|
|
|
goto kfd_gtt_restart_search;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* If we reached end of buffer, bail out with error
|
|
|
|
*/
|
|
|
|
if (found == kfd->gtt_sa_num_of_chunks)
|
|
|
|
goto kfd_gtt_no_free_chunk;
|
|
|
|
|
|
|
|
/* Check if we don't need another chunk */
|
|
|
|
if (cur_size <= kfd->gtt_sa_chunk_size)
|
|
|
|
cur_size = 0;
|
|
|
|
else
|
|
|
|
cur_size -= kfd->gtt_sa_chunk_size;
|
|
|
|
|
|
|
|
} while (cur_size > 0);
|
|
|
|
|
2017-08-16 10:00:05 +07:00
|
|
|
pr_debug("range_start = %d, range_end = %d\n",
|
2014-10-27 19:36:07 +07:00
|
|
|
(*mem_obj)->range_start, (*mem_obj)->range_end);
|
|
|
|
|
|
|
|
/* Mark the chunks as allocated */
|
|
|
|
for (found = (*mem_obj)->range_start;
|
|
|
|
found <= (*mem_obj)->range_end;
|
|
|
|
found++)
|
|
|
|
set_bit(found, kfd->gtt_sa_bitmap);
|
|
|
|
|
|
|
|
kfd_gtt_out:
|
|
|
|
mutex_unlock(&kfd->gtt_sa_lock);
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
kfd_gtt_no_free_chunk:
|
2017-08-16 10:00:05 +07:00
|
|
|
pr_debug("Allocation failed with mem_obj = %p\n", mem_obj);
|
2014-10-27 19:36:07 +07:00
|
|
|
mutex_unlock(&kfd->gtt_sa_lock);
|
|
|
|
kfree(mem_obj);
|
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
|
|
|
|
int kfd_gtt_sa_free(struct kfd_dev *kfd, struct kfd_mem_obj *mem_obj)
|
|
|
|
{
|
|
|
|
unsigned int bit;
|
|
|
|
|
2015-01-13 03:34:21 +07:00
|
|
|
/* Act like kfree when trying to free a NULL object */
|
|
|
|
if (!mem_obj)
|
|
|
|
return 0;
|
2014-10-27 19:36:07 +07:00
|
|
|
|
2017-08-16 10:00:05 +07:00
|
|
|
pr_debug("Free mem_obj = %p, range_start = %d, range_end = %d\n",
|
2014-10-27 19:36:07 +07:00
|
|
|
mem_obj, mem_obj->range_start, mem_obj->range_end);
|
|
|
|
|
|
|
|
mutex_lock(&kfd->gtt_sa_lock);
|
|
|
|
|
|
|
|
/* Mark the chunks as free */
|
|
|
|
for (bit = mem_obj->range_start;
|
|
|
|
bit <= mem_obj->range_end;
|
|
|
|
bit++)
|
|
|
|
clear_bit(bit, kfd->gtt_sa_bitmap);
|
|
|
|
|
|
|
|
mutex_unlock(&kfd->gtt_sa_lock);
|
|
|
|
|
|
|
|
kfree(mem_obj);
|
|
|
|
return 0;
|
|
|
|
}
|
2018-07-12 09:33:04 +07:00
|
|
|
|
2019-01-12 02:38:51 +07:00
|
|
|
void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd)
|
|
|
|
{
|
|
|
|
if (kfd)
|
|
|
|
atomic_inc(&kfd->sram_ecc_flag);
|
|
|
|
}
|
|
|
|
|
2018-07-12 09:33:04 +07:00
|
|
|
#if defined(CONFIG_DEBUG_FS)
|
|
|
|
|
|
|
|
/* This function will send a package to HIQ to hang the HWS
|
|
|
|
* which will trigger a GPU reset and bring the HWS back to normal state
|
|
|
|
*/
|
|
|
|
int kfd_debugfs_hang_hws(struct kfd_dev *dev)
|
|
|
|
{
|
|
|
|
int r = 0;
|
|
|
|
|
|
|
|
if (dev->dqm->sched_policy != KFD_SCHED_POLICY_HWS) {
|
|
|
|
pr_err("HWS is not enabled");
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
r = pm_debugfs_hang_hws(&dev->dqm->packets);
|
|
|
|
if (!r)
|
|
|
|
r = dqm_debugfs_execute_queues(dev->dqm);
|
|
|
|
|
|
|
|
return r;
|
|
|
|
}
|
|
|
|
|
|
|
|
#endif
|