2005-04-17 05:20:36 +07:00
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/* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
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*/
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2006-01-02 16:14:23 +07:00
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/*
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2005-06-23 19:46:46 +07:00
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*
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2005-04-17 05:20:36 +07:00
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* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
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* All Rights Reserved.
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2005-06-23 19:46:46 +07:00
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sub license, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
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* IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
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* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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2006-01-02 16:14:23 +07:00
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*/
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2005-04-17 05:20:36 +07:00
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2009-02-18 06:13:31 +07:00
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#include <linux/device.h>
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2012-10-03 00:01:07 +07:00
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#include <drm/drmP.h>
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#include <drm/i915_drm.h>
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2005-04-17 05:20:36 +07:00
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#include "i915_drv.h"
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2012-07-02 21:51:02 +07:00
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#include "i915_trace.h"
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2010-09-11 15:19:14 +07:00
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#include "intel_drv.h"
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2005-04-17 05:20:36 +07:00
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DRM: i915: add mode setting support
This commit adds i915 driver support for the DRM mode setting APIs.
Currently, VGA, LVDS, SDVO DVI & VGA, TV and DVO LVDS outputs are
supported. HDMI, DisplayPort and additional SDVO output support will
follow.
Support for the mode setting code is controlled by the new 'modeset'
module option. A new config option, CONFIG_DRM_I915_KMS controls the
default behavior, and whether a PCI ID list is built into the module for
use by user level module utilities.
Note that if mode setting is enabled, user level drivers that access
display registers directly or that don't use the kernel graphics memory
manager will likely corrupt kernel graphics memory, disrupt output
configuration (possibly leading to hangs and/or blank displays), and
prevent panic/oops messages from appearing. So use caution when
enabling this code; be sure your user level code supports the new
interfaces.
A new SysRq key, 'g', provides emergency support for switching back to
the kernel's framebuffer console; which is useful for testing.
Co-authors: Dave Airlie <airlied@linux.ie>, Hong Liu <hong.liu@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2008-11-08 05:24:08 +07:00
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#include <linux/console.h>
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2011-08-30 22:04:30 +07:00
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#include <linux/module.h>
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2012-10-03 00:01:07 +07:00
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#include <drm/drm_crtc_helper.h>
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DRM: i915: add mode setting support
This commit adds i915 driver support for the DRM mode setting APIs.
Currently, VGA, LVDS, SDVO DVI & VGA, TV and DVO LVDS outputs are
supported. HDMI, DisplayPort and additional SDVO output support will
follow.
Support for the mode setting code is controlled by the new 'modeset'
module option. A new config option, CONFIG_DRM_I915_KMS controls the
default behavior, and whether a PCI ID list is built into the module for
use by user level module utilities.
Note that if mode setting is enabled, user level drivers that access
display registers directly or that don't use the kernel graphics memory
manager will likely corrupt kernel graphics memory, disrupt output
configuration (possibly leading to hangs and/or blank displays), and
prevent panic/oops messages from appearing. So use caution when
enabling this code; be sure your user level code supports the new
interfaces.
A new SysRq key, 'g', provides emergency support for switching back to
the kernel's framebuffer console; which is useful for testing.
Co-authors: Dave Airlie <airlied@linux.ie>, Hong Liu <hong.liu@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2008-11-08 05:24:08 +07:00
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2011-07-14 04:38:17 +07:00
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static int i915_modeset __read_mostly = -1;
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DRM: i915: add mode setting support
This commit adds i915 driver support for the DRM mode setting APIs.
Currently, VGA, LVDS, SDVO DVI & VGA, TV and DVO LVDS outputs are
supported. HDMI, DisplayPort and additional SDVO output support will
follow.
Support for the mode setting code is controlled by the new 'modeset'
module option. A new config option, CONFIG_DRM_I915_KMS controls the
default behavior, and whether a PCI ID list is built into the module for
use by user level module utilities.
Note that if mode setting is enabled, user level drivers that access
display registers directly or that don't use the kernel graphics memory
manager will likely corrupt kernel graphics memory, disrupt output
configuration (possibly leading to hangs and/or blank displays), and
prevent panic/oops messages from appearing. So use caution when
enabling this code; be sure your user level code supports the new
interfaces.
A new SysRq key, 'g', provides emergency support for switching back to
the kernel's framebuffer console; which is useful for testing.
Co-authors: Dave Airlie <airlied@linux.ie>, Hong Liu <hong.liu@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2008-11-08 05:24:08 +07:00
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module_param_named(modeset, i915_modeset, int, 0400);
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2011-07-14 04:38:18 +07:00
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MODULE_PARM_DESC(modeset,
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"Use kernel modesetting [KMS] (0=DRM_I915_KMS from .config, "
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"1=on, -1=force vga console preference [default])");
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DRM: i915: add mode setting support
This commit adds i915 driver support for the DRM mode setting APIs.
Currently, VGA, LVDS, SDVO DVI & VGA, TV and DVO LVDS outputs are
supported. HDMI, DisplayPort and additional SDVO output support will
follow.
Support for the mode setting code is controlled by the new 'modeset'
module option. A new config option, CONFIG_DRM_I915_KMS controls the
default behavior, and whether a PCI ID list is built into the module for
use by user level module utilities.
Note that if mode setting is enabled, user level drivers that access
display registers directly or that don't use the kernel graphics memory
manager will likely corrupt kernel graphics memory, disrupt output
configuration (possibly leading to hangs and/or blank displays), and
prevent panic/oops messages from appearing. So use caution when
enabling this code; be sure your user level code supports the new
interfaces.
A new SysRq key, 'g', provides emergency support for switching back to
the kernel's framebuffer console; which is useful for testing.
Co-authors: Dave Airlie <airlied@linux.ie>, Hong Liu <hong.liu@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2008-11-08 05:24:08 +07:00
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2011-07-14 04:38:17 +07:00
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unsigned int i915_fbpercrtc __always_unused = 0;
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DRM: i915: add mode setting support
This commit adds i915 driver support for the DRM mode setting APIs.
Currently, VGA, LVDS, SDVO DVI & VGA, TV and DVO LVDS outputs are
supported. HDMI, DisplayPort and additional SDVO output support will
follow.
Support for the mode setting code is controlled by the new 'modeset'
module option. A new config option, CONFIG_DRM_I915_KMS controls the
default behavior, and whether a PCI ID list is built into the module for
use by user level module utilities.
Note that if mode setting is enabled, user level drivers that access
display registers directly or that don't use the kernel graphics memory
manager will likely corrupt kernel graphics memory, disrupt output
configuration (possibly leading to hangs and/or blank displays), and
prevent panic/oops messages from appearing. So use caution when
enabling this code; be sure your user level code supports the new
interfaces.
A new SysRq key, 'g', provides emergency support for switching back to
the kernel's framebuffer console; which is useful for testing.
Co-authors: Dave Airlie <airlied@linux.ie>, Hong Liu <hong.liu@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2008-11-08 05:24:08 +07:00
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module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400);
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2005-04-17 05:20:36 +07:00
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2012-11-20 20:50:08 +07:00
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int i915_panel_ignore_lid __read_mostly = 1;
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2011-02-17 20:44:48 +07:00
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module_param_named(panel_ignore_lid, i915_panel_ignore_lid, int, 0600);
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2011-07-14 04:38:18 +07:00
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MODULE_PARM_DESC(panel_ignore_lid,
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2012-11-20 20:50:08 +07:00
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"Override lid status (0=autodetect, 1=autodetect disabled [default], "
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"-1=force lid closed, -2=force lid open)");
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2011-02-17 20:44:48 +07:00
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2011-07-14 04:38:17 +07:00
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unsigned int i915_powersave __read_mostly = 1;
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2010-11-02 16:20:50 +07:00
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module_param_named(powersave, i915_powersave, int, 0600);
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2011-07-14 04:38:18 +07:00
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MODULE_PARM_DESC(powersave,
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"Enable powersavings, fbc, downclocking, etc. (default: true)");
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2009-08-18 03:31:43 +07:00
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2011-12-10 08:16:37 +07:00
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int i915_semaphores __read_mostly = -1;
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2011-03-05 01:48:03 +07:00
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module_param_named(semaphores, i915_semaphores, int, 0600);
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2011-07-14 04:38:18 +07:00
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MODULE_PARM_DESC(semaphores,
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2011-12-10 08:16:37 +07:00
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"Use semaphores for inter-ring sync (default: -1 (use per-chip defaults))");
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2011-03-05 01:48:03 +07:00
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2011-11-17 13:24:52 +07:00
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int i915_enable_rc6 __read_mostly = -1;
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2012-04-11 23:39:02 +07:00
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module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0400);
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2011-07-14 04:38:18 +07:00
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MODULE_PARM_DESC(i915_enable_rc6,
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2012-03-23 21:57:18 +07:00
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"Enable power-saving render C-state 6. "
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"Different stages can be selected via bitmask values "
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"(0 = disable; 1 = enable rc6; 2 = enable deep rc6; 4 = enable deepest rc6). "
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"For example, 3 would enable rc6 and deep rc6, and 7 would enable everything. "
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"default: -1 (use per-chip default)");
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2011-02-09 23:15:32 +07:00
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2011-11-10 00:57:50 +07:00
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int i915_enable_fbc __read_mostly = -1;
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2011-05-06 05:24:21 +07:00
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module_param_named(i915_enable_fbc, i915_enable_fbc, int, 0600);
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2011-07-14 04:38:18 +07:00
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MODULE_PARM_DESC(i915_enable_fbc,
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"Enable frame buffer compression for power savings "
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2011-09-20 11:34:19 +07:00
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"(default: -1 (use per-chip default))");
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2011-05-06 05:24:21 +07:00
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2011-07-14 04:38:17 +07:00
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unsigned int i915_lvds_downclock __read_mostly = 0;
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2010-01-15 03:48:02 +07:00
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module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400);
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2011-07-14 04:38:18 +07:00
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MODULE_PARM_DESC(lvds_downclock,
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"Use panel (LVDS/eDP) downclocking for power savings "
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"(default: false)");
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2010-01-15 03:48:02 +07:00
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2012-03-20 19:07:06 +07:00
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int i915_lvds_channel_mode __read_mostly;
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module_param_named(lvds_channel_mode, i915_lvds_channel_mode, int, 0600);
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MODULE_PARM_DESC(lvds_channel_mode,
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"Specify LVDS channel mode "
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"(0=probe BIOS [default], 1=single-channel, 2=dual-channel)");
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2011-11-10 00:57:50 +07:00
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int i915_panel_use_ssc __read_mostly = -1;
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2011-01-13 00:04:08 +07:00
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module_param_named(lvds_use_ssc, i915_panel_use_ssc, int, 0600);
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2011-07-14 04:38:18 +07:00
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MODULE_PARM_DESC(lvds_use_ssc,
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"Use Spread Spectrum Clock with panels [LVDS/eDP] "
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2011-09-27 06:09:45 +07:00
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"(default: auto from VBT)");
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2011-01-13 00:04:08 +07:00
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2011-07-14 04:38:17 +07:00
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int i915_vbt_sdvo_panel_type __read_mostly = -1;
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2011-01-29 23:50:25 +07:00
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module_param_named(vbt_sdvo_panel_type, i915_vbt_sdvo_panel_type, int, 0600);
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2011-07-14 04:38:18 +07:00
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MODULE_PARM_DESC(vbt_sdvo_panel_type,
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2012-03-01 12:44:35 +07:00
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"Override/Ignore selection of SDVO panel mode in the VBT "
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"(-2=ignore, -1=auto [default], index in VBT BIOS table)");
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2011-01-29 23:50:25 +07:00
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2011-07-14 04:38:17 +07:00
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static bool i915_try_reset __read_mostly = true;
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2010-12-23 20:33:15 +07:00
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module_param_named(reset, i915_try_reset, bool, 0600);
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2011-07-14 04:38:18 +07:00
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MODULE_PARM_DESC(reset, "Attempt GPU resets (default: true)");
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2010-12-23 20:33:15 +07:00
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2011-07-14 04:38:17 +07:00
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bool i915_enable_hangcheck __read_mostly = true;
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2011-06-30 00:26:42 +07:00
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module_param_named(enable_hangcheck, i915_enable_hangcheck, bool, 0644);
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2011-07-14 04:38:18 +07:00
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MODULE_PARM_DESC(enable_hangcheck,
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"Periodically check GPU activity for detecting hangs. "
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"WARNING: Disabling this can cause system wide hangs. "
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"(default: true)");
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2011-06-30 00:26:42 +07:00
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2012-04-02 15:08:35 +07:00
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int i915_enable_ppgtt __read_mostly = -1;
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module_param_named(i915_enable_ppgtt, i915_enable_ppgtt, int, 0600);
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2012-02-10 02:53:27 +07:00
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MODULE_PARM_DESC(i915_enable_ppgtt,
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"Enable PPGTT (default: true)");
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2013-07-12 04:45:02 +07:00
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int i915_enable_psr __read_mostly = 0;
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module_param_named(enable_psr, i915_enable_psr, int, 0600);
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MODULE_PARM_DESC(enable_psr, "Enable PSR (default: false)");
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2013-08-14 06:23:17 +07:00
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unsigned int i915_preliminary_hw_support __read_mostly = IS_ENABLED(CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT);
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2012-10-16 03:16:23 +07:00
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module_param_named(preliminary_hw_support, i915_preliminary_hw_support, int, 0600);
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MODULE_PARM_DESC(preliminary_hw_support,
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2013-08-14 06:23:17 +07:00
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"Enable preliminary hardware support.");
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2012-10-16 03:16:23 +07:00
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2013-07-04 03:12:13 +07:00
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int i915_disable_power_well __read_mostly = 1;
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2013-03-23 00:07:23 +07:00
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module_param_named(disable_power_well, i915_disable_power_well, int, 0600);
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MODULE_PARM_DESC(disable_power_well,
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2013-07-04 03:12:13 +07:00
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"Disable the power well when possible (default: true)");
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2013-03-23 00:07:23 +07:00
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2013-06-01 02:33:23 +07:00
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int i915_enable_ips __read_mostly = 1;
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module_param_named(enable_ips, i915_enable_ips, int, 0600);
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MODULE_PARM_DESC(enable_ips, "Enable IPS (default: true)");
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2013-06-26 05:38:15 +07:00
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bool i915_fastboot __read_mostly = 0;
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module_param_named(fastboot, i915_fastboot, bool, 0600);
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MODULE_PARM_DESC(fastboot, "Try to skip unnecessary mode sets at boot time "
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"(default: false)");
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2013-07-19 12:51:24 +07:00
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bool i915_prefault_disable __read_mostly;
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module_param_named(prefault_disable, i915_prefault_disable, bool, 0600);
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MODULE_PARM_DESC(prefault_disable,
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"Disable page prefaulting for pread/pwrite/reloc (default:false). For developers only.");
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2009-01-05 04:55:33 +07:00
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static struct drm_driver driver;
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2010-02-23 13:05:24 +07:00
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extern int intel_agp_enabled;
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2009-01-05 04:55:33 +07:00
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2009-12-17 03:16:16 +07:00
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#define INTEL_VGA_DEVICE(id, info) { \
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2011-10-11 15:59:05 +07:00
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.class = PCI_BASE_CLASS_DISPLAY << 16, \
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2011-01-20 20:09:12 +07:00
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.class_mask = 0xff0000, \
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2009-12-17 03:16:15 +07:00
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.vendor = 0x8086, \
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.device = id, \
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.subvendor = PCI_ANY_ID, \
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.subdevice = PCI_ANY_ID, \
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2009-12-17 03:16:16 +07:00
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.driver_data = (unsigned long) info }
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2013-04-06 03:12:45 +07:00
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#define INTEL_QUANTA_VGA_DEVICE(info) { \
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.class = PCI_BASE_CLASS_DISPLAY << 16, \
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.class_mask = 0xff0000, \
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.vendor = 0x8086, \
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.device = 0x16a, \
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.subvendor = 0x152d, \
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.subdevice = 0x8990, \
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.driver_data = (unsigned long) info }
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2010-05-20 15:33:46 +07:00
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static const struct intel_device_info intel_i830_info = {
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2013-03-14 04:05:41 +07:00
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.gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2,
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2010-08-12 15:42:51 +07:00
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.has_overlay = 1, .overlay_needs_physical = 1,
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2009-12-17 03:16:16 +07:00
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};
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2010-05-20 15:33:46 +07:00
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static const struct intel_device_info intel_845g_info = {
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2013-03-14 04:05:41 +07:00
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.gen = 2, .num_pipes = 1,
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2010-08-12 15:42:51 +07:00
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.has_overlay = 1, .overlay_needs_physical = 1,
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2009-12-17 03:16:16 +07:00
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};
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2010-05-20 15:33:46 +07:00
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|
|
static const struct intel_device_info intel_i85x_info = {
|
2013-03-14 04:05:41 +07:00
|
|
|
.gen = 2, .is_i85x = 1, .is_mobile = 1, .num_pipes = 2,
|
2010-04-16 01:03:30 +07:00
|
|
|
.cursor_needs_physical = 1,
|
2010-08-12 15:42:51 +07:00
|
|
|
.has_overlay = 1, .overlay_needs_physical = 1,
|
2009-12-17 03:16:16 +07:00
|
|
|
};
|
|
|
|
|
2010-05-20 15:33:46 +07:00
|
|
|
static const struct intel_device_info intel_i865g_info = {
|
2013-03-14 04:05:41 +07:00
|
|
|
.gen = 2, .num_pipes = 1,
|
2010-08-12 15:42:51 +07:00
|
|
|
.has_overlay = 1, .overlay_needs_physical = 1,
|
2009-12-17 03:16:16 +07:00
|
|
|
};
|
|
|
|
|
2010-05-20 15:33:46 +07:00
|
|
|
static const struct intel_device_info intel_i915g_info = {
|
2013-03-14 04:05:41 +07:00
|
|
|
.gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, .num_pipes = 2,
|
2010-08-12 15:42:51 +07:00
|
|
|
.has_overlay = 1, .overlay_needs_physical = 1,
|
2009-12-17 03:16:16 +07:00
|
|
|
};
|
2010-05-20 15:33:46 +07:00
|
|
|
static const struct intel_device_info intel_i915gm_info = {
|
2013-03-14 04:05:41 +07:00
|
|
|
.gen = 3, .is_mobile = 1, .num_pipes = 2,
|
2009-12-17 03:16:17 +07:00
|
|
|
.cursor_needs_physical = 1,
|
2010-08-12 15:42:51 +07:00
|
|
|
.has_overlay = 1, .overlay_needs_physical = 1,
|
2010-09-17 06:32:17 +07:00
|
|
|
.supports_tv = 1,
|
2009-12-17 03:16:16 +07:00
|
|
|
};
|
2010-05-20 15:33:46 +07:00
|
|
|
static const struct intel_device_info intel_i945g_info = {
|
2013-03-14 04:05:41 +07:00
|
|
|
.gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, .num_pipes = 2,
|
2010-08-12 15:42:51 +07:00
|
|
|
.has_overlay = 1, .overlay_needs_physical = 1,
|
2009-12-17 03:16:16 +07:00
|
|
|
};
|
2010-05-20 15:33:46 +07:00
|
|
|
static const struct intel_device_info intel_i945gm_info = {
|
2013-03-14 04:05:41 +07:00
|
|
|
.gen = 3, .is_i945gm = 1, .is_mobile = 1, .num_pipes = 2,
|
2009-12-17 03:16:17 +07:00
|
|
|
.has_hotplug = 1, .cursor_needs_physical = 1,
|
2010-08-12 15:42:51 +07:00
|
|
|
.has_overlay = 1, .overlay_needs_physical = 1,
|
2010-09-17 06:32:17 +07:00
|
|
|
.supports_tv = 1,
|
2009-12-17 03:16:16 +07:00
|
|
|
};
|
|
|
|
|
2010-05-20 15:33:46 +07:00
|
|
|
static const struct intel_device_info intel_i965g_info = {
|
2013-03-14 04:05:41 +07:00
|
|
|
.gen = 4, .is_broadwater = 1, .num_pipes = 2,
|
2010-08-11 15:59:24 +07:00
|
|
|
.has_hotplug = 1,
|
2010-08-12 15:42:51 +07:00
|
|
|
.has_overlay = 1,
|
2009-12-17 03:16:16 +07:00
|
|
|
};
|
|
|
|
|
2010-05-20 15:33:46 +07:00
|
|
|
static const struct intel_device_info intel_i965gm_info = {
|
2013-03-14 04:05:41 +07:00
|
|
|
.gen = 4, .is_crestline = 1, .num_pipes = 2,
|
2010-12-05 23:49:51 +07:00
|
|
|
.is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
|
2010-08-12 15:42:51 +07:00
|
|
|
.has_overlay = 1,
|
2010-09-17 06:32:17 +07:00
|
|
|
.supports_tv = 1,
|
2009-12-17 03:16:16 +07:00
|
|
|
};
|
|
|
|
|
2010-05-20 15:33:46 +07:00
|
|
|
static const struct intel_device_info intel_g33_info = {
|
2013-03-14 04:05:41 +07:00
|
|
|
.gen = 3, .is_g33 = 1, .num_pipes = 2,
|
2010-08-11 15:59:24 +07:00
|
|
|
.need_gfx_hws = 1, .has_hotplug = 1,
|
2010-08-12 15:42:51 +07:00
|
|
|
.has_overlay = 1,
|
2009-12-17 03:16:16 +07:00
|
|
|
};
|
|
|
|
|
2010-05-20 15:33:46 +07:00
|
|
|
static const struct intel_device_info intel_g45_info = {
|
2013-03-14 04:05:41 +07:00
|
|
|
.gen = 4, .is_g4x = 1, .need_gfx_hws = 1, .num_pipes = 2,
|
2010-08-11 15:59:24 +07:00
|
|
|
.has_pipe_cxsr = 1, .has_hotplug = 1,
|
2010-09-16 09:43:10 +07:00
|
|
|
.has_bsd_ring = 1,
|
2009-12-17 03:16:16 +07:00
|
|
|
};
|
|
|
|
|
2010-05-20 15:33:46 +07:00
|
|
|
static const struct intel_device_info intel_gm45_info = {
|
2013-03-14 04:05:41 +07:00
|
|
|
.gen = 4, .is_g4x = 1, .num_pipes = 2,
|
2010-12-05 23:49:51 +07:00
|
|
|
.is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
|
2010-08-11 15:59:24 +07:00
|
|
|
.has_pipe_cxsr = 1, .has_hotplug = 1,
|
2010-09-17 06:32:17 +07:00
|
|
|
.supports_tv = 1,
|
2010-09-16 09:43:10 +07:00
|
|
|
.has_bsd_ring = 1,
|
2009-12-17 03:16:16 +07:00
|
|
|
};
|
|
|
|
|
2010-05-20 15:33:46 +07:00
|
|
|
static const struct intel_device_info intel_pineview_info = {
|
2013-03-14 04:05:41 +07:00
|
|
|
.gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .num_pipes = 2,
|
2010-08-11 15:59:24 +07:00
|
|
|
.need_gfx_hws = 1, .has_hotplug = 1,
|
2010-08-12 15:42:51 +07:00
|
|
|
.has_overlay = 1,
|
2009-12-17 03:16:16 +07:00
|
|
|
};
|
|
|
|
|
2010-05-20 15:33:46 +07:00
|
|
|
static const struct intel_device_info intel_ironlake_d_info = {
|
2013-03-14 04:05:41 +07:00
|
|
|
.gen = 5, .num_pipes = 2,
|
2012-01-05 18:34:29 +07:00
|
|
|
.need_gfx_hws = 1, .has_hotplug = 1,
|
2010-09-16 09:43:10 +07:00
|
|
|
.has_bsd_ring = 1,
|
2009-12-17 03:16:16 +07:00
|
|
|
};
|
|
|
|
|
2010-05-20 15:33:46 +07:00
|
|
|
static const struct intel_device_info intel_ironlake_m_info = {
|
2013-03-14 04:05:41 +07:00
|
|
|
.gen = 5, .is_mobile = 1, .num_pipes = 2,
|
2010-12-05 23:49:51 +07:00
|
|
|
.need_gfx_hws = 1, .has_hotplug = 1,
|
2011-05-06 05:24:21 +07:00
|
|
|
.has_fbc = 1,
|
2010-09-16 09:43:10 +07:00
|
|
|
.has_bsd_ring = 1,
|
2009-12-17 03:16:16 +07:00
|
|
|
};
|
|
|
|
|
2010-05-20 15:33:46 +07:00
|
|
|
static const struct intel_device_info intel_sandybridge_d_info = {
|
2013-03-14 04:05:41 +07:00
|
|
|
.gen = 6, .num_pipes = 2,
|
2010-08-11 15:59:24 +07:00
|
|
|
.need_gfx_hws = 1, .has_hotplug = 1,
|
2010-09-19 20:40:43 +07:00
|
|
|
.has_bsd_ring = 1,
|
2010-10-19 17:19:32 +07:00
|
|
|
.has_blt_ring = 1,
|
2012-01-17 23:43:53 +07:00
|
|
|
.has_llc = 1,
|
2012-06-04 16:18:15 +07:00
|
|
|
.has_force_wake = 1,
|
2009-11-03 03:08:22 +07:00
|
|
|
};
|
|
|
|
|
2010-05-20 15:33:46 +07:00
|
|
|
static const struct intel_device_info intel_sandybridge_m_info = {
|
2013-03-14 04:05:41 +07:00
|
|
|
.gen = 6, .is_mobile = 1, .num_pipes = 2,
|
2010-08-11 15:59:24 +07:00
|
|
|
.need_gfx_hws = 1, .has_hotplug = 1,
|
2010-12-15 14:42:32 +07:00
|
|
|
.has_fbc = 1,
|
2010-09-19 20:40:43 +07:00
|
|
|
.has_bsd_ring = 1,
|
2010-10-19 17:19:32 +07:00
|
|
|
.has_blt_ring = 1,
|
2012-01-17 23:43:53 +07:00
|
|
|
.has_llc = 1,
|
2012-06-04 16:18:15 +07:00
|
|
|
.has_force_wake = 1,
|
2010-01-08 06:08:18 +07:00
|
|
|
};
|
|
|
|
|
2013-03-16 01:17:54 +07:00
|
|
|
#define GEN7_FEATURES \
|
|
|
|
.gen = 7, .num_pipes = 3, \
|
|
|
|
.need_gfx_hws = 1, .has_hotplug = 1, \
|
|
|
|
.has_bsd_ring = 1, \
|
|
|
|
.has_blt_ring = 1, \
|
|
|
|
.has_llc = 1, \
|
|
|
|
.has_force_wake = 1
|
|
|
|
|
2011-04-29 04:32:07 +07:00
|
|
|
static const struct intel_device_info intel_ivybridge_d_info = {
|
2013-03-16 01:17:54 +07:00
|
|
|
GEN7_FEATURES,
|
|
|
|
.is_ivybridge = 1,
|
2011-04-29 04:32:07 +07:00
|
|
|
};
|
|
|
|
|
|
|
|
static const struct intel_device_info intel_ivybridge_m_info = {
|
2013-03-16 01:17:54 +07:00
|
|
|
GEN7_FEATURES,
|
|
|
|
.is_ivybridge = 1,
|
|
|
|
.is_mobile = 1,
|
2013-05-07 05:37:33 +07:00
|
|
|
.has_fbc = 1,
|
2011-04-29 04:32:07 +07:00
|
|
|
};
|
|
|
|
|
2013-04-06 03:12:45 +07:00
|
|
|
static const struct intel_device_info intel_ivybridge_q_info = {
|
|
|
|
GEN7_FEATURES,
|
|
|
|
.is_ivybridge = 1,
|
|
|
|
.num_pipes = 0, /* legal, last one wins */
|
|
|
|
};
|
|
|
|
|
2012-03-29 03:39:21 +07:00
|
|
|
static const struct intel_device_info intel_valleyview_m_info = {
|
2013-03-16 01:17:54 +07:00
|
|
|
GEN7_FEATURES,
|
|
|
|
.is_mobile = 1,
|
|
|
|
.num_pipes = 2,
|
2012-03-29 03:39:21 +07:00
|
|
|
.is_valleyview = 1,
|
2013-01-24 20:29:56 +07:00
|
|
|
.display_mmio_offset = VLV_DISPLAY_BASE,
|
2013-04-16 11:48:03 +07:00
|
|
|
.has_llc = 0, /* legal, last one wins */
|
2012-03-29 03:39:21 +07:00
|
|
|
};
|
|
|
|
|
|
|
|
static const struct intel_device_info intel_valleyview_d_info = {
|
2013-03-16 01:17:54 +07:00
|
|
|
GEN7_FEATURES,
|
|
|
|
.num_pipes = 2,
|
2012-03-29 03:39:21 +07:00
|
|
|
.is_valleyview = 1,
|
2013-01-24 20:29:56 +07:00
|
|
|
.display_mmio_offset = VLV_DISPLAY_BASE,
|
2013-04-16 11:48:03 +07:00
|
|
|
.has_llc = 0, /* legal, last one wins */
|
2012-03-29 03:39:21 +07:00
|
|
|
};
|
|
|
|
|
2012-03-29 22:32:18 +07:00
|
|
|
static const struct intel_device_info intel_haswell_d_info = {
|
2013-03-16 01:17:54 +07:00
|
|
|
GEN7_FEATURES,
|
|
|
|
.is_haswell = 1,
|
2013-04-23 00:40:39 +07:00
|
|
|
.has_ddi = 1,
|
2013-04-23 00:40:41 +07:00
|
|
|
.has_fpga_dbg = 1,
|
2013-05-29 09:22:22 +07:00
|
|
|
.has_vebox_ring = 1,
|
2012-03-29 22:32:18 +07:00
|
|
|
};
|
|
|
|
|
|
|
|
static const struct intel_device_info intel_haswell_m_info = {
|
2013-03-16 01:17:54 +07:00
|
|
|
GEN7_FEATURES,
|
|
|
|
.is_haswell = 1,
|
|
|
|
.is_mobile = 1,
|
2013-04-23 00:40:39 +07:00
|
|
|
.has_ddi = 1,
|
2013-04-23 00:40:41 +07:00
|
|
|
.has_fpga_dbg = 1,
|
2013-05-07 05:37:36 +07:00
|
|
|
.has_fbc = 1,
|
2013-05-29 09:22:22 +07:00
|
|
|
.has_vebox_ring = 1,
|
2011-04-29 04:32:07 +07:00
|
|
|
};
|
|
|
|
|
2010-07-06 00:01:47 +07:00
|
|
|
static const struct pci_device_id pciidlist[] = { /* aka */
|
|
|
|
INTEL_VGA_DEVICE(0x3577, &intel_i830_info), /* I830_M */
|
|
|
|
INTEL_VGA_DEVICE(0x2562, &intel_845g_info), /* 845_G */
|
|
|
|
INTEL_VGA_DEVICE(0x3582, &intel_i85x_info), /* I855_GM */
|
2010-04-16 01:03:30 +07:00
|
|
|
INTEL_VGA_DEVICE(0x358e, &intel_i85x_info),
|
2010-07-06 00:01:47 +07:00
|
|
|
INTEL_VGA_DEVICE(0x2572, &intel_i865g_info), /* I865_G */
|
|
|
|
INTEL_VGA_DEVICE(0x2582, &intel_i915g_info), /* I915_G */
|
|
|
|
INTEL_VGA_DEVICE(0x258a, &intel_i915g_info), /* E7221_G */
|
|
|
|
INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info), /* I915_GM */
|
|
|
|
INTEL_VGA_DEVICE(0x2772, &intel_i945g_info), /* I945_G */
|
|
|
|
INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info), /* I945_GM */
|
|
|
|
INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info), /* I945_GME */
|
|
|
|
INTEL_VGA_DEVICE(0x2972, &intel_i965g_info), /* I946_GZ */
|
|
|
|
INTEL_VGA_DEVICE(0x2982, &intel_i965g_info), /* G35_G */
|
|
|
|
INTEL_VGA_DEVICE(0x2992, &intel_i965g_info), /* I965_Q */
|
|
|
|
INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info), /* I965_G */
|
|
|
|
INTEL_VGA_DEVICE(0x29b2, &intel_g33_info), /* Q35_G */
|
|
|
|
INTEL_VGA_DEVICE(0x29c2, &intel_g33_info), /* G33_G */
|
|
|
|
INTEL_VGA_DEVICE(0x29d2, &intel_g33_info), /* Q33_G */
|
|
|
|
INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info), /* I965_GM */
|
|
|
|
INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info), /* I965_GME */
|
|
|
|
INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info), /* GM45_G */
|
|
|
|
INTEL_VGA_DEVICE(0x2e02, &intel_g45_info), /* IGD_E_G */
|
|
|
|
INTEL_VGA_DEVICE(0x2e12, &intel_g45_info), /* Q45_G */
|
|
|
|
INTEL_VGA_DEVICE(0x2e22, &intel_g45_info), /* G45_G */
|
|
|
|
INTEL_VGA_DEVICE(0x2e32, &intel_g45_info), /* G41_G */
|
|
|
|
INTEL_VGA_DEVICE(0x2e42, &intel_g45_info), /* B43_G */
|
2010-09-17 14:22:30 +07:00
|
|
|
INTEL_VGA_DEVICE(0x2e92, &intel_g45_info), /* B43_G.1 */
|
2009-12-17 03:16:16 +07:00
|
|
|
INTEL_VGA_DEVICE(0xa001, &intel_pineview_info),
|
|
|
|
INTEL_VGA_DEVICE(0xa011, &intel_pineview_info),
|
|
|
|
INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info),
|
|
|
|
INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info),
|
2009-11-03 03:08:22 +07:00
|
|
|
INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info),
|
2010-09-07 12:45:32 +07:00
|
|
|
INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info),
|
|
|
|
INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info),
|
2010-01-08 06:08:18 +07:00
|
|
|
INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info),
|
2010-09-07 12:45:32 +07:00
|
|
|
INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info),
|
2010-08-19 08:46:16 +07:00
|
|
|
INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info),
|
2010-09-07 12:45:32 +07:00
|
|
|
INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info),
|
2011-04-29 04:32:07 +07:00
|
|
|
INTEL_VGA_DEVICE(0x0156, &intel_ivybridge_m_info), /* GT1 mobile */
|
|
|
|
INTEL_VGA_DEVICE(0x0166, &intel_ivybridge_m_info), /* GT2 mobile */
|
|
|
|
INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */
|
|
|
|
INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */
|
|
|
|
INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */
|
2013-04-06 03:12:45 +07:00
|
|
|
INTEL_QUANTA_VGA_DEVICE(&intel_ivybridge_q_info), /* Quanta transcode */
|
2012-03-30 06:55:48 +07:00
|
|
|
INTEL_VGA_DEVICE(0x016a, &intel_ivybridge_d_info), /* GT2 server */
|
2012-05-10 01:37:32 +07:00
|
|
|
INTEL_VGA_DEVICE(0x0402, &intel_haswell_d_info), /* GT1 desktop */
|
|
|
|
INTEL_VGA_DEVICE(0x0412, &intel_haswell_d_info), /* GT2 desktop */
|
2013-05-14 04:12:25 +07:00
|
|
|
INTEL_VGA_DEVICE(0x0422, &intel_haswell_d_info), /* GT3 desktop */
|
2012-05-10 01:37:32 +07:00
|
|
|
INTEL_VGA_DEVICE(0x040a, &intel_haswell_d_info), /* GT1 server */
|
|
|
|
INTEL_VGA_DEVICE(0x041a, &intel_haswell_d_info), /* GT2 server */
|
2013-05-14 04:12:25 +07:00
|
|
|
INTEL_VGA_DEVICE(0x042a, &intel_haswell_d_info), /* GT3 server */
|
2012-05-10 01:37:32 +07:00
|
|
|
INTEL_VGA_DEVICE(0x0406, &intel_haswell_m_info), /* GT1 mobile */
|
|
|
|
INTEL_VGA_DEVICE(0x0416, &intel_haswell_m_info), /* GT2 mobile */
|
2012-08-07 04:45:01 +07:00
|
|
|
INTEL_VGA_DEVICE(0x0426, &intel_haswell_m_info), /* GT2 mobile */
|
2013-05-14 04:12:25 +07:00
|
|
|
INTEL_VGA_DEVICE(0x040B, &intel_haswell_d_info), /* GT1 reserved */
|
|
|
|
INTEL_VGA_DEVICE(0x041B, &intel_haswell_d_info), /* GT2 reserved */
|
|
|
|
INTEL_VGA_DEVICE(0x042B, &intel_haswell_d_info), /* GT3 reserved */
|
|
|
|
INTEL_VGA_DEVICE(0x040E, &intel_haswell_d_info), /* GT1 reserved */
|
|
|
|
INTEL_VGA_DEVICE(0x041E, &intel_haswell_d_info), /* GT2 reserved */
|
|
|
|
INTEL_VGA_DEVICE(0x042E, &intel_haswell_d_info), /* GT3 reserved */
|
2012-08-07 04:45:01 +07:00
|
|
|
INTEL_VGA_DEVICE(0x0C02, &intel_haswell_d_info), /* SDV GT1 desktop */
|
|
|
|
INTEL_VGA_DEVICE(0x0C12, &intel_haswell_d_info), /* SDV GT2 desktop */
|
2013-05-14 04:12:25 +07:00
|
|
|
INTEL_VGA_DEVICE(0x0C22, &intel_haswell_d_info), /* SDV GT3 desktop */
|
2012-08-07 04:45:01 +07:00
|
|
|
INTEL_VGA_DEVICE(0x0C0A, &intel_haswell_d_info), /* SDV GT1 server */
|
|
|
|
INTEL_VGA_DEVICE(0x0C1A, &intel_haswell_d_info), /* SDV GT2 server */
|
2013-05-14 04:12:25 +07:00
|
|
|
INTEL_VGA_DEVICE(0x0C2A, &intel_haswell_d_info), /* SDV GT3 server */
|
2012-08-07 04:45:01 +07:00
|
|
|
INTEL_VGA_DEVICE(0x0C06, &intel_haswell_m_info), /* SDV GT1 mobile */
|
|
|
|
INTEL_VGA_DEVICE(0x0C16, &intel_haswell_m_info), /* SDV GT2 mobile */
|
2013-05-14 04:12:25 +07:00
|
|
|
INTEL_VGA_DEVICE(0x0C26, &intel_haswell_m_info), /* SDV GT3 mobile */
|
|
|
|
INTEL_VGA_DEVICE(0x0C0B, &intel_haswell_d_info), /* SDV GT1 reserved */
|
|
|
|
INTEL_VGA_DEVICE(0x0C1B, &intel_haswell_d_info), /* SDV GT2 reserved */
|
|
|
|
INTEL_VGA_DEVICE(0x0C2B, &intel_haswell_d_info), /* SDV GT3 reserved */
|
|
|
|
INTEL_VGA_DEVICE(0x0C0E, &intel_haswell_d_info), /* SDV GT1 reserved */
|
|
|
|
INTEL_VGA_DEVICE(0x0C1E, &intel_haswell_d_info), /* SDV GT2 reserved */
|
|
|
|
INTEL_VGA_DEVICE(0x0C2E, &intel_haswell_d_info), /* SDV GT3 reserved */
|
2012-08-07 04:45:01 +07:00
|
|
|
INTEL_VGA_DEVICE(0x0A02, &intel_haswell_d_info), /* ULT GT1 desktop */
|
|
|
|
INTEL_VGA_DEVICE(0x0A12, &intel_haswell_d_info), /* ULT GT2 desktop */
|
2013-05-14 04:12:25 +07:00
|
|
|
INTEL_VGA_DEVICE(0x0A22, &intel_haswell_d_info), /* ULT GT3 desktop */
|
2012-08-07 04:45:01 +07:00
|
|
|
INTEL_VGA_DEVICE(0x0A0A, &intel_haswell_d_info), /* ULT GT1 server */
|
|
|
|
INTEL_VGA_DEVICE(0x0A1A, &intel_haswell_d_info), /* ULT GT2 server */
|
2013-05-14 04:12:25 +07:00
|
|
|
INTEL_VGA_DEVICE(0x0A2A, &intel_haswell_d_info), /* ULT GT3 server */
|
2012-08-07 04:45:01 +07:00
|
|
|
INTEL_VGA_DEVICE(0x0A06, &intel_haswell_m_info), /* ULT GT1 mobile */
|
|
|
|
INTEL_VGA_DEVICE(0x0A16, &intel_haswell_m_info), /* ULT GT2 mobile */
|
2013-05-14 04:12:25 +07:00
|
|
|
INTEL_VGA_DEVICE(0x0A26, &intel_haswell_m_info), /* ULT GT3 mobile */
|
|
|
|
INTEL_VGA_DEVICE(0x0A0B, &intel_haswell_d_info), /* ULT GT1 reserved */
|
|
|
|
INTEL_VGA_DEVICE(0x0A1B, &intel_haswell_d_info), /* ULT GT2 reserved */
|
|
|
|
INTEL_VGA_DEVICE(0x0A2B, &intel_haswell_d_info), /* ULT GT3 reserved */
|
|
|
|
INTEL_VGA_DEVICE(0x0A0E, &intel_haswell_m_info), /* ULT GT1 reserved */
|
|
|
|
INTEL_VGA_DEVICE(0x0A1E, &intel_haswell_m_info), /* ULT GT2 reserved */
|
|
|
|
INTEL_VGA_DEVICE(0x0A2E, &intel_haswell_m_info), /* ULT GT3 reserved */
|
2013-03-02 08:00:50 +07:00
|
|
|
INTEL_VGA_DEVICE(0x0D02, &intel_haswell_d_info), /* CRW GT1 desktop */
|
|
|
|
INTEL_VGA_DEVICE(0x0D12, &intel_haswell_d_info), /* CRW GT2 desktop */
|
2013-05-14 04:12:25 +07:00
|
|
|
INTEL_VGA_DEVICE(0x0D22, &intel_haswell_d_info), /* CRW GT3 desktop */
|
2013-03-02 08:00:50 +07:00
|
|
|
INTEL_VGA_DEVICE(0x0D0A, &intel_haswell_d_info), /* CRW GT1 server */
|
|
|
|
INTEL_VGA_DEVICE(0x0D1A, &intel_haswell_d_info), /* CRW GT2 server */
|
2013-05-14 04:12:25 +07:00
|
|
|
INTEL_VGA_DEVICE(0x0D2A, &intel_haswell_d_info), /* CRW GT3 server */
|
2013-03-02 08:00:50 +07:00
|
|
|
INTEL_VGA_DEVICE(0x0D06, &intel_haswell_m_info), /* CRW GT1 mobile */
|
|
|
|
INTEL_VGA_DEVICE(0x0D16, &intel_haswell_m_info), /* CRW GT2 mobile */
|
2013-05-14 04:12:25 +07:00
|
|
|
INTEL_VGA_DEVICE(0x0D26, &intel_haswell_m_info), /* CRW GT3 mobile */
|
|
|
|
INTEL_VGA_DEVICE(0x0D0B, &intel_haswell_d_info), /* CRW GT1 reserved */
|
|
|
|
INTEL_VGA_DEVICE(0x0D1B, &intel_haswell_d_info), /* CRW GT2 reserved */
|
|
|
|
INTEL_VGA_DEVICE(0x0D2B, &intel_haswell_d_info), /* CRW GT3 reserved */
|
|
|
|
INTEL_VGA_DEVICE(0x0D0E, &intel_haswell_d_info), /* CRW GT1 reserved */
|
|
|
|
INTEL_VGA_DEVICE(0x0D1E, &intel_haswell_d_info), /* CRW GT2 reserved */
|
|
|
|
INTEL_VGA_DEVICE(0x0D2E, &intel_haswell_d_info), /* CRW GT3 reserved */
|
2012-06-21 00:53:13 +07:00
|
|
|
INTEL_VGA_DEVICE(0x0f30, &intel_valleyview_m_info),
|
2013-03-09 01:45:50 +07:00
|
|
|
INTEL_VGA_DEVICE(0x0f31, &intel_valleyview_m_info),
|
|
|
|
INTEL_VGA_DEVICE(0x0f32, &intel_valleyview_m_info),
|
|
|
|
INTEL_VGA_DEVICE(0x0f33, &intel_valleyview_m_info),
|
2012-06-21 00:53:13 +07:00
|
|
|
INTEL_VGA_DEVICE(0x0157, &intel_valleyview_m_info),
|
|
|
|
INTEL_VGA_DEVICE(0x0155, &intel_valleyview_d_info),
|
2009-12-17 03:16:15 +07:00
|
|
|
{0, 0, 0}
|
2005-04-17 05:20:36 +07:00
|
|
|
};
|
|
|
|
|
DRM: i915: add mode setting support
This commit adds i915 driver support for the DRM mode setting APIs.
Currently, VGA, LVDS, SDVO DVI & VGA, TV and DVO LVDS outputs are
supported. HDMI, DisplayPort and additional SDVO output support will
follow.
Support for the mode setting code is controlled by the new 'modeset'
module option. A new config option, CONFIG_DRM_I915_KMS controls the
default behavior, and whether a PCI ID list is built into the module for
use by user level module utilities.
Note that if mode setting is enabled, user level drivers that access
display registers directly or that don't use the kernel graphics memory
manager will likely corrupt kernel graphics memory, disrupt output
configuration (possibly leading to hangs and/or blank displays), and
prevent panic/oops messages from appearing. So use caution when
enabling this code; be sure your user level code supports the new
interfaces.
A new SysRq key, 'g', provides emergency support for switching back to
the kernel's framebuffer console; which is useful for testing.
Co-authors: Dave Airlie <airlied@linux.ie>, Hong Liu <hong.liu@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2008-11-08 05:24:08 +07:00
|
|
|
#if defined(CONFIG_DRM_I915_KMS)
|
|
|
|
MODULE_DEVICE_TABLE(pci, pciidlist);
|
|
|
|
#endif
|
|
|
|
|
2011-08-17 02:34:10 +07:00
|
|
|
void intel_detect_pch(struct drm_device *dev)
|
2010-04-07 15:15:53 +07:00
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
struct pci_dev *pch;
|
|
|
|
|
2013-04-06 03:12:44 +07:00
|
|
|
/* In all current cases, num_pipes is equivalent to the PCH_NOP setting
|
|
|
|
* (which really amounts to a PCH but no South Display).
|
|
|
|
*/
|
|
|
|
if (INTEL_INFO(dev)->num_pipes == 0) {
|
|
|
|
dev_priv->pch_type = PCH_NOP;
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2010-04-07 15:15:53 +07:00
|
|
|
/*
|
|
|
|
* The reason to probe ISA bridge instead of Dev31:Fun0 is to
|
|
|
|
* make graphics device passthrough work easy for VMM, that only
|
|
|
|
* need to expose ISA bridge to let driver know the real hardware
|
|
|
|
* underneath. This is a requirement from virtualization team.
|
2013-06-19 20:10:23 +07:00
|
|
|
*
|
|
|
|
* In some virtualized environments (e.g. XEN), there is irrelevant
|
|
|
|
* ISA bridge in the system. To work reliably, we should scan trhough
|
|
|
|
* all the ISA bridge devices and check for the first match, instead
|
|
|
|
* of only checking the first one.
|
2010-04-07 15:15:53 +07:00
|
|
|
*/
|
|
|
|
pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
|
2013-06-19 20:10:23 +07:00
|
|
|
while (pch) {
|
|
|
|
struct pci_dev *curr = pch;
|
2010-04-07 15:15:53 +07:00
|
|
|
if (pch->vendor == PCI_VENDOR_ID_INTEL) {
|
2012-11-21 00:12:07 +07:00
|
|
|
unsigned short id;
|
2010-04-07 15:15:53 +07:00
|
|
|
id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
|
2012-11-21 00:12:07 +07:00
|
|
|
dev_priv->pch_id = id;
|
2010-04-07 15:15:53 +07:00
|
|
|
|
2011-04-29 04:48:02 +07:00
|
|
|
if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
|
|
|
|
dev_priv->pch_type = PCH_IBX;
|
|
|
|
DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
|
2012-11-01 04:52:27 +07:00
|
|
|
WARN_ON(!IS_GEN5(dev));
|
2011-04-29 04:48:02 +07:00
|
|
|
} else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
|
2010-04-07 15:15:53 +07:00
|
|
|
dev_priv->pch_type = PCH_CPT;
|
|
|
|
DRM_DEBUG_KMS("Found CougarPoint PCH\n");
|
2012-11-01 04:52:27 +07:00
|
|
|
WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
|
2011-04-08 02:33:56 +07:00
|
|
|
} else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
|
|
|
|
/* PantherPoint is CPT compatible */
|
|
|
|
dev_priv->pch_type = PCH_CPT;
|
|
|
|
DRM_DEBUG_KMS("Found PatherPoint PCH\n");
|
2012-11-01 04:52:27 +07:00
|
|
|
WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
|
2012-03-29 22:32:20 +07:00
|
|
|
} else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
|
|
|
|
dev_priv->pch_type = PCH_LPT;
|
|
|
|
DRM_DEBUG_KMS("Found LynxPoint PCH\n");
|
2012-11-01 04:52:27 +07:00
|
|
|
WARN_ON(!IS_HASWELL(dev));
|
2013-04-13 04:16:54 +07:00
|
|
|
WARN_ON(IS_ULT(dev));
|
2012-11-13 03:54:13 +07:00
|
|
|
} else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
|
|
|
|
dev_priv->pch_type = PCH_LPT;
|
|
|
|
DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
|
|
|
|
WARN_ON(!IS_HASWELL(dev));
|
2013-04-13 04:16:54 +07:00
|
|
|
WARN_ON(!IS_ULT(dev));
|
2013-06-19 20:10:23 +07:00
|
|
|
} else {
|
|
|
|
goto check_next;
|
2010-04-07 15:15:53 +07:00
|
|
|
}
|
2013-06-19 20:10:23 +07:00
|
|
|
pci_dev_put(pch);
|
|
|
|
break;
|
2010-04-07 15:15:53 +07:00
|
|
|
}
|
2013-06-19 20:10:23 +07:00
|
|
|
check_next:
|
|
|
|
pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, curr);
|
|
|
|
pci_dev_put(curr);
|
2010-04-07 15:15:53 +07:00
|
|
|
}
|
2013-06-19 20:10:23 +07:00
|
|
|
if (!pch)
|
|
|
|
DRM_DEBUG_KMS("No PCH found?\n");
|
2010-04-07 15:15:53 +07:00
|
|
|
}
|
|
|
|
|
2012-04-06 04:47:36 +07:00
|
|
|
bool i915_semaphore_is_enabled(struct drm_device *dev)
|
|
|
|
{
|
|
|
|
if (INTEL_INFO(dev)->gen < 6)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
if (i915_semaphores >= 0)
|
|
|
|
return i915_semaphores;
|
|
|
|
|
2012-04-03 01:48:43 +07:00
|
|
|
#ifdef CONFIG_INTEL_IOMMU
|
2012-04-06 04:47:36 +07:00
|
|
|
/* Enable semaphores on SNB when IO remapping is off */
|
2012-04-03 01:48:43 +07:00
|
|
|
if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
|
|
|
|
return false;
|
|
|
|
#endif
|
2012-04-06 04:47:36 +07:00
|
|
|
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
|
2010-02-08 03:48:24 +07:00
|
|
|
static int i915_drm_freeze(struct drm_device *dev)
|
2007-11-22 11:14:14 +07:00
|
|
|
{
|
2010-02-19 05:06:27 +07:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2013-03-26 23:25:45 +07:00
|
|
|
struct drm_crtc *crtc;
|
2010-02-19 05:06:27 +07:00
|
|
|
|
i915: ignore lid open event when resuming
i915 driver needs to do modeset when
1. system resumes from sleep
2. lid is opened
In PM_SUSPEND_MEM state, all the GPEs are cleared when system resumes,
thus it is the i915_resume code does the modeset rather than intel_lid_notify().
But in PM_SUSPEND_FREEZE state, this will be broken because
system is still responsive to the lid events.
1. When we close the lid in Freeze state, intel_lid_notify() sets modeset_on_lid.
2. When we reopen the lid, intel_lid_notify() will do a modeset,
before the system is resumed.
here is the error log,
[92146.548074] WARNING: at drivers/gpu/drm/i915/intel_display.c:1028 intel_wait_for_pipe_off+0x184/0x190 [i915]()
[92146.548076] Hardware name: VGN-Z540N
[92146.548078] pipe_off wait timed out
[92146.548167] Modules linked in: hid_generic usbhid hid snd_hda_codec_realtek snd_hda_intel snd_hda_codec parport_pc snd_hwdep ppdev snd_pcm_oss i915 snd_mixer_oss snd_pcm arc4 iwldvm snd_seq_dummy mac80211 snd_seq_oss snd_seq_midi fbcon tileblit font bitblit softcursor drm_kms_helper snd_rawmidi snd_seq_midi_event coretemp drm snd_seq kvm btusb bluetooth snd_timer iwlwifi pcmcia tpm_infineon i2c_algo_bit joydev snd_seq_device intel_agp cfg80211 snd intel_gtt yenta_socket pcmcia_rsrc sony_laptop agpgart microcode psmouse tpm_tis serio_raw mxm_wmi soundcore snd_page_alloc tpm acpi_cpufreq lpc_ich pcmcia_core tpm_bios mperf processor lp parport firewire_ohci firewire_core crc_itu_t sdhci_pci sdhci thermal e1000e
[92146.548173] Pid: 4304, comm: kworker/0:0 Tainted: G W 3.8.0-rc3-s0i3-v3-test+ #9
[92146.548175] Call Trace:
[92146.548189] [<c10378e2>] warn_slowpath_common+0x72/0xa0
[92146.548227] [<f86398b4>] ? intel_wait_for_pipe_off+0x184/0x190 [i915]
[92146.548263] [<f86398b4>] ? intel_wait_for_pipe_off+0x184/0x190 [i915]
[92146.548270] [<c10379b3>] warn_slowpath_fmt+0x33/0x40
[92146.548307] [<f86398b4>] intel_wait_for_pipe_off+0x184/0x190 [i915]
[92146.548344] [<f86399c2>] intel_disable_pipe+0x102/0x190 [i915]
[92146.548380] [<f8639ea4>] ? intel_disable_plane+0x64/0x80 [i915]
[92146.548417] [<f8639f7c>] i9xx_crtc_disable+0xbc/0x150 [i915]
[92146.548456] [<f863ebee>] intel_crtc_update_dpms+0x5e/0x90 [i915]
[92146.548493] [<f86437cf>] intel_modeset_setup_hw_state+0x42f/0x8f0 [i915]
[92146.548535] [<f8645b0b>] intel_lid_notify+0x9b/0xc0 [i915]
[92146.548543] [<c15610d3>] notifier_call_chain+0x43/0x60
[92146.548550] [<c105d1e1>] __blocking_notifier_call_chain+0x41/0x80
[92146.548556] [<c105d23f>] blocking_notifier_call_chain+0x1f/0x30
[92146.548563] [<c131a684>] acpi_lid_send_state+0x78/0xa4
[92146.548569] [<c131aa9e>] acpi_button_notify+0x3b/0xf1
[92146.548577] [<c12df56a>] ? acpi_os_execute+0x17/0x19
[92146.548582] [<c12e591a>] ? acpi_ec_sync_query+0xa5/0xbc
[92146.548589] [<c12e2b82>] acpi_device_notify+0x16/0x18
[92146.548595] [<c12f4904>] acpi_ev_notify_dispatch+0x38/0x4f
[92146.548600] [<c12df0e8>] acpi_os_execute_deferred+0x20/0x2b
[92146.548607] [<c1051208>] process_one_work+0x128/0x3f0
[92146.548613] [<c1564f73>] ? common_interrupt+0x33/0x38
[92146.548618] [<c104f8c0>] ? wake_up_worker+0x30/0x30
[92146.548624] [<c12df0c8>] ? acpi_os_wait_events_complete+0x1e/0x1e
[92146.548629] [<c10524f9>] worker_thread+0x119/0x3b0
[92146.548634] [<c10523e0>] ? manage_workers+0x240/0x240
[92146.548640] [<c1056e84>] kthread+0x94/0xa0
[92146.548647] [<c1060000>] ? ftrace_raw_output_sched_stat_runtime+0x70/0xf0
[92146.548652] [<c15649b7>] ret_from_kernel_thread+0x1b/0x28
[92146.548658] [<c1056df0>] ? kthread_create_on_node+0xc0/0xc0
three different modeset flags are introduced in this patch
MODESET_ON_LID_OPEN: do modeset on next lid open event
MODESET_DONE: modeset already done
MODESET_SUSPENDED: suspended, only do modeset when system is resumed
In this way,
1. when lid is closed, MODESET_ON_LID_OPEN is set so that
we'll do modeset on next lid open event.
2. when lid is opened, MODESET_DONE is set
so that duplicate lid open events will be ignored.
3. when system suspends, MODESET_SUSPENDED is set.
In this case, we will not do modeset on any lid events.
Plus, locking mechanism is also introduced to avoid racing.
Signed-off-by: Zhang Rui <rui.zhang@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-02-05 14:41:53 +07:00
|
|
|
/* ignore lid events during suspend */
|
|
|
|
mutex_lock(&dev_priv->modeset_restore_lock);
|
|
|
|
dev_priv->modeset_restore = MODESET_SUSPENDED;
|
|
|
|
mutex_unlock(&dev_priv->modeset_restore_lock);
|
|
|
|
|
2013-01-26 01:59:15 +07:00
|
|
|
intel_set_power_well(dev, true);
|
|
|
|
|
2010-12-07 06:20:40 +07:00
|
|
|
drm_kms_helper_poll_disable(dev);
|
|
|
|
|
2007-11-22 11:14:14 +07:00
|
|
|
pci_save_state(dev->pdev);
|
|
|
|
|
2009-02-18 06:13:31 +07:00
|
|
|
/* If KMS is active, we do the leavevt stuff here */
|
2009-02-24 06:41:09 +07:00
|
|
|
if (drm_core_check_feature(dev, DRIVER_MODESET)) {
|
2013-07-09 21:51:37 +07:00
|
|
|
int error;
|
|
|
|
|
|
|
|
mutex_lock(&dev->struct_mutex);
|
|
|
|
error = i915_gem_idle(dev);
|
|
|
|
mutex_unlock(&dev->struct_mutex);
|
2010-02-08 03:48:24 +07:00
|
|
|
if (error) {
|
2009-02-24 06:41:09 +07:00
|
|
|
dev_err(&dev->pdev->dev,
|
2010-02-08 03:48:24 +07:00
|
|
|
"GEM idle failed, resume might fail\n");
|
|
|
|
return error;
|
|
|
|
}
|
2012-07-27 00:21:47 +07:00
|
|
|
|
2012-11-03 01:14:00 +07:00
|
|
|
cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
|
|
|
|
|
2009-02-24 06:41:09 +07:00
|
|
|
drm_irq_uninstall(dev);
|
2013-03-05 15:50:58 +07:00
|
|
|
dev_priv->enable_hotplug_processing = false;
|
2013-03-26 23:25:45 +07:00
|
|
|
/*
|
|
|
|
* Disable CRTCs directly since we want to preserve sw state
|
|
|
|
* for _thaw.
|
|
|
|
*/
|
|
|
|
list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
|
|
|
|
dev_priv->display.crtc_disable(crtc);
|
2013-04-17 18:04:50 +07:00
|
|
|
|
|
|
|
intel_modeset_suspend_hw(dev);
|
2009-02-18 06:13:31 +07:00
|
|
|
}
|
|
|
|
|
2009-06-23 08:05:12 +07:00
|
|
|
i915_save_state(dev);
|
|
|
|
|
2010-08-19 22:09:23 +07:00
|
|
|
intel_opregion_fini(dev);
|
2008-08-06 01:37:25 +07:00
|
|
|
|
2012-03-28 16:48:49 +07:00
|
|
|
console_lock();
|
2013-06-10 21:48:09 +07:00
|
|
|
intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED);
|
2012-03-28 16:48:49 +07:00
|
|
|
console_unlock();
|
|
|
|
|
2010-02-19 05:06:27 +07:00
|
|
|
return 0;
|
2010-02-08 03:48:24 +07:00
|
|
|
}
|
|
|
|
|
2010-02-01 12:38:10 +07:00
|
|
|
int i915_suspend(struct drm_device *dev, pm_message_t state)
|
2010-02-08 03:48:24 +07:00
|
|
|
{
|
|
|
|
int error;
|
|
|
|
|
|
|
|
if (!dev || !dev->dev_private) {
|
|
|
|
DRM_ERROR("dev: %p\n", dev);
|
|
|
|
DRM_ERROR("DRM not initialized, aborting suspend.\n");
|
|
|
|
return -ENODEV;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (state.event == PM_EVENT_PRETHAW)
|
|
|
|
return 0;
|
|
|
|
|
2010-12-07 06:20:40 +07:00
|
|
|
|
|
|
|
if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
|
|
|
|
return 0;
|
2010-09-08 15:45:11 +07:00
|
|
|
|
2010-02-08 03:48:24 +07:00
|
|
|
error = i915_drm_freeze(dev);
|
|
|
|
if (error)
|
|
|
|
return error;
|
|
|
|
|
2008-02-20 07:02:20 +07:00
|
|
|
if (state.event == PM_EVENT_SUSPEND) {
|
|
|
|
/* Shut down the device */
|
|
|
|
pci_disable_device(dev->pdev);
|
|
|
|
pci_set_power_state(dev->pdev, PCI_D3hot);
|
|
|
|
}
|
2007-11-22 11:14:14 +07:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2012-11-03 01:13:59 +07:00
|
|
|
void intel_console_resume(struct work_struct *work)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv =
|
|
|
|
container_of(work, struct drm_i915_private,
|
|
|
|
console_resume_work);
|
|
|
|
struct drm_device *dev = dev_priv->dev;
|
|
|
|
|
|
|
|
console_lock();
|
2013-06-10 21:48:09 +07:00
|
|
|
intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING);
|
2012-11-03 01:13:59 +07:00
|
|
|
console_unlock();
|
|
|
|
}
|
|
|
|
|
2013-03-26 23:25:46 +07:00
|
|
|
static void intel_resume_hotplug(struct drm_device *dev)
|
|
|
|
{
|
|
|
|
struct drm_mode_config *mode_config = &dev->mode_config;
|
|
|
|
struct intel_encoder *encoder;
|
|
|
|
|
|
|
|
mutex_lock(&mode_config->mutex);
|
|
|
|
DRM_DEBUG_KMS("running encoder hotplug functions\n");
|
|
|
|
|
|
|
|
list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
|
|
|
|
if (encoder->hot_plug)
|
|
|
|
encoder->hot_plug(encoder);
|
|
|
|
|
|
|
|
mutex_unlock(&mode_config->mutex);
|
|
|
|
|
|
|
|
/* Just fire off a uevent and let userspace tell us what to do */
|
|
|
|
drm_helper_hpd_irq_event(dev);
|
|
|
|
}
|
|
|
|
|
2012-11-03 01:14:02 +07:00
|
|
|
static int __i915_drm_thaw(struct drm_device *dev)
|
2007-11-22 11:14:14 +07:00
|
|
|
{
|
2009-02-18 06:13:31 +07:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2010-02-08 03:48:24 +07:00
|
|
|
int error = 0;
|
2008-08-06 01:37:25 +07:00
|
|
|
|
2010-02-19 05:06:27 +07:00
|
|
|
i915_restore_state(dev);
|
2010-08-19 22:09:23 +07:00
|
|
|
intel_opregion_setup(dev);
|
2010-02-19 05:06:27 +07:00
|
|
|
|
2009-02-18 06:13:31 +07:00
|
|
|
/* KMS EnterVT equivalent */
|
|
|
|
if (drm_core_check_feature(dev, DRIVER_MODESET)) {
|
2012-12-01 21:04:25 +07:00
|
|
|
intel_init_pch_refclk(dev);
|
2012-05-09 17:56:28 +07:00
|
|
|
|
2009-02-18 06:13:31 +07:00
|
|
|
mutex_lock(&dev->struct_mutex);
|
|
|
|
|
2012-02-02 15:58:12 +07:00
|
|
|
error = i915_gem_init_hw(dev);
|
2009-02-18 06:13:31 +07:00
|
|
|
mutex_unlock(&dev->struct_mutex);
|
2009-02-24 06:41:09 +07:00
|
|
|
|
2013-03-05 15:50:58 +07:00
|
|
|
/* We need working interrupts for modeset enabling ... */
|
|
|
|
drm_irq_install(dev);
|
|
|
|
|
2012-05-09 17:56:28 +07:00
|
|
|
intel_modeset_init_hw(dev);
|
2013-03-26 23:25:45 +07:00
|
|
|
|
|
|
|
drm_modeset_lock_all(dev);
|
|
|
|
intel_modeset_setup_hw_state(dev, true);
|
|
|
|
drm_modeset_unlock_all(dev);
|
2013-03-05 15:50:58 +07:00
|
|
|
|
|
|
|
/*
|
|
|
|
* ... but also need to make sure that hotplug processing
|
|
|
|
* doesn't cause havoc. Like in the driver load code we don't
|
|
|
|
* bother with the tiny race here where we might loose hotplug
|
|
|
|
* notifications.
|
|
|
|
* */
|
2012-12-11 20:05:07 +07:00
|
|
|
intel_hpd_init(dev);
|
2013-03-05 15:50:58 +07:00
|
|
|
dev_priv->enable_hotplug_processing = true;
|
2013-03-26 23:25:46 +07:00
|
|
|
/* Config may have changed between suspend and resume */
|
|
|
|
intel_resume_hotplug(dev);
|
2011-01-06 03:01:26 +07:00
|
|
|
}
|
2011-01-06 03:01:25 +07:00
|
|
|
|
2010-08-19 22:09:23 +07:00
|
|
|
intel_opregion_init(dev);
|
|
|
|
|
2012-11-03 01:13:59 +07:00
|
|
|
/*
|
|
|
|
* The console lock can be pretty contented on resume due
|
|
|
|
* to all the printk activity. Try to keep it out of the hot
|
|
|
|
* path of resume if possible.
|
|
|
|
*/
|
|
|
|
if (console_trylock()) {
|
2013-06-10 21:48:09 +07:00
|
|
|
intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING);
|
2012-11-03 01:13:59 +07:00
|
|
|
console_unlock();
|
|
|
|
} else {
|
|
|
|
schedule_work(&dev_priv->console_resume_work);
|
|
|
|
}
|
|
|
|
|
i915: ignore lid open event when resuming
i915 driver needs to do modeset when
1. system resumes from sleep
2. lid is opened
In PM_SUSPEND_MEM state, all the GPEs are cleared when system resumes,
thus it is the i915_resume code does the modeset rather than intel_lid_notify().
But in PM_SUSPEND_FREEZE state, this will be broken because
system is still responsive to the lid events.
1. When we close the lid in Freeze state, intel_lid_notify() sets modeset_on_lid.
2. When we reopen the lid, intel_lid_notify() will do a modeset,
before the system is resumed.
here is the error log,
[92146.548074] WARNING: at drivers/gpu/drm/i915/intel_display.c:1028 intel_wait_for_pipe_off+0x184/0x190 [i915]()
[92146.548076] Hardware name: VGN-Z540N
[92146.548078] pipe_off wait timed out
[92146.548167] Modules linked in: hid_generic usbhid hid snd_hda_codec_realtek snd_hda_intel snd_hda_codec parport_pc snd_hwdep ppdev snd_pcm_oss i915 snd_mixer_oss snd_pcm arc4 iwldvm snd_seq_dummy mac80211 snd_seq_oss snd_seq_midi fbcon tileblit font bitblit softcursor drm_kms_helper snd_rawmidi snd_seq_midi_event coretemp drm snd_seq kvm btusb bluetooth snd_timer iwlwifi pcmcia tpm_infineon i2c_algo_bit joydev snd_seq_device intel_agp cfg80211 snd intel_gtt yenta_socket pcmcia_rsrc sony_laptop agpgart microcode psmouse tpm_tis serio_raw mxm_wmi soundcore snd_page_alloc tpm acpi_cpufreq lpc_ich pcmcia_core tpm_bios mperf processor lp parport firewire_ohci firewire_core crc_itu_t sdhci_pci sdhci thermal e1000e
[92146.548173] Pid: 4304, comm: kworker/0:0 Tainted: G W 3.8.0-rc3-s0i3-v3-test+ #9
[92146.548175] Call Trace:
[92146.548189] [<c10378e2>] warn_slowpath_common+0x72/0xa0
[92146.548227] [<f86398b4>] ? intel_wait_for_pipe_off+0x184/0x190 [i915]
[92146.548263] [<f86398b4>] ? intel_wait_for_pipe_off+0x184/0x190 [i915]
[92146.548270] [<c10379b3>] warn_slowpath_fmt+0x33/0x40
[92146.548307] [<f86398b4>] intel_wait_for_pipe_off+0x184/0x190 [i915]
[92146.548344] [<f86399c2>] intel_disable_pipe+0x102/0x190 [i915]
[92146.548380] [<f8639ea4>] ? intel_disable_plane+0x64/0x80 [i915]
[92146.548417] [<f8639f7c>] i9xx_crtc_disable+0xbc/0x150 [i915]
[92146.548456] [<f863ebee>] intel_crtc_update_dpms+0x5e/0x90 [i915]
[92146.548493] [<f86437cf>] intel_modeset_setup_hw_state+0x42f/0x8f0 [i915]
[92146.548535] [<f8645b0b>] intel_lid_notify+0x9b/0xc0 [i915]
[92146.548543] [<c15610d3>] notifier_call_chain+0x43/0x60
[92146.548550] [<c105d1e1>] __blocking_notifier_call_chain+0x41/0x80
[92146.548556] [<c105d23f>] blocking_notifier_call_chain+0x1f/0x30
[92146.548563] [<c131a684>] acpi_lid_send_state+0x78/0xa4
[92146.548569] [<c131aa9e>] acpi_button_notify+0x3b/0xf1
[92146.548577] [<c12df56a>] ? acpi_os_execute+0x17/0x19
[92146.548582] [<c12e591a>] ? acpi_ec_sync_query+0xa5/0xbc
[92146.548589] [<c12e2b82>] acpi_device_notify+0x16/0x18
[92146.548595] [<c12f4904>] acpi_ev_notify_dispatch+0x38/0x4f
[92146.548600] [<c12df0e8>] acpi_os_execute_deferred+0x20/0x2b
[92146.548607] [<c1051208>] process_one_work+0x128/0x3f0
[92146.548613] [<c1564f73>] ? common_interrupt+0x33/0x38
[92146.548618] [<c104f8c0>] ? wake_up_worker+0x30/0x30
[92146.548624] [<c12df0c8>] ? acpi_os_wait_events_complete+0x1e/0x1e
[92146.548629] [<c10524f9>] worker_thread+0x119/0x3b0
[92146.548634] [<c10523e0>] ? manage_workers+0x240/0x240
[92146.548640] [<c1056e84>] kthread+0x94/0xa0
[92146.548647] [<c1060000>] ? ftrace_raw_output_sched_stat_runtime+0x70/0xf0
[92146.548652] [<c15649b7>] ret_from_kernel_thread+0x1b/0x28
[92146.548658] [<c1056df0>] ? kthread_create_on_node+0xc0/0xc0
three different modeset flags are introduced in this patch
MODESET_ON_LID_OPEN: do modeset on next lid open event
MODESET_DONE: modeset already done
MODESET_SUSPENDED: suspended, only do modeset when system is resumed
In this way,
1. when lid is closed, MODESET_ON_LID_OPEN is set so that
we'll do modeset on next lid open event.
2. when lid is opened, MODESET_DONE is set
so that duplicate lid open events will be ignored.
3. when system suspends, MODESET_SUSPENDED is set.
In this case, we will not do modeset on any lid events.
Plus, locking mechanism is also introduced to avoid racing.
Signed-off-by: Zhang Rui <rui.zhang@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-02-05 14:41:53 +07:00
|
|
|
mutex_lock(&dev_priv->modeset_restore_lock);
|
|
|
|
dev_priv->modeset_restore = MODESET_DONE;
|
|
|
|
mutex_unlock(&dev_priv->modeset_restore_lock);
|
2010-02-08 03:48:24 +07:00
|
|
|
return error;
|
|
|
|
}
|
|
|
|
|
2012-11-03 01:14:02 +07:00
|
|
|
static int i915_drm_thaw(struct drm_device *dev)
|
|
|
|
{
|
|
|
|
int error = 0;
|
|
|
|
|
2013-07-20 02:36:52 +07:00
|
|
|
intel_uncore_sanitize(dev);
|
2012-11-03 01:14:02 +07:00
|
|
|
|
|
|
|
if (drm_core_check_feature(dev, DRIVER_MODESET)) {
|
|
|
|
mutex_lock(&dev->struct_mutex);
|
|
|
|
i915_gem_restore_gtt_mappings(dev);
|
|
|
|
mutex_unlock(&dev->struct_mutex);
|
|
|
|
}
|
|
|
|
|
|
|
|
__i915_drm_thaw(dev);
|
|
|
|
|
2010-02-08 03:48:24 +07:00
|
|
|
return error;
|
|
|
|
}
|
|
|
|
|
2010-02-01 12:38:10 +07:00
|
|
|
int i915_resume(struct drm_device *dev)
|
2010-02-08 03:48:24 +07:00
|
|
|
{
|
2012-11-03 01:14:02 +07:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2010-09-08 15:45:11 +07:00
|
|
|
int ret;
|
|
|
|
|
2010-12-07 06:20:40 +07:00
|
|
|
if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
|
|
|
|
return 0;
|
|
|
|
|
2010-02-08 03:48:24 +07:00
|
|
|
if (pci_enable_device(dev->pdev))
|
|
|
|
return -EIO;
|
|
|
|
|
|
|
|
pci_set_master(dev->pdev);
|
|
|
|
|
2013-07-20 02:36:52 +07:00
|
|
|
intel_uncore_sanitize(dev);
|
2012-11-03 01:14:02 +07:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Platforms with opregion should have sane BIOS, older ones (gen3 and
|
|
|
|
* earlier) need this since the BIOS might clear all our scratch PTEs.
|
|
|
|
*/
|
|
|
|
if (drm_core_check_feature(dev, DRIVER_MODESET) &&
|
|
|
|
!dev_priv->opregion.header) {
|
|
|
|
mutex_lock(&dev->struct_mutex);
|
|
|
|
i915_gem_restore_gtt_mappings(dev);
|
|
|
|
mutex_unlock(&dev->struct_mutex);
|
|
|
|
}
|
|
|
|
|
|
|
|
ret = __i915_drm_thaw(dev);
|
2010-09-08 15:45:11 +07:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
drm_kms_helper_poll_enable(dev);
|
|
|
|
return 0;
|
2007-11-22 11:14:14 +07:00
|
|
|
}
|
|
|
|
|
2009-09-15 04:48:45 +07:00
|
|
|
/**
|
2011-11-29 01:15:17 +07:00
|
|
|
* i915_reset - reset chip after a hang
|
2009-09-15 04:48:45 +07:00
|
|
|
* @dev: drm device to reset
|
|
|
|
*
|
|
|
|
* Reset the chip. Useful if a hang is detected. Returns zero on successful
|
|
|
|
* reset or otherwise an error code.
|
|
|
|
*
|
|
|
|
* Procedure is fairly simple:
|
|
|
|
* - reset the chip using the reset reg
|
|
|
|
* - re-init context state
|
|
|
|
* - re-init hardware status page
|
|
|
|
* - re-init ring buffer
|
|
|
|
* - re-init interrupt state
|
|
|
|
* - re-init display
|
|
|
|
*/
|
2012-04-27 20:17:44 +07:00
|
|
|
int i915_reset(struct drm_device *dev)
|
2009-09-15 04:48:45 +07:00
|
|
|
{
|
|
|
|
drm_i915_private_t *dev_priv = dev->dev_private;
|
2013-05-28 16:38:44 +07:00
|
|
|
bool simulated;
|
2010-09-11 17:17:19 +07:00
|
|
|
int ret;
|
2009-09-15 04:48:45 +07:00
|
|
|
|
2010-12-23 20:33:15 +07:00
|
|
|
if (!i915_try_reset)
|
|
|
|
return 0;
|
|
|
|
|
2012-07-05 03:18:39 +07:00
|
|
|
mutex_lock(&dev->struct_mutex);
|
2009-09-15 04:48:45 +07:00
|
|
|
|
2010-09-30 22:53:18 +07:00
|
|
|
i915_gem_reset(dev);
|
2010-09-19 18:31:36 +07:00
|
|
|
|
2013-05-28 16:38:44 +07:00
|
|
|
simulated = dev_priv->gpu_error.stop_rings != 0;
|
|
|
|
|
|
|
|
if (!simulated && get_seconds() - dev_priv->gpu_error.last_reset < 5) {
|
2010-10-01 20:57:56 +07:00
|
|
|
DRM_ERROR("GPU hanging too fast, declaring wedged!\n");
|
2013-05-28 16:38:44 +07:00
|
|
|
ret = -ENODEV;
|
|
|
|
} else {
|
2012-04-27 20:17:44 +07:00
|
|
|
ret = intel_gpu_reset(dev);
|
2012-04-27 20:17:42 +07:00
|
|
|
|
2013-05-28 16:38:44 +07:00
|
|
|
/* Also reset the gpu hangman. */
|
|
|
|
if (simulated) {
|
|
|
|
DRM_INFO("Simulated gpu hang, resetting stop_rings\n");
|
|
|
|
dev_priv->gpu_error.stop_rings = 0;
|
|
|
|
if (ret == -ENODEV) {
|
|
|
|
DRM_ERROR("Reset not implemented, but ignoring "
|
|
|
|
"error for simulated gpu hangs\n");
|
|
|
|
ret = 0;
|
|
|
|
}
|
|
|
|
} else
|
|
|
|
dev_priv->gpu_error.last_reset = get_seconds();
|
|
|
|
}
|
2010-09-11 17:17:19 +07:00
|
|
|
if (ret) {
|
2010-09-19 18:38:26 +07:00
|
|
|
DRM_ERROR("Failed to reset chip.\n");
|
2010-05-17 20:23:52 +07:00
|
|
|
mutex_unlock(&dev->struct_mutex);
|
2010-09-19 18:38:26 +07:00
|
|
|
return ret;
|
2009-09-15 04:48:45 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Ok, now get things going again... */
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Everything depends on having the GTT running, so we need to start
|
|
|
|
* there. Fortunately we don't need to do this unless we reset the
|
|
|
|
* chip at a PCI level.
|
|
|
|
*
|
|
|
|
* Next we need to restore the context, but we don't use those
|
|
|
|
* yet either...
|
|
|
|
*
|
|
|
|
* Ring buffer needs to be re-initialized in the KMS case, or if X
|
|
|
|
* was running at the time of the reset (i.e. we weren't VT
|
|
|
|
* switched away).
|
|
|
|
*/
|
|
|
|
if (drm_core_check_feature(dev, DRIVER_MODESET) ||
|
2013-07-09 21:51:37 +07:00
|
|
|
!dev_priv->ums.mm_suspended) {
|
2012-05-11 20:29:30 +07:00
|
|
|
struct intel_ring_buffer *ring;
|
|
|
|
int i;
|
|
|
|
|
2013-07-09 21:51:37 +07:00
|
|
|
dev_priv->ums.mm_suspended = 0;
|
2010-11-18 08:31:13 +07:00
|
|
|
|
2012-02-02 15:58:12 +07:00
|
|
|
i915_gem_init_swizzling(dev);
|
|
|
|
|
2012-05-11 20:29:30 +07:00
|
|
|
for_each_ring(ring, dev_priv, i)
|
|
|
|
ring->init(ring);
|
2010-11-18 08:31:13 +07:00
|
|
|
|
drm/i915: preliminary context support
Very basic code for context setup/destruction in the driver.
Adds the file i915_gem_context.c This file implements HW context
support. On gen5+ a HW context consists of an opaque GPU object which is
referenced at times of context saves and restores. With RC6 enabled,
the context is also referenced as the GPU enters and exists from RC6
(GPU has it's own internal power context, except on gen5). Though
something like a context does exist for the media ring, the code only
supports contexts for the render ring.
In software, there is a distinction between contexts created by the
user, and the default HW context. The default HW context is used by GPU
clients that do not request setup of their own hardware context. The
default context's state is never restored to help prevent programming
errors. This would happen if a client ran and piggy-backed off another
clients GPU state. The default context only exists to give the GPU some
offset to load as the current to invoke a save of the context we
actually care about. In fact, the code could likely be constructed,
albeit in a more complicated fashion, to never use the default context,
though that limits the driver's ability to swap out, and/or destroy
other contexts.
All other contexts are created as a request by the GPU client. These
contexts store GPU state, and thus allow GPU clients to not re-emit
state (and potentially query certain state) at any time. The kernel
driver makes certain that the appropriate commands are inserted.
There are 4 entry points into the contexts, init, fini, open, close.
The names are self-explanatory except that init can be called during
reset, and also during pm thaw/resume. As we expect our context to be
preserved across these events, we do not reinitialize in this case.
As Adam Jackson pointed out, The cutoff of 1MB where a HW context is
considered too big is arbitrary. The reason for this is even though
context sizes are increasing with every generation, they have yet to
eclipse even 32k. If we somehow read back way more than that, it
probably means BIOS has done something strange, or we're running on a
platform that wasn't designed for this.
v2: rename load/unload to init/fini (daniel)
remove ILK support for get_size() (indirectly daniel)
add HAS_HW_CONTEXTS macro to clarify supported platforms (daniel)
added comments (Ben)
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2012-06-05 04:42:42 +07:00
|
|
|
i915_gem_context_init(dev);
|
2013-04-09 08:43:56 +07:00
|
|
|
if (dev_priv->mm.aliasing_ppgtt) {
|
|
|
|
ret = dev_priv->mm.aliasing_ppgtt->enable(dev);
|
|
|
|
if (ret)
|
|
|
|
i915_gem_cleanup_aliasing_ppgtt(dev);
|
|
|
|
}
|
2012-02-10 02:53:27 +07:00
|
|
|
|
2012-06-19 23:40:00 +07:00
|
|
|
/*
|
|
|
|
* It would make sense to re-init all the other hw state, at
|
|
|
|
* least the rps/rc6/emon init done within modeset_init_hw. For
|
|
|
|
* some unknown reason, this blows up my ilk, so don't.
|
|
|
|
*/
|
2012-04-10 20:50:11 +07:00
|
|
|
|
2012-06-19 23:40:00 +07:00
|
|
|
mutex_unlock(&dev->struct_mutex);
|
2012-04-10 20:50:11 +07:00
|
|
|
|
2009-09-15 04:48:45 +07:00
|
|
|
drm_irq_uninstall(dev);
|
|
|
|
drm_irq_install(dev);
|
2012-12-11 20:05:07 +07:00
|
|
|
intel_hpd_init(dev);
|
2012-04-27 20:17:41 +07:00
|
|
|
} else {
|
|
|
|
mutex_unlock(&dev->struct_mutex);
|
2009-09-15 04:48:45 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2012-12-22 06:09:25 +07:00
|
|
|
static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
|
2009-01-05 04:55:33 +07:00
|
|
|
{
|
2012-06-25 20:58:49 +07:00
|
|
|
struct intel_device_info *intel_info =
|
|
|
|
(struct intel_device_info *) ent->driver_data;
|
|
|
|
|
2011-02-02 02:43:02 +07:00
|
|
|
/* Only bind to function 0 of the device. Early generations
|
|
|
|
* used function 1 as a placeholder for multi-head. This causes
|
|
|
|
* us confusion instead, especially on the systems where both
|
|
|
|
* functions have the same PCI-ID!
|
|
|
|
*/
|
|
|
|
if (PCI_FUNC(pdev->devfn))
|
|
|
|
return -ENODEV;
|
|
|
|
|
2012-06-25 20:58:49 +07:00
|
|
|
/* We've managed to ship a kms-enabled ddx that shipped with an XvMC
|
|
|
|
* implementation for gen3 (and only gen3) that used legacy drm maps
|
|
|
|
* (gasp!) to share buffers between X and the client. Hence we need to
|
|
|
|
* keep around the fake agp stuff for gen3, even when kms is enabled. */
|
|
|
|
if (intel_info->gen != 3) {
|
|
|
|
driver.driver_features &=
|
|
|
|
~(DRIVER_USE_AGP | DRIVER_REQUIRE_AGP);
|
|
|
|
} else if (!intel_agp_enabled) {
|
|
|
|
DRM_ERROR("drm/i915 can't work without intel_agp module!\n");
|
|
|
|
return -ENODEV;
|
|
|
|
}
|
|
|
|
|
2010-05-28 02:40:25 +07:00
|
|
|
return drm_get_pci_dev(pdev, ent, &driver);
|
2009-01-05 04:55:33 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
i915_pci_remove(struct pci_dev *pdev)
|
|
|
|
{
|
|
|
|
struct drm_device *dev = pci_get_drvdata(pdev);
|
|
|
|
|
|
|
|
drm_put_dev(dev);
|
|
|
|
}
|
|
|
|
|
2010-02-08 03:48:24 +07:00
|
|
|
static int i915_pm_suspend(struct device *dev)
|
2009-01-05 04:55:33 +07:00
|
|
|
{
|
2010-02-08 03:48:24 +07:00
|
|
|
struct pci_dev *pdev = to_pci_dev(dev);
|
|
|
|
struct drm_device *drm_dev = pci_get_drvdata(pdev);
|
|
|
|
int error;
|
2009-01-05 04:55:33 +07:00
|
|
|
|
2010-02-08 03:48:24 +07:00
|
|
|
if (!drm_dev || !drm_dev->dev_private) {
|
|
|
|
dev_err(dev, "DRM not initialized, aborting suspend.\n");
|
|
|
|
return -ENODEV;
|
|
|
|
}
|
2009-01-05 04:55:33 +07:00
|
|
|
|
2010-12-07 06:20:40 +07:00
|
|
|
if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
|
|
|
|
return 0;
|
|
|
|
|
2010-02-08 03:48:24 +07:00
|
|
|
error = i915_drm_freeze(drm_dev);
|
|
|
|
if (error)
|
|
|
|
return error;
|
2009-01-05 04:55:33 +07:00
|
|
|
|
2010-02-08 03:48:24 +07:00
|
|
|
pci_disable_device(pdev);
|
|
|
|
pci_set_power_state(pdev, PCI_D3hot);
|
2009-12-16 12:36:10 +07:00
|
|
|
|
2010-02-08 03:48:24 +07:00
|
|
|
return 0;
|
2009-12-16 12:36:10 +07:00
|
|
|
}
|
|
|
|
|
2010-02-08 03:48:24 +07:00
|
|
|
static int i915_pm_resume(struct device *dev)
|
2009-12-16 12:36:10 +07:00
|
|
|
{
|
2010-02-08 03:48:24 +07:00
|
|
|
struct pci_dev *pdev = to_pci_dev(dev);
|
|
|
|
struct drm_device *drm_dev = pci_get_drvdata(pdev);
|
|
|
|
|
|
|
|
return i915_resume(drm_dev);
|
2009-12-16 12:36:10 +07:00
|
|
|
}
|
|
|
|
|
2010-02-08 03:48:24 +07:00
|
|
|
static int i915_pm_freeze(struct device *dev)
|
2009-12-16 12:36:10 +07:00
|
|
|
{
|
2010-02-08 03:48:24 +07:00
|
|
|
struct pci_dev *pdev = to_pci_dev(dev);
|
|
|
|
struct drm_device *drm_dev = pci_get_drvdata(pdev);
|
|
|
|
|
|
|
|
if (!drm_dev || !drm_dev->dev_private) {
|
|
|
|
dev_err(dev, "DRM not initialized, aborting suspend.\n");
|
|
|
|
return -ENODEV;
|
|
|
|
}
|
|
|
|
|
|
|
|
return i915_drm_freeze(drm_dev);
|
2009-12-16 12:36:10 +07:00
|
|
|
}
|
|
|
|
|
2010-02-08 03:48:24 +07:00
|
|
|
static int i915_pm_thaw(struct device *dev)
|
2009-12-16 12:36:10 +07:00
|
|
|
{
|
2010-02-08 03:48:24 +07:00
|
|
|
struct pci_dev *pdev = to_pci_dev(dev);
|
|
|
|
struct drm_device *drm_dev = pci_get_drvdata(pdev);
|
|
|
|
|
|
|
|
return i915_drm_thaw(drm_dev);
|
2009-12-16 12:36:10 +07:00
|
|
|
}
|
|
|
|
|
2010-02-08 03:48:24 +07:00
|
|
|
static int i915_pm_poweroff(struct device *dev)
|
2009-12-16 12:36:10 +07:00
|
|
|
{
|
2010-02-08 03:48:24 +07:00
|
|
|
struct pci_dev *pdev = to_pci_dev(dev);
|
|
|
|
struct drm_device *drm_dev = pci_get_drvdata(pdev);
|
|
|
|
|
2010-02-19 05:06:27 +07:00
|
|
|
return i915_drm_freeze(drm_dev);
|
2009-12-16 12:36:10 +07:00
|
|
|
}
|
|
|
|
|
2010-06-06 21:40:20 +07:00
|
|
|
static const struct dev_pm_ops i915_pm_ops = {
|
2011-08-17 02:34:10 +07:00
|
|
|
.suspend = i915_pm_suspend,
|
|
|
|
.resume = i915_pm_resume,
|
|
|
|
.freeze = i915_pm_freeze,
|
|
|
|
.thaw = i915_pm_thaw,
|
|
|
|
.poweroff = i915_pm_poweroff,
|
|
|
|
.restore = i915_pm_resume,
|
2009-12-16 12:36:10 +07:00
|
|
|
};
|
|
|
|
|
2012-05-17 18:27:22 +07:00
|
|
|
static const struct vm_operations_struct i915_gem_vm_ops = {
|
2008-11-13 01:03:55 +07:00
|
|
|
.fault = i915_gem_fault,
|
2009-02-12 05:01:46 +07:00
|
|
|
.open = drm_gem_vm_open,
|
|
|
|
.close = drm_gem_vm_close,
|
2008-11-13 01:03:55 +07:00
|
|
|
};
|
|
|
|
|
2011-10-31 21:28:57 +07:00
|
|
|
static const struct file_operations i915_driver_fops = {
|
|
|
|
.owner = THIS_MODULE,
|
|
|
|
.open = drm_open,
|
|
|
|
.release = drm_release,
|
|
|
|
.unlocked_ioctl = drm_ioctl,
|
|
|
|
.mmap = drm_gem_mmap,
|
|
|
|
.poll = drm_poll,
|
|
|
|
.fasync = drm_fasync,
|
|
|
|
.read = drm_read,
|
|
|
|
#ifdef CONFIG_COMPAT
|
|
|
|
.compat_ioctl = i915_compat_ioctl,
|
|
|
|
#endif
|
|
|
|
.llseek = noop_llseek,
|
|
|
|
};
|
|
|
|
|
2005-04-17 05:20:36 +07:00
|
|
|
static struct drm_driver driver = {
|
2011-08-26 00:55:54 +07:00
|
|
|
/* Don't use MTRRs here; the Xserver or userspace app should
|
|
|
|
* deal with them for Intel hardware.
|
2005-11-11 19:30:27 +07:00
|
|
|
*/
|
2008-07-31 02:06:12 +07:00
|
|
|
.driver_features =
|
|
|
|
DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | /* DRIVER_USE_MTRR |*/
|
2012-05-10 20:25:09 +07:00
|
|
|
DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME,
|
2005-11-10 18:16:34 +07:00
|
|
|
.load = i915_driver_load,
|
2007-11-22 11:14:14 +07:00
|
|
|
.unload = i915_driver_unload,
|
2008-07-31 02:06:12 +07:00
|
|
|
.open = i915_driver_open,
|
2005-11-10 18:16:34 +07:00
|
|
|
.lastclose = i915_driver_lastclose,
|
|
|
|
.preclose = i915_driver_preclose,
|
2008-07-31 02:06:12 +07:00
|
|
|
.postclose = i915_driver_postclose,
|
2010-01-09 06:45:33 +07:00
|
|
|
|
|
|
|
/* Used in place of i915_pm_ops for non-DRIVER_MODESET */
|
|
|
|
.suspend = i915_suspend,
|
|
|
|
.resume = i915_resume,
|
|
|
|
|
2005-07-10 14:31:26 +07:00
|
|
|
.device_is_agp = i915_driver_device_is_agp,
|
2008-11-28 11:22:24 +07:00
|
|
|
.master_create = i915_master_create,
|
|
|
|
.master_destroy = i915_master_destroy,
|
2009-02-18 08:08:49 +07:00
|
|
|
#if defined(CONFIG_DEBUG_FS)
|
2009-07-02 09:26:52 +07:00
|
|
|
.debugfs_init = i915_debugfs_init,
|
|
|
|
.debugfs_cleanup = i915_debugfs_cleanup,
|
2009-02-18 08:08:49 +07:00
|
|
|
#endif
|
2008-07-31 02:06:12 +07:00
|
|
|
.gem_init_object = i915_gem_init_object,
|
|
|
|
.gem_free_object = i915_gem_free_object,
|
2008-11-13 01:03:55 +07:00
|
|
|
.gem_vm_ops = &i915_gem_vm_ops,
|
2012-05-10 20:25:09 +07:00
|
|
|
|
|
|
|
.prime_handle_to_fd = drm_gem_prime_handle_to_fd,
|
|
|
|
.prime_fd_to_handle = drm_gem_prime_fd_to_handle,
|
|
|
|
.gem_prime_export = i915_gem_prime_export,
|
|
|
|
.gem_prime_import = i915_gem_prime_import,
|
|
|
|
|
2011-02-07 09:16:14 +07:00
|
|
|
.dumb_create = i915_gem_dumb_create,
|
|
|
|
.dumb_map_offset = i915_gem_mmap_gtt,
|
|
|
|
.dumb_destroy = i915_gem_dumb_destroy,
|
2005-04-17 05:20:36 +07:00
|
|
|
.ioctls = i915_ioctls,
|
2011-10-31 21:28:57 +07:00
|
|
|
.fops = &i915_driver_fops,
|
2005-11-10 18:16:34 +07:00
|
|
|
.name = DRIVER_NAME,
|
|
|
|
.desc = DRIVER_DESC,
|
|
|
|
.date = DRIVER_DATE,
|
|
|
|
.major = DRIVER_MAJOR,
|
|
|
|
.minor = DRIVER_MINOR,
|
|
|
|
.patchlevel = DRIVER_PATCHLEVEL,
|
2005-04-17 05:20:36 +07:00
|
|
|
};
|
|
|
|
|
2010-12-15 00:16:38 +07:00
|
|
|
static struct pci_driver i915_pci_driver = {
|
|
|
|
.name = DRIVER_NAME,
|
|
|
|
.id_table = pciidlist,
|
|
|
|
.probe = i915_pci_probe,
|
|
|
|
.remove = i915_pci_remove,
|
|
|
|
.driver.pm = &i915_pm_ops,
|
|
|
|
};
|
|
|
|
|
2005-04-17 05:20:36 +07:00
|
|
|
static int __init i915_init(void)
|
|
|
|
{
|
|
|
|
driver.num_ioctls = i915_max_ioctl;
|
DRM: i915: add mode setting support
This commit adds i915 driver support for the DRM mode setting APIs.
Currently, VGA, LVDS, SDVO DVI & VGA, TV and DVO LVDS outputs are
supported. HDMI, DisplayPort and additional SDVO output support will
follow.
Support for the mode setting code is controlled by the new 'modeset'
module option. A new config option, CONFIG_DRM_I915_KMS controls the
default behavior, and whether a PCI ID list is built into the module for
use by user level module utilities.
Note that if mode setting is enabled, user level drivers that access
display registers directly or that don't use the kernel graphics memory
manager will likely corrupt kernel graphics memory, disrupt output
configuration (possibly leading to hangs and/or blank displays), and
prevent panic/oops messages from appearing. So use caution when
enabling this code; be sure your user level code supports the new
interfaces.
A new SysRq key, 'g', provides emergency support for switching back to
the kernel's framebuffer console; which is useful for testing.
Co-authors: Dave Airlie <airlied@linux.ie>, Hong Liu <hong.liu@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2008-11-08 05:24:08 +07:00
|
|
|
|
|
|
|
/*
|
|
|
|
* If CONFIG_DRM_I915_KMS is set, default to KMS unless
|
|
|
|
* explicitly disabled with the module pararmeter.
|
|
|
|
*
|
|
|
|
* Otherwise, just follow the parameter (defaulting to off).
|
|
|
|
*
|
|
|
|
* Allow optional vga_text_mode_force boot option to override
|
|
|
|
* the default behavior.
|
|
|
|
*/
|
|
|
|
#if defined(CONFIG_DRM_I915_KMS)
|
|
|
|
if (i915_modeset != 0)
|
|
|
|
driver.driver_features |= DRIVER_MODESET;
|
|
|
|
#endif
|
|
|
|
if (i915_modeset == 1)
|
|
|
|
driver.driver_features |= DRIVER_MODESET;
|
|
|
|
|
|
|
|
#ifdef CONFIG_VGA_CONSOLE
|
|
|
|
if (vgacon_text_force() && i915_modeset == -1)
|
|
|
|
driver.driver_features &= ~DRIVER_MODESET;
|
|
|
|
#endif
|
|
|
|
|
2011-01-23 17:45:14 +07:00
|
|
|
if (!(driver.driver_features & DRIVER_MODESET))
|
|
|
|
driver.get_vblank_timestamp = NULL;
|
|
|
|
|
2010-12-15 00:16:38 +07:00
|
|
|
return drm_pci_init(&driver, &i915_pci_driver);
|
2005-04-17 05:20:36 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
static void __exit i915_exit(void)
|
|
|
|
{
|
2010-12-15 00:16:38 +07:00
|
|
|
drm_pci_exit(&driver, &i915_pci_driver);
|
2005-04-17 05:20:36 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
module_init(i915_init);
|
|
|
|
module_exit(i915_exit);
|
|
|
|
|
2005-09-25 11:28:13 +07:00
|
|
|
MODULE_AUTHOR(DRIVER_AUTHOR);
|
|
|
|
MODULE_DESCRIPTION(DRIVER_DESC);
|
2005-04-17 05:20:36 +07:00
|
|
|
MODULE_LICENSE("GPL and additional rights");
|