2006-06-18 05:52:48 +07:00
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/*
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2008-10-08 02:00:18 +07:00
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* MPC83xx/85xx/86xx PCI/PCIE support routing.
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2006-06-18 05:52:48 +07:00
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*
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2008-10-08 02:00:18 +07:00
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* Copyright 2007,2008 Freescale Semiconductor, Inc
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2006-06-18 05:52:48 +07:00
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*
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2007-07-10 17:46:35 +07:00
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* Initial author: Xianghua Xiao <x.xiao@freescale.com>
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* Recode: ZHANG WEI <wei.zhang@freescale.com>
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* Rewrite the routing for Frescale PCI and PCI Express
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* Roy Zang <tie-fei.zang@freescale.com>
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2006-06-18 05:52:48 +07:00
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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2007-07-10 17:46:35 +07:00
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#include <linux/kernel.h>
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2006-06-18 05:52:48 +07:00
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#include <linux/pci.h>
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2007-07-10 17:46:35 +07:00
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#include <linux/delay.h>
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#include <linux/string.h>
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#include <linux/init.h>
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#include <linux/bootmem.h>
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2006-06-18 05:52:48 +07:00
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#include <asm/io.h>
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#include <asm/prom.h>
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#include <asm/pci-bridge.h>
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2007-07-10 17:46:35 +07:00
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#include <asm/machdep.h>
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2006-06-18 05:52:48 +07:00
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#include <sysdev/fsl_soc.h>
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2007-07-10 17:44:34 +07:00
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#include <sysdev/fsl_pci.h>
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2006-06-18 05:52:48 +07:00
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2008-06-27 00:07:57 +07:00
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#if defined(CONFIG_PPC_85xx) || defined(CONFIG_PPC_86xx)
|
powerpc/fsl-pci: Better ATMU setup for 85xx/86xx
The code that sets up the outbound ATMU windows, which is used to map CPU
physical addresses into PCI bus addresses where BARs will be mapped, didn't
work so well.
For one, it leaked the ioremap() of the ATMU registers. Another small bug
was the high 20 bits of the PCI bus address were left as zero. It's legal
for prefetchable memory regions to be above 32 bits, so the high 20 bits
might not be zero.
Mainly, it couldn't handle ranges that were not a power of two in size or
were not naturally aligned. The ATMU windows have these requirements (size
& alignment), but the code didn't bother to check if the ranges it was
programming met them. If they didn't, the windows would silently be
programmed incorrectly.
This new code can handle ranges which are not power of two sized nor
naturally aligned. It simply splits the ranges into multiple valid ATMU
windows. As there are only four windows, pooly aligned or sized ranges
(which didn't even work before) may run out of windows. In this case an
error is printed and an effort is made to disable the unmapped resources.
An improvement that could be made would be to make use of the default
outbound window. Iff hose->pci_mem_offset is zero, then it's possible that
some or all of the ranges might not need an outbound window and could just
use the default window.
The default ATMU window can support a pci_mem_offset less than zero too,
but pci_mem_offset is unsigned. One could say the abilities allowed a
powerpc pci_controller is neither subset nor a superset of the abilities of
a Freescale PCIe controller. Thankfully, the most useful bits are in the
intersection of the two abilities.
Signed-off-by: Trent Piepho <tpiepho@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-01-07 11:37:53 +07:00
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static int __init setup_one_atmu(struct ccsr_pci __iomem *pci,
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unsigned int index, const struct resource *res,
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resource_size_t offset)
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{
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resource_size_t pci_addr = res->start - offset;
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resource_size_t phys_addr = res->start;
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resource_size_t size = res->end - res->start + 1;
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u32 flags = 0x80044000; /* enable & mem R/W */
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unsigned int i;
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pr_debug("PCI MEM resource start 0x%016llx, size 0x%016llx.\n",
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(u64)res->start, (u64)size);
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for (i = 0; size > 0; i++) {
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unsigned int bits = min(__ilog2(size),
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__ffs(pci_addr | phys_addr));
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if (index + i >= 5)
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return -1;
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out_be32(&pci->pow[index + i].potar, pci_addr >> 12);
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out_be32(&pci->pow[index + i].potear, (u64)pci_addr >> 44);
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out_be32(&pci->pow[index + i].powbar, phys_addr >> 12);
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out_be32(&pci->pow[index + i].powar, flags | (bits - 1));
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pci_addr += (resource_size_t)1U << bits;
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phys_addr += (resource_size_t)1U << bits;
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size -= (resource_size_t)1U << bits;
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}
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return i;
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}
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|
2007-07-10 17:46:35 +07:00
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/* atmu setup for fsl pci/pcie controller */
|
2008-12-29 23:40:32 +07:00
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static void __init setup_pci_atmu(struct pci_controller *hose,
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struct resource *rsrc)
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2006-06-18 05:52:48 +07:00
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|
{
|
2007-07-10 17:46:35 +07:00
|
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|
struct ccsr_pci __iomem *pci;
|
powerpc/fsl-pci: Better ATMU setup for 85xx/86xx
The code that sets up the outbound ATMU windows, which is used to map CPU
physical addresses into PCI bus addresses where BARs will be mapped, didn't
work so well.
For one, it leaked the ioremap() of the ATMU registers. Another small bug
was the high 20 bits of the PCI bus address were left as zero. It's legal
for prefetchable memory regions to be above 32 bits, so the high 20 bits
might not be zero.
Mainly, it couldn't handle ranges that were not a power of two in size or
were not naturally aligned. The ATMU windows have these requirements (size
& alignment), but the code didn't bother to check if the ranges it was
programming met them. If they didn't, the windows would silently be
programmed incorrectly.
This new code can handle ranges which are not power of two sized nor
naturally aligned. It simply splits the ranges into multiple valid ATMU
windows. As there are only four windows, pooly aligned or sized ranges
(which didn't even work before) may run out of windows. In this case an
error is printed and an effort is made to disable the unmapped resources.
An improvement that could be made would be to make use of the default
outbound window. Iff hose->pci_mem_offset is zero, then it's possible that
some or all of the ranges might not need an outbound window and could just
use the default window.
The default ATMU window can support a pci_mem_offset less than zero too,
but pci_mem_offset is unsigned. One could say the abilities allowed a
powerpc pci_controller is neither subset nor a superset of the abilities of
a Freescale PCIe controller. Thankfully, the most useful bits are in the
intersection of the two abilities.
Signed-off-by: Trent Piepho <tpiepho@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-01-07 11:37:53 +07:00
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int i, j, n;
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2006-06-18 05:52:48 +07:00
|
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|
2008-01-15 06:02:19 +07:00
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pr_debug("PCI memory map start 0x%016llx, size 0x%016llx\n",
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(u64)rsrc->start, (u64)rsrc->end - (u64)rsrc->start + 1);
|
2007-07-10 17:46:35 +07:00
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|
pci = ioremap(rsrc->start, rsrc->end - rsrc->start + 1);
|
powerpc/fsl-pci: Better ATMU setup for 85xx/86xx
The code that sets up the outbound ATMU windows, which is used to map CPU
physical addresses into PCI bus addresses where BARs will be mapped, didn't
work so well.
For one, it leaked the ioremap() of the ATMU registers. Another small bug
was the high 20 bits of the PCI bus address were left as zero. It's legal
for prefetchable memory regions to be above 32 bits, so the high 20 bits
might not be zero.
Mainly, it couldn't handle ranges that were not a power of two in size or
were not naturally aligned. The ATMU windows have these requirements (size
& alignment), but the code didn't bother to check if the ranges it was
programming met them. If they didn't, the windows would silently be
programmed incorrectly.
This new code can handle ranges which are not power of two sized nor
naturally aligned. It simply splits the ranges into multiple valid ATMU
windows. As there are only four windows, pooly aligned or sized ranges
(which didn't even work before) may run out of windows. In this case an
error is printed and an effort is made to disable the unmapped resources.
An improvement that could be made would be to make use of the default
outbound window. Iff hose->pci_mem_offset is zero, then it's possible that
some or all of the ranges might not need an outbound window and could just
use the default window.
The default ATMU window can support a pci_mem_offset less than zero too,
but pci_mem_offset is unsigned. One could say the abilities allowed a
powerpc pci_controller is neither subset nor a superset of the abilities of
a Freescale PCIe controller. Thankfully, the most useful bits are in the
intersection of the two abilities.
Signed-off-by: Trent Piepho <tpiepho@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-01-07 11:37:53 +07:00
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if (!pci) {
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dev_err(hose->parent, "Unable to map ATMU registers\n");
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return;
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}
|
2007-07-10 17:46:35 +07:00
|
|
|
|
powerpc/fsl-pci: Better ATMU setup for 85xx/86xx
The code that sets up the outbound ATMU windows, which is used to map CPU
physical addresses into PCI bus addresses where BARs will be mapped, didn't
work so well.
For one, it leaked the ioremap() of the ATMU registers. Another small bug
was the high 20 bits of the PCI bus address were left as zero. It's legal
for prefetchable memory regions to be above 32 bits, so the high 20 bits
might not be zero.
Mainly, it couldn't handle ranges that were not a power of two in size or
were not naturally aligned. The ATMU windows have these requirements (size
& alignment), but the code didn't bother to check if the ranges it was
programming met them. If they didn't, the windows would silently be
programmed incorrectly.
This new code can handle ranges which are not power of two sized nor
naturally aligned. It simply splits the ranges into multiple valid ATMU
windows. As there are only four windows, pooly aligned or sized ranges
(which didn't even work before) may run out of windows. In this case an
error is printed and an effort is made to disable the unmapped resources.
An improvement that could be made would be to make use of the default
outbound window. Iff hose->pci_mem_offset is zero, then it's possible that
some or all of the ranges might not need an outbound window and could just
use the default window.
The default ATMU window can support a pci_mem_offset less than zero too,
but pci_mem_offset is unsigned. One could say the abilities allowed a
powerpc pci_controller is neither subset nor a superset of the abilities of
a Freescale PCIe controller. Thankfully, the most useful bits are in the
intersection of the two abilities.
Signed-off-by: Trent Piepho <tpiepho@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-01-07 11:37:53 +07:00
|
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|
/* Disable all windows (except powar0 since it's ignored) */
|
2007-07-10 17:46:35 +07:00
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|
for(i = 1; i < 5; i++)
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out_be32(&pci->pow[i].powar, 0);
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for(i = 0; i < 3; i++)
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out_be32(&pci->piw[i].piwar, 0);
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/* Setup outbound MEM window */
|
powerpc/fsl-pci: Better ATMU setup for 85xx/86xx
The code that sets up the outbound ATMU windows, which is used to map CPU
physical addresses into PCI bus addresses where BARs will be mapped, didn't
work so well.
For one, it leaked the ioremap() of the ATMU registers. Another small bug
was the high 20 bits of the PCI bus address were left as zero. It's legal
for prefetchable memory regions to be above 32 bits, so the high 20 bits
might not be zero.
Mainly, it couldn't handle ranges that were not a power of two in size or
were not naturally aligned. The ATMU windows have these requirements (size
& alignment), but the code didn't bother to check if the ranges it was
programming met them. If they didn't, the windows would silently be
programmed incorrectly.
This new code can handle ranges which are not power of two sized nor
naturally aligned. It simply splits the ranges into multiple valid ATMU
windows. As there are only four windows, pooly aligned or sized ranges
(which didn't even work before) may run out of windows. In this case an
error is printed and an effort is made to disable the unmapped resources.
An improvement that could be made would be to make use of the default
outbound window. Iff hose->pci_mem_offset is zero, then it's possible that
some or all of the ranges might not need an outbound window and could just
use the default window.
The default ATMU window can support a pci_mem_offset less than zero too,
but pci_mem_offset is unsigned. One could say the abilities allowed a
powerpc pci_controller is neither subset nor a superset of the abilities of
a Freescale PCIe controller. Thankfully, the most useful bits are in the
intersection of the two abilities.
Signed-off-by: Trent Piepho <tpiepho@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-01-07 11:37:53 +07:00
|
|
|
for(i = 0, j = 1; i < 3; i++) {
|
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|
|
|
if (!(hose->mem_resources[i].flags & IORESOURCE_MEM))
|
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continue;
|
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n = setup_one_atmu(pci, j, &hose->mem_resources[i],
|
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|
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hose->pci_mem_offset);
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if (n < 0 || j >= 5) {
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pr_err("Ran out of outbound PCI ATMUs for resource %d!\n", i);
|
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|
|
hose->mem_resources[i].flags |= IORESOURCE_DISABLED;
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|
|
} else
|
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|
j += n;
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|
}
|
2007-07-10 17:46:35 +07:00
|
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|
|
|
|
|
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/* Setup outbound IO window */
|
powerpc/fsl-pci: Better ATMU setup for 85xx/86xx
The code that sets up the outbound ATMU windows, which is used to map CPU
physical addresses into PCI bus addresses where BARs will be mapped, didn't
work so well.
For one, it leaked the ioremap() of the ATMU registers. Another small bug
was the high 20 bits of the PCI bus address were left as zero. It's legal
for prefetchable memory regions to be above 32 bits, so the high 20 bits
might not be zero.
Mainly, it couldn't handle ranges that were not a power of two in size or
were not naturally aligned. The ATMU windows have these requirements (size
& alignment), but the code didn't bother to check if the ranges it was
programming met them. If they didn't, the windows would silently be
programmed incorrectly.
This new code can handle ranges which are not power of two sized nor
naturally aligned. It simply splits the ranges into multiple valid ATMU
windows. As there are only four windows, pooly aligned or sized ranges
(which didn't even work before) may run out of windows. In this case an
error is printed and an effort is made to disable the unmapped resources.
An improvement that could be made would be to make use of the default
outbound window. Iff hose->pci_mem_offset is zero, then it's possible that
some or all of the ranges might not need an outbound window and could just
use the default window.
The default ATMU window can support a pci_mem_offset less than zero too,
but pci_mem_offset is unsigned. One could say the abilities allowed a
powerpc pci_controller is neither subset nor a superset of the abilities of
a Freescale PCIe controller. Thankfully, the most useful bits are in the
intersection of the two abilities.
Signed-off-by: Trent Piepho <tpiepho@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-01-07 11:37:53 +07:00
|
|
|
if (hose->io_resource.flags & IORESOURCE_IO) {
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|
|
|
|
if (j >= 5) {
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|
|
|
|
pr_err("Ran out of outbound PCI ATMUs for IO resource\n");
|
|
|
|
|
} else {
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|
|
|
|
pr_debug("PCI IO resource start 0x%016llx, size 0x%016llx, "
|
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|
|
|
"phy base 0x%016llx.\n",
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|
|
|
(u64)hose->io_resource.start,
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|
|
|
(u64)hose->io_resource.end - (u64)hose->io_resource.start + 1,
|
|
|
|
|
(u64)hose->io_base_phys);
|
|
|
|
|
out_be32(&pci->pow[j].potar, (hose->io_resource.start >> 12));
|
|
|
|
|
out_be32(&pci->pow[j].potear, 0);
|
|
|
|
|
out_be32(&pci->pow[j].powbar, (hose->io_base_phys >> 12));
|
|
|
|
|
/* Enable, IO R/W */
|
|
|
|
|
out_be32(&pci->pow[j].powar, 0x80088000
|
|
|
|
|
| (__ilog2(hose->io_resource.end
|
|
|
|
|
- hose->io_resource.start + 1) - 1));
|
|
|
|
|
}
|
2007-07-10 17:46:35 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Setup 2G inbound Memory Window @ 1 */
|
|
|
|
|
out_be32(&pci->piw[2].pitar, 0x00000000);
|
|
|
|
|
out_be32(&pci->piw[2].piwbar,0x00000000);
|
|
|
|
|
out_be32(&pci->piw[2].piwar, PIWAR_2G);
|
powerpc/fsl-pci: Better ATMU setup for 85xx/86xx
The code that sets up the outbound ATMU windows, which is used to map CPU
physical addresses into PCI bus addresses where BARs will be mapped, didn't
work so well.
For one, it leaked the ioremap() of the ATMU registers. Another small bug
was the high 20 bits of the PCI bus address were left as zero. It's legal
for prefetchable memory regions to be above 32 bits, so the high 20 bits
might not be zero.
Mainly, it couldn't handle ranges that were not a power of two in size or
were not naturally aligned. The ATMU windows have these requirements (size
& alignment), but the code didn't bother to check if the ranges it was
programming met them. If they didn't, the windows would silently be
programmed incorrectly.
This new code can handle ranges which are not power of two sized nor
naturally aligned. It simply splits the ranges into multiple valid ATMU
windows. As there are only four windows, pooly aligned or sized ranges
(which didn't even work before) may run out of windows. In this case an
error is printed and an effort is made to disable the unmapped resources.
An improvement that could be made would be to make use of the default
outbound window. Iff hose->pci_mem_offset is zero, then it's possible that
some or all of the ranges might not need an outbound window and could just
use the default window.
The default ATMU window can support a pci_mem_offset less than zero too,
but pci_mem_offset is unsigned. One could say the abilities allowed a
powerpc pci_controller is neither subset nor a superset of the abilities of
a Freescale PCIe controller. Thankfully, the most useful bits are in the
intersection of the two abilities.
Signed-off-by: Trent Piepho <tpiepho@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-01-07 11:37:53 +07:00
|
|
|
|
|
|
|
|
iounmap(pci);
|
2006-06-18 05:52:48 +07:00
|
|
|
}
|
|
|
|
|
|
2008-12-29 23:40:32 +07:00
|
|
|
static void __init setup_pci_cmd(struct pci_controller *hose)
|
2006-06-18 05:52:48 +07:00
|
|
|
{
|
|
|
|
|
u16 cmd;
|
2007-07-21 04:29:09 +07:00
|
|
|
int cap_x;
|
|
|
|
|
|
2006-06-18 05:52:48 +07:00
|
|
|
early_read_config_word(hose, 0, 0, PCI_COMMAND, &cmd);
|
|
|
|
|
cmd |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY
|
2007-07-10 17:46:35 +07:00
|
|
|
| PCI_COMMAND_IO;
|
2006-06-18 05:52:48 +07:00
|
|
|
early_write_config_word(hose, 0, 0, PCI_COMMAND, cmd);
|
2007-07-21 04:29:09 +07:00
|
|
|
|
|
|
|
|
cap_x = early_find_capability(hose, 0, 0, PCI_CAP_ID_PCIX);
|
|
|
|
|
if (cap_x) {
|
|
|
|
|
int pci_x_cmd = cap_x + PCI_X_CMD;
|
|
|
|
|
cmd = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
|
|
|
|
|
| PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
|
|
|
|
|
early_write_config_word(hose, 0, 0, pci_x_cmd, cmd);
|
|
|
|
|
} else {
|
|
|
|
|
early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80);
|
|
|
|
|
}
|
2006-06-28 12:37:45 +07:00
|
|
|
}
|
|
|
|
|
|
2008-05-23 20:41:02 +07:00
|
|
|
static void __init setup_pci_pcsrbar(struct pci_controller *hose)
|
2008-05-23 15:32:46 +07:00
|
|
|
{
|
2008-05-23 20:41:02 +07:00
|
|
|
#ifdef CONFIG_PCI_MSI
|
2008-05-23 15:32:46 +07:00
|
|
|
phys_addr_t immr_base;
|
|
|
|
|
|
|
|
|
|
immr_base = get_immrbase();
|
|
|
|
|
early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, immr_base);
|
|
|
|
|
#endif
|
2008-05-23 20:41:02 +07:00
|
|
|
}
|
2008-05-23 15:32:46 +07:00
|
|
|
|
2008-01-15 06:02:19 +07:00
|
|
|
static int fsl_pcie_bus_fixup;
|
2007-06-27 06:22:40 +07:00
|
|
|
|
2008-01-15 06:02:19 +07:00
|
|
|
static void __init quirk_fsl_pcie_header(struct pci_dev *dev)
|
|
|
|
|
{
|
2007-07-12 01:31:58 +07:00
|
|
|
/* if we aren't a PCIe don't bother */
|
|
|
|
|
if (!pci_find_capability(dev, PCI_CAP_ID_EXP))
|
|
|
|
|
return ;
|
|
|
|
|
|
2008-01-15 06:02:19 +07:00
|
|
|
dev->class = PCI_CLASS_BRIDGE_PCI << 8;
|
|
|
|
|
fsl_pcie_bus_fixup = 1;
|
|
|
|
|
return ;
|
2007-06-27 06:22:40 +07:00
|
|
|
}
|
|
|
|
|
|
2008-12-29 23:40:32 +07:00
|
|
|
static int __init fsl_pcie_check_link(struct pci_controller *hose)
|
2007-07-10 17:46:35 +07:00
|
|
|
{
|
2007-10-04 11:37:33 +07:00
|
|
|
u32 val;
|
|
|
|
|
early_read_config_dword(hose, 0, 0, PCIE_LTSSM, &val);
|
2007-07-10 17:46:35 +07:00
|
|
|
if (val < PCIE_LTSSM_L0)
|
|
|
|
|
return 1;
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
2007-06-27 06:22:40 +07:00
|
|
|
|
2007-07-20 03:29:53 +07:00
|
|
|
void fsl_pcibios_fixup_bus(struct pci_bus *bus)
|
|
|
|
|
{
|
|
|
|
|
struct pci_controller *hose = (struct pci_controller *) bus->sysdata;
|
|
|
|
|
int i;
|
|
|
|
|
|
2008-01-15 06:02:19 +07:00
|
|
|
if ((bus->parent == hose->bus) &&
|
|
|
|
|
((fsl_pcie_bus_fixup &&
|
|
|
|
|
early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) ||
|
|
|
|
|
(hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK)))
|
|
|
|
|
{
|
|
|
|
|
for (i = 0; i < 4; ++i) {
|
|
|
|
|
struct resource *res = bus->resource[i];
|
|
|
|
|
struct resource *par = bus->parent->resource[i];
|
|
|
|
|
if (res) {
|
|
|
|
|
res->start = 0;
|
|
|
|
|
res->end = 0;
|
|
|
|
|
res->flags = 0;
|
|
|
|
|
}
|
|
|
|
|
if (res && par) {
|
|
|
|
|
res->start = par->start;
|
|
|
|
|
res->end = par->end;
|
|
|
|
|
res->flags = par->flags;
|
|
|
|
|
}
|
2007-07-20 03:29:53 +07:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2007-07-10 17:46:35 +07:00
|
|
|
int __init fsl_add_bridge(struct device_node *dev, int is_primary)
|
2006-06-18 05:52:48 +07:00
|
|
|
{
|
|
|
|
|
int len;
|
|
|
|
|
struct pci_controller *hose;
|
|
|
|
|
struct resource rsrc;
|
2006-07-12 12:39:42 +07:00
|
|
|
const int *bus_range;
|
2006-06-18 05:52:48 +07:00
|
|
|
|
2007-07-10 17:46:35 +07:00
|
|
|
pr_debug("Adding PCI host bridge %s\n", dev->full_name);
|
2006-06-18 05:52:48 +07:00
|
|
|
|
|
|
|
|
/* Fetch host bridge registers address */
|
2007-07-10 17:46:35 +07:00
|
|
|
if (of_address_to_resource(dev, 0, &rsrc)) {
|
|
|
|
|
printk(KERN_WARNING "Can't get pci register base!");
|
|
|
|
|
return -ENOMEM;
|
|
|
|
|
}
|
2006-06-18 05:52:48 +07:00
|
|
|
|
|
|
|
|
/* Get bus range if any */
|
2007-04-03 19:26:41 +07:00
|
|
|
bus_range = of_get_property(dev, "bus-range", &len);
|
2006-06-18 05:52:48 +07:00
|
|
|
if (bus_range == NULL || len < 2 * sizeof(int))
|
|
|
|
|
printk(KERN_WARNING "Can't get bus-range for %s, assume"
|
2007-07-10 17:46:35 +07:00
|
|
|
" bus 0\n", dev->full_name);
|
2006-06-18 05:52:48 +07:00
|
|
|
|
2008-12-11 16:46:44 +07:00
|
|
|
ppc_pci_add_flags(PPC_PCI_REASSIGN_ALL_BUS);
|
2007-06-27 13:56:50 +07:00
|
|
|
hose = pcibios_alloc_controller(dev);
|
2006-06-18 05:52:48 +07:00
|
|
|
if (!hose)
|
|
|
|
|
return -ENOMEM;
|
2007-06-27 13:56:50 +07:00
|
|
|
|
2006-06-18 05:52:48 +07:00
|
|
|
hose->first_busno = bus_range ? bus_range[0] : 0x0;
|
2007-05-22 10:38:26 +07:00
|
|
|
hose->last_busno = bus_range ? bus_range[1] : 0xff;
|
2006-06-18 05:52:48 +07:00
|
|
|
|
2007-07-20 04:07:35 +07:00
|
|
|
setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4,
|
|
|
|
|
PPC_INDIRECT_TYPE_BIG_ENDIAN);
|
2007-07-10 17:46:35 +07:00
|
|
|
setup_pci_cmd(hose);
|
2006-06-18 05:52:48 +07:00
|
|
|
|
2007-07-10 17:46:35 +07:00
|
|
|
/* check PCI express link status */
|
2007-07-12 01:31:58 +07:00
|
|
|
if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
|
2007-07-25 12:29:53 +07:00
|
|
|
hose->indirect_type |= PPC_INDIRECT_TYPE_EXT_REG |
|
2007-07-12 01:31:58 +07:00
|
|
|
PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS;
|
2007-07-10 17:46:35 +07:00
|
|
|
if (fsl_pcie_check_link(hose))
|
2007-07-12 01:31:58 +07:00
|
|
|
hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
|
|
|
|
|
}
|
2006-06-18 05:52:48 +07:00
|
|
|
|
2007-11-20 08:47:55 +07:00
|
|
|
printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. "
|
2007-07-10 17:46:35 +07:00
|
|
|
"Firmware bus number: %d->%d\n",
|
|
|
|
|
(unsigned long long)rsrc.start, hose->first_busno,
|
|
|
|
|
hose->last_busno);
|
2006-06-18 05:52:48 +07:00
|
|
|
|
2007-07-10 17:46:35 +07:00
|
|
|
pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
|
2006-06-18 05:52:48 +07:00
|
|
|
hose, hose->cfg_addr, hose->cfg_data);
|
|
|
|
|
|
|
|
|
|
/* Interpret the "ranges" property */
|
|
|
|
|
/* This also maps the I/O region and sets isa_io/mem_base */
|
2007-07-10 17:46:35 +07:00
|
|
|
pci_process_bridge_OF_ranges(hose, dev, is_primary);
|
2006-06-18 05:52:48 +07:00
|
|
|
|
|
|
|
|
/* Setup PEX window registers */
|
2007-07-10 17:46:35 +07:00
|
|
|
setup_pci_atmu(hose, &rsrc);
|
2006-06-18 05:52:48 +07:00
|
|
|
|
2008-05-23 15:32:46 +07:00
|
|
|
/* Setup PEXCSRBAR */
|
|
|
|
|
setup_pci_pcsrbar(hose);
|
2006-06-18 05:52:48 +07:00
|
|
|
return 0;
|
|
|
|
|
}
|
2007-07-10 17:46:35 +07:00
|
|
|
|
2008-01-15 06:02:19 +07:00
|
|
|
DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8548E, quirk_fsl_pcie_header);
|
|
|
|
|
DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8548, quirk_fsl_pcie_header);
|
|
|
|
|
DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8543E, quirk_fsl_pcie_header);
|
|
|
|
|
DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8543, quirk_fsl_pcie_header);
|
|
|
|
|
DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8547E, quirk_fsl_pcie_header);
|
|
|
|
|
DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8545E, quirk_fsl_pcie_header);
|
|
|
|
|
DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8545, quirk_fsl_pcie_header);
|
|
|
|
|
DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8568E, quirk_fsl_pcie_header);
|
|
|
|
|
DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8568, quirk_fsl_pcie_header);
|
|
|
|
|
DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8567E, quirk_fsl_pcie_header);
|
|
|
|
|
DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8567, quirk_fsl_pcie_header);
|
|
|
|
|
DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8533E, quirk_fsl_pcie_header);
|
|
|
|
|
DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8533, quirk_fsl_pcie_header);
|
|
|
|
|
DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8544E, quirk_fsl_pcie_header);
|
|
|
|
|
DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8544, quirk_fsl_pcie_header);
|
|
|
|
|
DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8572E, quirk_fsl_pcie_header);
|
|
|
|
|
DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8572, quirk_fsl_pcie_header);
|
2008-07-02 13:36:15 +07:00
|
|
|
DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8536E, quirk_fsl_pcie_header);
|
|
|
|
|
DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8536, quirk_fsl_pcie_header);
|
2008-01-15 06:02:19 +07:00
|
|
|
DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8641, quirk_fsl_pcie_header);
|
|
|
|
|
DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8641D, quirk_fsl_pcie_header);
|
|
|
|
|
DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8610, quirk_fsl_pcie_header);
|
2008-06-27 00:07:57 +07:00
|
|
|
#endif /* CONFIG_PPC_85xx || CONFIG_PPC_86xx */
|
|
|
|
|
|
2008-10-08 04:13:18 +07:00
|
|
|
#if defined(CONFIG_PPC_83xx) || defined(CONFIG_PPC_MPC512x)
|
2008-06-27 00:07:57 +07:00
|
|
|
int __init mpc83xx_add_bridge(struct device_node *dev)
|
|
|
|
|
{
|
|
|
|
|
int len;
|
|
|
|
|
struct pci_controller *hose;
|
2008-10-08 02:00:18 +07:00
|
|
|
struct resource rsrc_reg;
|
|
|
|
|
struct resource rsrc_cfg;
|
2008-06-27 00:07:57 +07:00
|
|
|
const int *bus_range;
|
2008-10-08 02:00:18 +07:00
|
|
|
int primary;
|
2008-06-27 00:07:57 +07:00
|
|
|
|
|
|
|
|
pr_debug("Adding PCI host bridge %s\n", dev->full_name);
|
|
|
|
|
|
|
|
|
|
/* Fetch host bridge registers address */
|
2008-10-08 02:00:18 +07:00
|
|
|
if (of_address_to_resource(dev, 0, &rsrc_reg)) {
|
|
|
|
|
printk(KERN_WARNING "Can't get pci register base!\n");
|
|
|
|
|
return -ENOMEM;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
memset(&rsrc_cfg, 0, sizeof(rsrc_cfg));
|
|
|
|
|
|
|
|
|
|
if (of_address_to_resource(dev, 1, &rsrc_cfg)) {
|
|
|
|
|
printk(KERN_WARNING
|
|
|
|
|
"No pci config register base in dev tree, "
|
|
|
|
|
"using default\n");
|
|
|
|
|
/*
|
|
|
|
|
* MPC83xx supports up to two host controllers
|
|
|
|
|
* one at 0x8500 has config space registers at 0x8300
|
|
|
|
|
* one at 0x8600 has config space registers at 0x8380
|
|
|
|
|
*/
|
|
|
|
|
if ((rsrc_reg.start & 0xfffff) == 0x8500)
|
|
|
|
|
rsrc_cfg.start = (rsrc_reg.start & 0xfff00000) + 0x8300;
|
|
|
|
|
else if ((rsrc_reg.start & 0xfffff) == 0x8600)
|
|
|
|
|
rsrc_cfg.start = (rsrc_reg.start & 0xfff00000) + 0x8380;
|
|
|
|
|
}
|
|
|
|
|
/*
|
|
|
|
|
* Controller at offset 0x8500 is primary
|
|
|
|
|
*/
|
|
|
|
|
if ((rsrc_reg.start & 0xfffff) == 0x8500)
|
|
|
|
|
primary = 1;
|
|
|
|
|
else
|
|
|
|
|
primary = 0;
|
2008-06-27 00:07:57 +07:00
|
|
|
|
|
|
|
|
/* Get bus range if any */
|
|
|
|
|
bus_range = of_get_property(dev, "bus-range", &len);
|
|
|
|
|
if (bus_range == NULL || len < 2 * sizeof(int)) {
|
|
|
|
|
printk(KERN_WARNING "Can't get bus-range for %s, assume"
|
|
|
|
|
" bus 0\n", dev->full_name);
|
|
|
|
|
}
|
|
|
|
|
|
2008-12-11 16:46:44 +07:00
|
|
|
ppc_pci_add_flags(PPC_PCI_REASSIGN_ALL_BUS);
|
2008-06-27 00:07:57 +07:00
|
|
|
hose = pcibios_alloc_controller(dev);
|
|
|
|
|
if (!hose)
|
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
|
|
hose->first_busno = bus_range ? bus_range[0] : 0;
|
|
|
|
|
hose->last_busno = bus_range ? bus_range[1] : 0xff;
|
|
|
|
|
|
2008-10-08 02:00:18 +07:00
|
|
|
setup_indirect_pci(hose, rsrc_cfg.start, rsrc_cfg.start + 4, 0);
|
2008-06-27 00:07:57 +07:00
|
|
|
|
2008-10-08 04:13:18 +07:00
|
|
|
printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. "
|
2008-06-27 00:07:57 +07:00
|
|
|
"Firmware bus number: %d->%d\n",
|
2008-10-08 02:00:18 +07:00
|
|
|
(unsigned long long)rsrc_reg.start, hose->first_busno,
|
2008-06-27 00:07:57 +07:00
|
|
|
hose->last_busno);
|
|
|
|
|
|
|
|
|
|
pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
|
|
|
|
|
hose, hose->cfg_addr, hose->cfg_data);
|
|
|
|
|
|
|
|
|
|
/* Interpret the "ranges" property */
|
|
|
|
|
/* This also maps the I/O region and sets isa_io/mem_base */
|
|
|
|
|
pci_process_bridge_OF_ranges(hose, dev, primary);
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
#endif /* CONFIG_PPC_83xx */
|