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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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[POWERPC] FSL: Rework PCI/PCIe support for 85xx/86xx
The current PCI code for Freescale 85xx/86xx was treating the virtual P2P PCIe bridge as a transparent bridge. Rather than doing that fixup the virtual P2P bridge by copying the resources from the PHB. Also, fixup a bit of the code for dealing with resource_size_t being 64-bits and how we set ATMU registers for >4G. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Kumar Gala
parent
b188b2aefe
commit
72b122cc30
@ -33,8 +33,8 @@ void __init setup_pci_atmu(struct pci_controller *hose, struct resource *rsrc)
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struct ccsr_pci __iomem *pci;
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int i;
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pr_debug("PCI memory map start 0x%x, size 0x%x\n", rsrc->start,
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rsrc->end - rsrc->start + 1);
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pr_debug("PCI memory map start 0x%016llx, size 0x%016llx\n",
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(u64)rsrc->start, (u64)rsrc->end - (u64)rsrc->start + 1);
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pci = ioremap(rsrc->start, rsrc->end - rsrc->start + 1);
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/* Disable all windows (except powar0 since its ignored) */
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@ -46,17 +46,17 @@ void __init setup_pci_atmu(struct pci_controller *hose, struct resource *rsrc)
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/* Setup outbound MEM window */
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for(i = 0; i < 3; i++)
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if (hose->mem_resources[i].flags & IORESOURCE_MEM){
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pr_debug("PCI MEM resource start 0x%08x, size 0x%08x.\n",
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hose->mem_resources[i].start,
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hose->mem_resources[i].end
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- hose->mem_resources[i].start + 1);
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out_be32(&pci->pow[i+1].potar,
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(hose->mem_resources[i].start >> 12)
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& 0x000fffff);
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resource_size_t pci_addr_start =
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hose->mem_resources[i].start -
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hose->pci_mem_offset;
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pr_debug("PCI MEM resource start 0x%016llx, size 0x%016llx.\n",
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(u64)hose->mem_resources[i].start,
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(u64)hose->mem_resources[i].end
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- (u64)hose->mem_resources[i].start + 1);
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out_be32(&pci->pow[i+1].potar, (pci_addr_start >> 12));
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out_be32(&pci->pow[i+1].potear, 0);
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out_be32(&pci->pow[i+1].powbar,
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(hose->mem_resources[i].start >> 12)
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& 0x000fffff);
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(hose->mem_resources[i].start >> 12));
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/* Enable, Mem R/W */
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out_be32(&pci->pow[i+1].powar, 0x80044000
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| (__ilog2(hose->mem_resources[i].end
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@ -65,15 +65,14 @@ void __init setup_pci_atmu(struct pci_controller *hose, struct resource *rsrc)
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/* Setup outbound IO window */
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if (hose->io_resource.flags & IORESOURCE_IO){
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pr_debug("PCI IO resource start 0x%08x, size 0x%08x, phy base 0x%08x.\n",
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hose->io_resource.start,
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hose->io_resource.end - hose->io_resource.start + 1,
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hose->io_base_phys);
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out_be32(&pci->pow[i+1].potar, (hose->io_resource.start >> 12)
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& 0x000fffff);
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pr_debug("PCI IO resource start 0x%016llx, size 0x%016llx, "
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"phy base 0x%016llx.\n",
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(u64)hose->io_resource.start,
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(u64)hose->io_resource.end - (u64)hose->io_resource.start + 1,
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(u64)hose->io_base_phys);
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out_be32(&pci->pow[i+1].potar, (hose->io_resource.start >> 12));
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out_be32(&pci->pow[i+1].potear, 0);
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out_be32(&pci->pow[i+1].powbar, (hose->io_base_phys >> 12)
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& 0x000fffff);
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out_be32(&pci->pow[i+1].powbar, (hose->io_base_phys >> 12));
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/* Enable, IO R/W */
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out_be32(&pci->pow[i+1].powar, 0x80088000
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| (__ilog2(hose->io_resource.end
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@ -107,55 +106,17 @@ void __init setup_pci_cmd(struct pci_controller *hose)
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}
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}
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static void __init quirk_fsl_pcie_transparent(struct pci_dev *dev)
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{
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struct resource *res;
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int i, res_idx = PCI_BRIDGE_RESOURCES;
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struct pci_controller *hose;
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static int fsl_pcie_bus_fixup;
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static void __init quirk_fsl_pcie_header(struct pci_dev *dev)
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{
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/* if we aren't a PCIe don't bother */
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if (!pci_find_capability(dev, PCI_CAP_ID_EXP))
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return ;
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/*
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* Make the bridge be transparent.
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*/
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dev->transparent = 1;
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hose = pci_bus_to_host(dev->bus);
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if (!hose) {
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printk(KERN_ERR "Can't find hose for bus %d\n",
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dev->bus->number);
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return;
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}
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/* Clear out any of the virtual P2P bridge registers */
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pci_write_config_word(dev, PCI_IO_BASE_UPPER16, 0);
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pci_write_config_word(dev, PCI_IO_LIMIT_UPPER16, 0);
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pci_write_config_byte(dev, PCI_IO_BASE, 0x10);
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pci_write_config_byte(dev, PCI_IO_LIMIT, 0);
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pci_write_config_word(dev, PCI_MEMORY_BASE, 0x10);
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pci_write_config_word(dev, PCI_MEMORY_LIMIT, 0);
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pci_write_config_word(dev, PCI_PREF_BASE_UPPER32, 0x0);
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pci_write_config_word(dev, PCI_PREF_LIMIT_UPPER32, 0x0);
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pci_write_config_word(dev, PCI_PREF_MEMORY_BASE, 0x10);
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pci_write_config_word(dev, PCI_PREF_MEMORY_LIMIT, 0);
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if (hose->io_resource.flags) {
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res = &dev->resource[res_idx++];
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res->start = hose->io_resource.start;
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res->end = hose->io_resource.end;
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res->flags = hose->io_resource.flags;
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update_bridge_resource(dev, res);
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}
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for (i = 0; i < 3; i++) {
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res = &dev->resource[res_idx + i];
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res->start = hose->mem_resources[i].start;
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res->end = hose->mem_resources[i].end;
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res->flags = hose->mem_resources[i].flags;
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update_bridge_resource(dev, res);
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}
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dev->class = PCI_CLASS_BRIDGE_PCI << 8;
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fsl_pcie_bus_fixup = 1;
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return ;
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}
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int __init fsl_pcie_check_link(struct pci_controller *hose)
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@ -172,11 +133,24 @@ void fsl_pcibios_fixup_bus(struct pci_bus *bus)
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struct pci_controller *hose = (struct pci_controller *) bus->sysdata;
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int i;
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/* deal with bogus pci_bus when we don't have anything connected on PCIe */
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if (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK) {
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if (bus->parent) {
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for (i = 0; i < 4; ++i)
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bus->resource[i] = bus->parent->resource[i];
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if ((bus->parent == hose->bus) &&
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((fsl_pcie_bus_fixup &&
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early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) ||
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(hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK)))
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{
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for (i = 0; i < 4; ++i) {
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struct resource *res = bus->resource[i];
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struct resource *par = bus->parent->resource[i];
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if (res) {
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res->start = 0;
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res->end = 0;
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res->flags = 0;
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}
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if (res && par) {
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res->start = par->start;
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res->end = par->end;
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res->flags = par->flags;
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}
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}
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}
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}
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@ -240,23 +214,23 @@ int __init fsl_add_bridge(struct device_node *dev, int is_primary)
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return 0;
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}
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DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8548E, quirk_fsl_pcie_transparent);
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DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8548, quirk_fsl_pcie_transparent);
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DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8543E, quirk_fsl_pcie_transparent);
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DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8543, quirk_fsl_pcie_transparent);
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DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8547E, quirk_fsl_pcie_transparent);
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DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8545E, quirk_fsl_pcie_transparent);
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DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8545, quirk_fsl_pcie_transparent);
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DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8568E, quirk_fsl_pcie_transparent);
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DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8568, quirk_fsl_pcie_transparent);
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DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8567E, quirk_fsl_pcie_transparent);
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DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8567, quirk_fsl_pcie_transparent);
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DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8533E, quirk_fsl_pcie_transparent);
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DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8533, quirk_fsl_pcie_transparent);
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DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8544E, quirk_fsl_pcie_transparent);
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DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8544, quirk_fsl_pcie_transparent);
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DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8572E, quirk_fsl_pcie_transparent);
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DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8572, quirk_fsl_pcie_transparent);
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DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8641, quirk_fsl_pcie_transparent);
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DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8641D, quirk_fsl_pcie_transparent);
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DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8610, quirk_fsl_pcie_transparent);
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DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8548E, quirk_fsl_pcie_header);
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DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8548, quirk_fsl_pcie_header);
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DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8543E, quirk_fsl_pcie_header);
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DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8543, quirk_fsl_pcie_header);
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DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8547E, quirk_fsl_pcie_header);
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DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8545E, quirk_fsl_pcie_header);
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DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8545, quirk_fsl_pcie_header);
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DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8568E, quirk_fsl_pcie_header);
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DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8568, quirk_fsl_pcie_header);
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DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8567E, quirk_fsl_pcie_header);
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DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8567, quirk_fsl_pcie_header);
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DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8533E, quirk_fsl_pcie_header);
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DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8533, quirk_fsl_pcie_header);
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DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8544E, quirk_fsl_pcie_header);
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DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8544, quirk_fsl_pcie_header);
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DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8572E, quirk_fsl_pcie_header);
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DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8572, quirk_fsl_pcie_header);
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DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8641, quirk_fsl_pcie_header);
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DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8641D, quirk_fsl_pcie_header);
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DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8610, quirk_fsl_pcie_header);
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