mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-25 16:30:53 +07:00
[POWERPC] Rewrite Freescale PCI/PCIe support for 8{3,5,6}xx
Rewrite the Freescale PCI code to support PCI on 83xx/85xx/86xx and PCIe on 85xx/86xx. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Zang Roy-r61911
Kumar Gala
parent
55c44991e2
commit
9ac4dd301e
@ -211,8 +211,8 @@ serial@4600 {
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interrupt-parent = <&mpic>;
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};
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pci@8000 {
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compatible = "86xx";
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pcie@8000 {
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compatible = "fsl,mpc8641-pcie";
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device_type = "pci";
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#interrupt-cells = <1>;
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#size-cells = <2>;
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@ -399,8 +399,8 @@ gpio@400 {
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};
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pci@9000 {
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compatible = "86xx";
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pcie@9000 {
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compatible = "fsl,mpc8641-pcie";
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device_type = "pci";
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#interrupt-cells = <1>;
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#size-cells = <2>;
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@ -15,11 +15,6 @@
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* mpc86xx_* files. Mostly for use by mpc86xx_setup().
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*/
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extern int mpc86xx_add_bridge(struct device_node *dev);
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extern int mpc86xx_exclude_device(struct pci_controller *hose,
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u_char bus, u_char devfn);
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extern void __init mpc86xx_smp_init(void);
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#endif /* __MPC86XX_H__ */
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@ -31,6 +31,7 @@
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#include <asm/mpic.h>
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#include <sysdev/fsl_pci.h>
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#include <sysdev/fsl_soc.h>
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#include "mpc86xx.h"
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@ -344,8 +345,14 @@ mpc86xx_hpcn_setup_arch(void)
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}
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#ifdef CONFIG_PCI
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for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;)
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mpc86xx_add_bridge(np);
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for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;) {
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struct resource rsrc;
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of_address_to_resource(np, 0, &rsrc);
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if ((rsrc.start & 0xfffff) == 0x8000)
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fsl_add_bridge(np, 1);
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else
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fsl_add_bridge(np, 0);
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}
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#endif
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printk("MPC86xx HPCN board from Freescale Semiconductor\n");
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@ -1,136 +1,98 @@
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/*
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* MPC86XX pci setup code
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* MPC85xx/86xx PCI/PCIE support routing.
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*
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* Copyright 2007 Freescale Semiconductor, Inc
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*
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* Recode: ZHANG WEI <wei.zhang@freescale.com>
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* Initial author: Xianghua Xiao <x.xiao@freescale.com>
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*
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* Copyright 2006 Freescale Semiconductor Inc.
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* Recode: ZHANG WEI <wei.zhang@freescale.com>
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* Rewrite the routing for Frescale PCI and PCI Express
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* Roy Zang <tie-fei.zang@freescale.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/types.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/serial.h>
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#include <linux/delay.h>
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#include <linux/string.h>
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#include <linux/init.h>
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#include <linux/bootmem.h>
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#include <asm/system.h>
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#include <asm/atomic.h>
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#include <asm/io.h>
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#include <asm/prom.h>
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#include <asm/pci-bridge.h>
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#include <asm/machdep.h>
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#include <sysdev/fsl_soc.h>
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#include <sysdev/fsl_pci.h>
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#include "../platforms/86xx/mpc86xx.h"
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#undef DEBUG
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#ifdef DEBUG
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#define DBG(fmt, args...) printk(KERN_ERR "%s: " fmt, __FUNCTION__, ## args)
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#else
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#define DBG(fmt, args...)
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#endif
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struct pcie_outbound_window_regs {
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uint pexotar; /* 0x.0 - PCI Express outbound translation address register */
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uint pexotear; /* 0x.4 - PCI Express outbound translation extended address register */
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uint pexowbar; /* 0x.8 - PCI Express outbound window base address register */
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char res1[4];
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uint pexowar; /* 0x.10 - PCI Express outbound window attributes register */
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char res2[12];
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};
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struct pcie_inbound_window_regs {
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uint pexitar; /* 0x.0 - PCI Express inbound translation address register */
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char res1[4];
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uint pexiwbar; /* 0x.8 - PCI Express inbound window base address register */
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uint pexiwbear; /* 0x.c - PCI Express inbound window base extended address register */
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uint pexiwar; /* 0x.10 - PCI Express inbound window attributes register */
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char res2[12];
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};
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static void __init setup_pcie_atmu(struct pci_controller *hose, struct resource *rsrc)
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/* atmu setup for fsl pci/pcie controller */
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void __init setup_pci_atmu(struct pci_controller *hose, struct resource *rsrc)
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{
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volatile struct ccsr_pex *pcie;
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volatile struct pcie_outbound_window_regs *pcieow;
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volatile struct pcie_inbound_window_regs *pcieiw;
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int i = 0;
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struct ccsr_pci __iomem *pci;
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int i;
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DBG("PCIE memory map start 0x%x, size 0x%x\n", rsrc->start,
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pr_debug("PCI memory map start 0x%x, size 0x%x\n", rsrc->start,
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rsrc->end - rsrc->start + 1);
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pcie = ioremap(rsrc->start, rsrc->end - rsrc->start + 1);
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pci = ioremap(rsrc->start, rsrc->end - rsrc->start + 1);
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/* Disable all windows (except pexowar0 since its ignored) */
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pcie->pexowar1 = 0;
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pcie->pexowar2 = 0;
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pcie->pexowar3 = 0;
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pcie->pexowar4 = 0;
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pcie->pexiwar1 = 0;
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pcie->pexiwar2 = 0;
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pcie->pexiwar3 = 0;
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/* Disable all windows (except powar0 since its ignored) */
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for(i = 1; i < 5; i++)
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out_be32(&pci->pow[i].powar, 0);
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for(i = 0; i < 3; i++)
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out_be32(&pci->piw[i].piwar, 0);
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pcieow = (struct pcie_outbound_window_regs *)&pcie->pexotar1;
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pcieiw = (struct pcie_inbound_window_regs *)&pcie->pexitar1;
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/* Setup outbound MEM window */
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for(i = 0; i < 3; i++)
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if (hose->mem_resources[i].flags & IORESOURCE_MEM){
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pr_debug("PCI MEM resource start 0x%08x, size 0x%08x.\n",
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hose->mem_resources[i].start,
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hose->mem_resources[i].end
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- hose->mem_resources[i].start + 1);
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out_be32(&pci->pow[i+1].potar,
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(hose->mem_resources[i].start >> 12)
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& 0x000fffff);
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out_be32(&pci->pow[i+1].potear, 0);
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out_be32(&pci->pow[i+1].powbar,
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(hose->mem_resources[i].start >> 12)
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& 0x000fffff);
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/* Enable, Mem R/W */
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out_be32(&pci->pow[i+1].powar, 0x80044000
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| (__ilog2(hose->mem_resources[i].end
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- hose->mem_resources[i].start + 1) - 1));
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}
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/* Setup outbound MEM window */
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for(i = 0; i < 3; i++)
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if (hose->mem_resources[i].flags & IORESOURCE_MEM){
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DBG("PCIE MEM resource start 0x%08x, size 0x%08x.\n",
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hose->mem_resources[i].start,
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hose->mem_resources[i].end
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- hose->mem_resources[i].start + 1);
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pcieow->pexotar = (hose->mem_resources[i].start) >> 12
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& 0x000fffff;
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pcieow->pexotear = 0;
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pcieow->pexowbar = (hose->mem_resources[i].start) >> 12
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& 0x000fffff;
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/* Enable, Mem R/W */
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pcieow->pexowar = 0x80044000 |
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(__ilog2(hose->mem_resources[i].end
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- hose->mem_resources[i].start + 1)
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- 1);
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pcieow++;
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}
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/* Setup outbound IO window */
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if (hose->io_resource.flags & IORESOURCE_IO){
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pr_debug("PCI IO resource start 0x%08x, size 0x%08x, phy base 0x%08x.\n",
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hose->io_resource.start,
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hose->io_resource.end - hose->io_resource.start + 1,
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hose->io_base_phys);
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out_be32(&pci->pow[i+1].potar, (hose->io_resource.start >> 12)
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& 0x000fffff);
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out_be32(&pci->pow[i+1].potear, 0);
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out_be32(&pci->pow[i+1].powbar, (hose->io_base_phys >> 12)
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& 0x000fffff);
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/* Enable, IO R/W */
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out_be32(&pci->pow[i+1].powar, 0x80088000
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| (__ilog2(hose->io_resource.end
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- hose->io_resource.start + 1) - 1));
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}
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/* Setup outbound IO window */
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if (hose->io_resource.flags & IORESOURCE_IO){
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DBG("PCIE IO resource start 0x%08x, size 0x%08x, phy base 0x%08x.\n",
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hose->io_resource.start,
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hose->io_resource.end - hose->io_resource.start + 1,
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hose->io_base_phys);
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pcieow->pexotar = (hose->io_resource.start) >> 12 & 0x000fffff;
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pcieow->pexotear = 0;
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pcieow->pexowbar = (hose->io_base_phys) >> 12 & 0x000fffff;
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/* Enable, IO R/W */
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pcieow->pexowar = 0x80088000 | (__ilog2(hose->io_resource.end
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- hose->io_resource.start + 1) - 1);
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}
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/* Setup 2G inbound Memory Window @ 0 */
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pcieiw->pexitar = 0x00000000;
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pcieiw->pexiwbar = 0x00000000;
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/* Enable, Prefetch, Local Mem, Snoop R/W, 2G */
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pcieiw->pexiwar = 0xa0f5501e;
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/* Setup 2G inbound Memory Window @ 1 */
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out_be32(&pci->piw[2].pitar, 0x00000000);
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out_be32(&pci->piw[2].piwbar,0x00000000);
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out_be32(&pci->piw[2].piwar, PIWAR_2G);
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}
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static void __init
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mpc86xx_setup_pcie(struct pci_controller *hose, u32 pcie_offset, u32 pcie_size)
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void __init setup_pci_cmd(struct pci_controller *hose)
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{
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u16 cmd;
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DBG("PCIE host controller register offset 0x%08x, size 0x%08x.\n",
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pcie_offset, pcie_size);
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early_read_config_word(hose, 0, 0, PCI_COMMAND, &cmd);
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cmd |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY
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| PCI_COMMAND_IO;
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| PCI_COMMAND_IO;
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early_write_config_word(hose, 0, 0, PCI_COMMAND, cmd);
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early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80);
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}
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@ -167,72 +129,76 @@ static void __devinit quirk_fsl_pcie_transparent(struct pci_dev *dev)
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}
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}
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int __init fsl_pcie_check_link(struct pci_controller *hose)
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{
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u16 val;
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early_read_config_word(hose, 0, 0, PCIE_LTSSM, &val);
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if (val < PCIE_LTSSM_L0)
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return 1;
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return 0;
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}
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DECLARE_PCI_FIXUP_EARLY(0x1957, 0x7010, quirk_fsl_pcie_transparent);
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DECLARE_PCI_FIXUP_EARLY(0x1957, 0x7011, quirk_fsl_pcie_transparent);
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#define PCIE_LTSSM 0x404 /* PCIe Link Training and Status */
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#define PCIE_LTSSM_L0 0x16 /* L0 state */
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int __init mpc86xx_add_bridge(struct device_node *dev)
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int __init fsl_add_bridge(struct device_node *dev, int is_primary)
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{
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int len;
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struct pci_controller *hose;
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struct resource rsrc;
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const int *bus_range;
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int has_address = 0;
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int primary = 0;
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u16 val;
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DBG("Adding PCIE host bridge %s\n", dev->full_name);
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pr_debug("Adding PCI host bridge %s\n", dev->full_name);
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/* Fetch host bridge registers address */
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has_address = (of_address_to_resource(dev, 0, &rsrc) == 0);
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if (of_address_to_resource(dev, 0, &rsrc)) {
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printk(KERN_WARNING "Can't get pci register base!");
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return -ENOMEM;
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}
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/* Get bus range if any */
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bus_range = of_get_property(dev, "bus-range", &len);
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if (bus_range == NULL || len < 2 * sizeof(int))
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printk(KERN_WARNING "Can't get bus-range for %s, assume"
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" bus 0\n", dev->full_name);
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" bus 0\n", dev->full_name);
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pci_assign_all_buses = 1;
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hose = pcibios_alloc_controller(dev);
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if (!hose)
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return -ENOMEM;
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hose->indirect_type = PPC_INDIRECT_TYPE_EXT_REG |
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PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS;
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hose->first_busno = bus_range ? bus_range[0] : 0x0;
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hose->last_busno = bus_range ? bus_range[1] : 0xff;
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/* check PCI express bridge */
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if (of_device_is_compatible(dev, "fsl,mpc8548-pcie") ||
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of_device_is_compatible(dev, "fsl,mpc8641-pcie"))
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hose->indirect_type = PPC_INDIRECT_TYPE_EXT_REG |
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PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS;
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setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4);
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setup_pci_cmd(hose);
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/* Probe the hose link training status */
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early_read_config_word(hose, 0, 0, PCIE_LTSSM, &val);
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if (val < PCIE_LTSSM_L0)
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return -ENXIO;
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/* check PCI express link status */
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if (of_device_is_compatible(dev, "fsl,mpc8548-pcie") ||
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of_device_is_compatible(dev, "fsl,mpc8641-pcie"))
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if (fsl_pcie_check_link(hose))
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return -ENXIO;
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/* Setup the PCIE host controller. */
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mpc86xx_setup_pcie(hose, rsrc.start, rsrc.end - rsrc.start + 1);
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printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx."
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"Firmware bus number: %d->%d\n",
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(unsigned long long)rsrc.start, hose->first_busno,
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hose->last_busno);
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if ((rsrc.start & 0xfffff) == 0x8000)
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primary = 1;
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printk(KERN_INFO "Found MPC86xx PCIE host bridge at 0x%08lx. "
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"Firmware bus number: %d->%d\n",
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(unsigned long) rsrc.start,
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hose->first_busno, hose->last_busno);
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DBG(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
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pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
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hose, hose->cfg_addr, hose->cfg_data);
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/* Interpret the "ranges" property */
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/* This also maps the I/O region and sets isa_io/mem_base */
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pci_process_bridge_OF_ranges(hose, dev, primary);
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pci_process_bridge_OF_ranges(hose, dev, is_primary);
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/* Setup PEX window registers */
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setup_pcie_atmu(hose, &rsrc);
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setup_pci_atmu(hose, &rsrc);
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return 0;
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}
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DECLARE_PCI_FIXUP_EARLY(0x1957, 0x7010, quirk_fsl_pcie_transparent);
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DECLARE_PCI_FIXUP_EARLY(0x1957, 0x7011, quirk_fsl_pcie_transparent);
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@ -11,84 +11,77 @@
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*/
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#ifdef __KERNEL__
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#ifndef __POWERPC_FSL_PCIE_H
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#define __POWERPC_FSL_PCIE_H
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#ifndef __POWERPC_FSL_PCI_H
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#define __POWERPC_FSL_PCI_H
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/* PCIE Express IO block registers in 85xx/86xx */
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#define PCIE_LTSSM 0x0404 /* PCIE Link Training and Status */
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#define PCIE_LTSSM_L0 0x16 /* L0 state */
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#define PIWAR_2G 0xa0f5501e /* Enable, Prefetch, Local Mem, Snoop R/W, 2G */
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struct ccsr_pex {
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__be32 __iomem pex_config_addr; /* 0x.000 - PCI Express Configuration Address Register */
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__be32 __iomem pex_config_data; /* 0x.004 - PCI Express Configuration Data Register */
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u8 __iomem res1[4];
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__be32 __iomem pex_otb_cpl_tor; /* 0x.00c - PCI Express Outbound completion timeout register */
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__be32 __iomem pex_conf_tor; /* 0x.010 - PCI Express configuration timeout register */
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u8 __iomem res2[12];
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__be32 __iomem pex_pme_mes_dr; /* 0x.020 - PCI Express PME and message detect register */
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__be32 __iomem pex_pme_mes_disr; /* 0x.024 - PCI Express PME and message disable register */
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__be32 __iomem pex_pme_mes_ier; /* 0x.028 - PCI Express PME and message interrupt enable register */
|
||||
__be32 __iomem pex_pmcr; /* 0x.02c - PCI Express power management command register */
|
||||
u8 __iomem res3[3024];
|
||||
__be32 __iomem pexotar0; /* 0x.c00 - PCI Express outbound translation address register 0 */
|
||||
__be32 __iomem pexotear0; /* 0x.c04 - PCI Express outbound translation extended address register 0*/
|
||||
u8 __iomem res4[8];
|
||||
__be32 __iomem pexowar0; /* 0x.c10 - PCI Express outbound window attributes register 0*/
|
||||
u8 __iomem res5[12];
|
||||
__be32 __iomem pexotar1; /* 0x.c20 - PCI Express outbound translation address register 1 */
|
||||
__be32 __iomem pexotear1; /* 0x.c24 - PCI Express outbound translation extended address register 1*/
|
||||
__be32 __iomem pexowbar1; /* 0x.c28 - PCI Express outbound window base address register 1*/
|
||||
u8 __iomem res6[4];
|
||||
__be32 __iomem pexowar1; /* 0x.c30 - PCI Express outbound window attributes register 1*/
|
||||
u8 __iomem res7[12];
|
||||
__be32 __iomem pexotar2; /* 0x.c40 - PCI Express outbound translation address register 2 */
|
||||
__be32 __iomem pexotear2; /* 0x.c44 - PCI Express outbound translation extended address register 2*/
|
||||
__be32 __iomem pexowbar2; /* 0x.c48 - PCI Express outbound window base address register 2*/
|
||||
u8 __iomem res8[4];
|
||||
__be32 __iomem pexowar2; /* 0x.c50 - PCI Express outbound window attributes register 2*/
|
||||
u8 __iomem res9[12];
|
||||
__be32 __iomem pexotar3; /* 0x.c60 - PCI Express outbound translation address register 3 */
|
||||
__be32 __iomem pexotear3; /* 0x.c64 - PCI Express outbound translation extended address register 3*/
|
||||
__be32 __iomem pexowbar3; /* 0x.c68 - PCI Express outbound window base address register 3*/
|
||||
u8 __iomem res10[4];
|
||||
__be32 __iomem pexowar3; /* 0x.c70 - PCI Express outbound window attributes register 3*/
|
||||
u8 __iomem res11[12];
|
||||
__be32 __iomem pexotar4; /* 0x.c80 - PCI Express outbound translation address register 4 */
|
||||
__be32 __iomem pexotear4; /* 0x.c84 - PCI Express outbound translation extended address register 4*/
|
||||
__be32 __iomem pexowbar4; /* 0x.c88 - PCI Express outbound window base address register 4*/
|
||||
u8 __iomem res12[4];
|
||||
__be32 __iomem pexowar4; /* 0x.c90 - PCI Express outbound window attributes register 4*/
|
||||
u8 __iomem res13[12];
|
||||
u8 __iomem res14[256];
|
||||
__be32 __iomem pexitar3; /* 0x.da0 - PCI Express inbound translation address register 3 */
|
||||
u8 __iomem res15[4];
|
||||
__be32 __iomem pexiwbar3; /* 0x.da8 - PCI Express inbound window base address register 3 */
|
||||
__be32 __iomem pexiwbear3; /* 0x.dac - PCI Express inbound window base extended address register 3 */
|
||||
__be32 __iomem pexiwar3; /* 0x.db0 - PCI Express inbound window attributes register 3 */
|
||||
u8 __iomem res16[12];
|
||||
__be32 __iomem pexitar2; /* 0x.dc0 - PCI Express inbound translation address register 2 */
|
||||
u8 __iomem res17[4];
|
||||
__be32 __iomem pexiwbar2; /* 0x.dc8 - PCI Express inbound window base address register 2 */
|
||||
__be32 __iomem pexiwbear2; /* 0x.dcc - PCI Express inbound window base extended address register 2 */
|
||||
__be32 __iomem pexiwar2; /* 0x.dd0 - PCI Express inbound window attributes register 2 */
|
||||
u8 __iomem res18[12];
|
||||
__be32 __iomem pexitar1; /* 0x.de0 - PCI Express inbound translation address register 2 */
|
||||
u8 __iomem res19[4];
|
||||
__be32 __iomem pexiwbar1; /* 0x.de8 - PCI Express inbound window base address register 2 */
|
||||
__be32 __iomem pexiwbear1; /* 0x.dec - PCI Express inbound window base extended address register 2 */
|
||||
__be32 __iomem pexiwar1; /* 0x.df0 - PCI Express inbound window attributes register 2 */
|
||||
u8 __iomem res20[12];
|
||||
__be32 __iomem pex_err_dr; /* 0x.e00 - PCI Express error detect register */
|
||||
u8 __iomem res21[4];
|
||||
__be32 __iomem pex_err_en; /* 0x.e08 - PCI Express error interrupt enable register */
|
||||
u8 __iomem res22[4];
|
||||
__be32 __iomem pex_err_disr; /* 0x.e10 - PCI Express error disable register */
|
||||
u8 __iomem res23[12];
|
||||
__be32 __iomem pex_err_cap_stat; /* 0x.e20 - PCI Express error capture status register */
|
||||
u8 __iomem res24[4];
|
||||
__be32 __iomem pex_err_cap_r0; /* 0x.e28 - PCI Express error capture register 0 */
|
||||
__be32 __iomem pex_err_cap_r1; /* 0x.e2c - PCI Express error capture register 0 */
|
||||
__be32 __iomem pex_err_cap_r2; /* 0x.e30 - PCI Express error capture register 0 */
|
||||
__be32 __iomem pex_err_cap_r3; /* 0x.e34 - PCI Express error capture register 0 */
|
||||
/* PCI/PCI Express outbound window reg */
|
||||
struct pci_outbound_window_regs {
|
||||
__be32 potar; /* 0x.0 - Outbound translation address register */
|
||||
__be32 potear; /* 0x.4 - Outbound translation extended address register */
|
||||
__be32 powbar; /* 0x.8 - Outbound window base address register */
|
||||
u8 res1[4];
|
||||
__be32 powar; /* 0x.10 - Outbound window attributes register */
|
||||
u8 res2[12];
|
||||
};
|
||||
|
||||
#endif /* __POWERPC_FSL_PCIE_H */
|
||||
/* PCI/PCI Express inbound window reg */
|
||||
struct pci_inbound_window_regs {
|
||||
__be32 pitar; /* 0x.0 - Inbound translation address register */
|
||||
u8 res1[4];
|
||||
__be32 piwbar; /* 0x.8 - Inbound window base address register */
|
||||
__be32 piwbear; /* 0x.c - Inbound window base extended address register */
|
||||
__be32 piwar; /* 0x.10 - Inbound window attributes register */
|
||||
u8 res2[12];
|
||||
};
|
||||
|
||||
/* PCI/PCI Express IO block registers for 85xx/86xx */
|
||||
struct ccsr_pci {
|
||||
__be32 config_addr; /* 0x.000 - PCI/PCIE Configuration Address Register */
|
||||
__be32 config_data; /* 0x.004 - PCI/PCIE Configuration Data Register */
|
||||
__be32 int_ack; /* 0x.008 - PCI Interrupt Acknowledge Register */
|
||||
__be32 pex_otb_cpl_tor; /* 0x.00c - PCIE Outbound completion timeout register */
|
||||
__be32 pex_conf_tor; /* 0x.010 - PCIE configuration timeout register */
|
||||
u8 res2[12];
|
||||
__be32 pex_pme_mes_dr; /* 0x.020 - PCIE PME and message detect register */
|
||||
__be32 pex_pme_mes_disr; /* 0x.024 - PCIE PME and message disable register */
|
||||
__be32 pex_pme_mes_ier; /* 0x.028 - PCIE PME and message interrupt enable register */
|
||||
__be32 pex_pmcr; /* 0x.02c - PCIE power management command register */
|
||||
u8 res3[3024];
|
||||
|
||||
/* PCI/PCI Express outbound window 0-4
|
||||
* Window 0 is the default window and is the only window enabled upon reset.
|
||||
* The default outbound register set is used when a transaction misses
|
||||
* in all of the other outbound windows.
|
||||
*/
|
||||
struct pci_outbound_window_regs pow[5];
|
||||
|
||||
u8 res14[256];
|
||||
|
||||
/* PCI/PCI Express inbound window 3-1
|
||||
* inbound window 1 supports only a 32-bit base address and does not
|
||||
* define an inbound window base extended address register.
|
||||
*/
|
||||
struct pci_inbound_window_regs piw[3];
|
||||
|
||||
__be32 pex_err_dr; /* 0x.e00 - PCI/PCIE error detect register */
|
||||
u8 res21[4];
|
||||
__be32 pex_err_en; /* 0x.e08 - PCI/PCIE error interrupt enable register */
|
||||
u8 res22[4];
|
||||
__be32 pex_err_disr; /* 0x.e10 - PCI/PCIE error disable register */
|
||||
u8 res23[12];
|
||||
__be32 pex_err_cap_stat; /* 0x.e20 - PCI/PCIE error capture status register */
|
||||
u8 res24[4];
|
||||
__be32 pex_err_cap_r0; /* 0x.e28 - PCIE error capture register 0 */
|
||||
__be32 pex_err_cap_r1; /* 0x.e2c - PCIE error capture register 0 */
|
||||
__be32 pex_err_cap_r2; /* 0x.e30 - PCIE error capture register 0 */
|
||||
__be32 pex_err_cap_r3; /* 0x.e34 - PCIE error capture register 0 */
|
||||
};
|
||||
|
||||
extern int fsl_add_bridge(struct device_node *dev, int is_primary);
|
||||
|
||||
#endif /* __POWERPC_FSL_PCI_H */
|
||||
#endif /* __KERNEL__ */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user