DRM: i915: add mode setting support
This commit adds i915 driver support for the DRM mode setting APIs.
Currently, VGA, LVDS, SDVO DVI & VGA, TV and DVO LVDS outputs are
supported. HDMI, DisplayPort and additional SDVO output support will
follow.
Support for the mode setting code is controlled by the new 'modeset'
module option. A new config option, CONFIG_DRM_I915_KMS controls the
default behavior, and whether a PCI ID list is built into the module for
use by user level module utilities.
Note that if mode setting is enabled, user level drivers that access
display registers directly or that don't use the kernel graphics memory
manager will likely corrupt kernel graphics memory, disrupt output
configuration (possibly leading to hangs and/or blank displays), and
prevent panic/oops messages from appearing. So use caution when
enabling this code; be sure your user level code supports the new
interfaces.
A new SysRq key, 'g', provides emergency support for switching back to
the kernel's framebuffer console; which is useful for testing.
Co-authors: Dave Airlie <airlied@linux.ie>, Hong Liu <hong.liu@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2008-11-08 05:24:08 +07:00
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/*
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* Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
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* Copyright (c) 2007-2008 Intel Corporation
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* Jesse Barnes <jesse.barnes@intel.com>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#ifndef __INTEL_DRV_H__
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#define __INTEL_DRV_H__
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2014-05-29 04:39:03 +07:00
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#include <linux/async.h>
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DRM: i915: add mode setting support
This commit adds i915 driver support for the DRM mode setting APIs.
Currently, VGA, LVDS, SDVO DVI & VGA, TV and DVO LVDS outputs are
supported. HDMI, DisplayPort and additional SDVO output support will
follow.
Support for the mode setting code is controlled by the new 'modeset'
module option. A new config option, CONFIG_DRM_I915_KMS controls the
default behavior, and whether a PCI ID list is built into the module for
use by user level module utilities.
Note that if mode setting is enabled, user level drivers that access
display registers directly or that don't use the kernel graphics memory
manager will likely corrupt kernel graphics memory, disrupt output
configuration (possibly leading to hangs and/or blank displays), and
prevent panic/oops messages from appearing. So use caution when
enabling this code; be sure your user level code supports the new
interfaces.
A new SysRq key, 'g', provides emergency support for switching back to
the kernel's framebuffer console; which is useful for testing.
Co-authors: Dave Airlie <airlied@linux.ie>, Hong Liu <hong.liu@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2008-11-08 05:24:08 +07:00
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#include <linux/i2c.h>
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2017-02-01 22:36:40 +07:00
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#include <linux/sched/clock.h>
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2019-04-05 18:00:18 +07:00
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#include <drm/drm_atomic.h>
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2012-10-03 00:01:07 +07:00
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#include <drm/drm_crtc.h>
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2016-05-03 02:08:23 +07:00
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#include <drm/drm_dp_dual_mode_helper.h>
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2014-05-02 11:02:48 +07:00
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#include <drm/drm_dp_mst_helper.h>
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2019-04-05 18:00:18 +07:00
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#include <drm/drm_encoder.h>
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#include <drm/drm_fb_helper.h>
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2019-01-18 04:03:34 +07:00
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#include <drm/drm_probe_helper.h>
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2014-09-06 03:04:46 +07:00
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#include <drm/drm_rect.h>
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2019-01-18 04:03:34 +07:00
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#include <drm/drm_vblank.h>
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2019-04-05 18:00:18 +07:00
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#include <drm/i915_drm.h>
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2019-02-17 00:36:51 +07:00
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#include <drm/i915_mei_hdcp_interface.h>
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2018-07-04 22:08:17 +07:00
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#include <media/cec-notifier.h>
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2010-08-07 17:01:35 +07:00
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2019-04-05 18:00:18 +07:00
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#include "i915_drv.h"
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2019-01-14 21:21:09 +07:00
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struct drm_printer;
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DRM: i915: add mode setting support
This commit adds i915 driver support for the DRM mode setting APIs.
Currently, VGA, LVDS, SDVO DVI & VGA, TV and DVO LVDS outputs are
supported. HDMI, DisplayPort and additional SDVO output support will
follow.
Support for the mode setting code is controlled by the new 'modeset'
module option. A new config option, CONFIG_DRM_I915_KMS controls the
default behavior, and whether a PCI ID list is built into the module for
use by user level module utilities.
Note that if mode setting is enabled, user level drivers that access
display registers directly or that don't use the kernel graphics memory
manager will likely corrupt kernel graphics memory, disrupt output
configuration (possibly leading to hangs and/or blank displays), and
prevent panic/oops messages from appearing. So use caution when
enabling this code; be sure your user level code supports the new
interfaces.
A new SysRq key, 'g', provides emergency support for switching back to
the kernel's framebuffer console; which is useful for testing.
Co-authors: Dave Airlie <airlied@linux.ie>, Hong Liu <hong.liu@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2008-11-08 05:24:08 +07:00
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/*
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* Display related stuff
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*/
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/* these are outputs from the chip - integrated only
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external chips are via DVO or SDVO output */
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2014-10-28 02:47:52 +07:00
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enum intel_output_type {
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INTEL_OUTPUT_UNUSED = 0,
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INTEL_OUTPUT_ANALOG = 1,
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INTEL_OUTPUT_DVO = 2,
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INTEL_OUTPUT_SDVO = 3,
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INTEL_OUTPUT_LVDS = 4,
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INTEL_OUTPUT_TVOUT = 5,
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INTEL_OUTPUT_HDMI = 6,
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2016-06-23 01:57:06 +07:00
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INTEL_OUTPUT_DP = 7,
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2014-10-28 02:47:52 +07:00
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INTEL_OUTPUT_EDP = 8,
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INTEL_OUTPUT_DSI = 9,
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2017-10-28 02:31:24 +07:00
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INTEL_OUTPUT_DDI = 10,
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2014-10-28 02:47:52 +07:00
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INTEL_OUTPUT_DP_MST = 11,
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};
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DRM: i915: add mode setting support
This commit adds i915 driver support for the DRM mode setting APIs.
Currently, VGA, LVDS, SDVO DVI & VGA, TV and DVO LVDS outputs are
supported. HDMI, DisplayPort and additional SDVO output support will
follow.
Support for the mode setting code is controlled by the new 'modeset'
module option. A new config option, CONFIG_DRM_I915_KMS controls the
default behavior, and whether a PCI ID list is built into the module for
use by user level module utilities.
Note that if mode setting is enabled, user level drivers that access
display registers directly or that don't use the kernel graphics memory
manager will likely corrupt kernel graphics memory, disrupt output
configuration (possibly leading to hangs and/or blank displays), and
prevent panic/oops messages from appearing. So use caution when
enabling this code; be sure your user level code supports the new
interfaces.
A new SysRq key, 'g', provides emergency support for switching back to
the kernel's framebuffer console; which is useful for testing.
Co-authors: Dave Airlie <airlied@linux.ie>, Hong Liu <hong.liu@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2008-11-08 05:24:08 +07:00
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struct intel_framebuffer {
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struct drm_framebuffer base;
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2016-02-16 03:54:47 +07:00
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struct intel_rotation_info rot_info;
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drm/i915: Rewrite fb rotation GTT handling
Redo the fb rotation handling in order to:
- eliminate the NV12 special casing
- handle fb->offsets[] properly
- make the rotation handling easier for the plane code
To achieve these goals we reduce intel_rotation_info to only contain
(for each plane) the rotated view width,height,stride in tile units,
and the page offset into the object where the plane starts. Each plane
is handled exactly the same way, no special casing for NV12 or other
formats. We then store the computed rotation_info under
intel_framebuffer so that we don't have to recompute it again.
To handle fb->offsets[] we treat them as a linear offsets and convert
them to x/y offsets from the start of the relevant GTT mapping (either
normal or rotated). We store the x/y offsets under intel_framebuffer,
and for some extra convenience we also store the rotated pitch (ie.
tile aligned plane height). So for each plane we have the normal
x/y offsets, rotated x/y offsets, and the rotated pitch. The normal
pitch is available already in fb->pitches[].
While we're gathering up all that extra information, we can also easily
compute the storage requirements for the framebuffer, so that we can
check that the object is big enough to hold it.
When it comes time to deal with the plane source coordinates, we first
rotate the clipped src coordinates to match the relevant GTT view
orientation, then add to them the fb x/y offsets. Next we compute
the aligned surface page offset, and as a result we're left with some
residual x/y offsets. Finally, if required by the hardware, we convert
the remaining x/y offsets into a linear offset.
For gen2/3 we simply skip computing the final page offset, and just
convert the src+fb x/y offsets directly into a linear offset since
that's what the hardware wants.
After this all platforms, incluing SKL+, compute these things in exactly
the same way (excluding alignemnt differences).
v2: Use BIT(DRM_ROTATE_270) instead of ROTATE_270 when rotating
plane src coordinates
Drop some spurious changes that got left behind during
development
v3: Split out more changes to prep patches (Daniel)
s/intel_fb->plane[].foo.bar/intel_fb->foo[].bar/ for brevity
Rename intel_surf_gtt_offset to intel_fb_gtt_offset
Kill the pointless 'plane' parameter from intel_fb_gtt_offset()
v4: Fix alignment vs. alignment-1 when calling
_intel_compute_tile_offset() from intel_fill_fb_info()
Pass the pitch in tiles in
stad of pixels to intel_adjust_tile_offset() from intel_fill_fb_info()
Pass the full width/height of the rotated area to
drm_rect_rotate() for clarity
Use u32 for more offsets
v5: Preserve the upper_32_bits()/lower_32_bits() handling for the
fb ggtt offset (Sivakumar)
v6: Rebase due to drm_plane_state src/dst rects
Cc: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1470821001-25272-2-git-send-email-ville.syrjala@linux.intel.com
Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-09-15 17:16:41 +07:00
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/* for each plane in the normal GTT view */
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struct {
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unsigned int x, y;
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} normal[2];
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/* for each plane in the rotated GTT view */
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struct {
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unsigned int x, y;
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unsigned int pitch; /* pixels */
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} rotated[2];
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DRM: i915: add mode setting support
This commit adds i915 driver support for the DRM mode setting APIs.
Currently, VGA, LVDS, SDVO DVI & VGA, TV and DVO LVDS outputs are
supported. HDMI, DisplayPort and additional SDVO output support will
follow.
Support for the mode setting code is controlled by the new 'modeset'
module option. A new config option, CONFIG_DRM_I915_KMS controls the
default behavior, and whether a PCI ID list is built into the module for
use by user level module utilities.
Note that if mode setting is enabled, user level drivers that access
display registers directly or that don't use the kernel graphics memory
manager will likely corrupt kernel graphics memory, disrupt output
configuration (possibly leading to hangs and/or blank displays), and
prevent panic/oops messages from appearing. So use caution when
enabling this code; be sure your user level code supports the new
interfaces.
A new SysRq key, 'g', provides emergency support for switching back to
the kernel's framebuffer console; which is useful for testing.
Co-authors: Dave Airlie <airlied@linux.ie>, Hong Liu <hong.liu@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2008-11-08 05:24:08 +07:00
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};
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2010-08-26 04:45:57 +07:00
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struct intel_fbdev {
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struct drm_fb_helper helper;
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2014-02-08 03:10:38 +07:00
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struct intel_framebuffer *fb;
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2016-08-15 16:49:06 +07:00
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struct i915_vma *vma;
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2018-02-20 20:42:06 +07:00
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unsigned long vma_flags;
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2016-06-21 15:16:54 +07:00
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async_cookie_t cookie;
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2014-03-07 23:57:51 +07:00
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int preferred_bpp;
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drm/i915: Block fbdev HPD processing during suspend
When resuming, we check whether or not any previously connected
MST topologies are still present and if so, attempt to resume them. If
this fails, we disable said MST topologies and fire off a hotplug event
so that userspace knows to reprobe.
However, sending a hotplug event involves calling
drm_fb_helper_hotplug_event(), which in turn results in fbcon doing a
connector reprobe in the caller's thread - something we can't do at the
point in which i915 calls drm_dp_mst_topology_mgr_resume() since
hotplugging hasn't been fully initialized yet.
This currently causes some rather subtle but fatal issues. For example,
on my T480s the laptop dock connected to it usually disappears during a
suspend cycle, and comes back up a short while after the system has been
resumed. This guarantees pretty much every suspend and resume cycle,
drm_dp_mst_topology_mgr_set_mst(mgr, false); will be caused and in turn,
a connector hotplug will occur. Now it's Rute Goldberg time: when the
connector hotplug occurs, i915 reprobes /all/ of the connectors,
including eDP. However, eDP probing requires that we power on the panel
VDD which in turn, grabs a wakeref to the appropriate power domain on
the GPU (on my T480s, this is the PORT_DDI_A_IO domain). This is where
things start breaking, since this all happens before
intel_power_domains_enable() is called we end up leaking the wakeref
that was acquired and never releasing it later. Come next suspend/resume
cycle, this causes us to fail to shut down the GPU properly, which
causes it not to resume properly and die a horrible complicated death.
(as a note: this only happens when there's both an eDP panel and MST
topology connected which is removed mid-suspend. One or the other seems
to always be OK).
We could try to fix the VDD wakeref leak, but this doesn't seem like
it's worth it at all since we aren't able to handle hotplug detection
while resuming anyway. So, let's go with a more robust solution inspired
by nouveau: block fbdev from handling hotplug events until we resume
fbdev. This allows us to still send sysfs hotplug events to be handled
later by user space while we're resuming, while also preventing us from
actually processing any hotplug events we receive until it's safe.
This fixes the wakeref leak observed on the T480s and as such, also
fixes suspend/resume with MST topologies connected on this machine.
Changes since v2:
* Don't call drm_fb_helper_hotplug_event() under lock, do it after lock
(Chris Wilson)
* Don't call drm_fb_helper_hotplug_event() in
intel_fbdev_output_poll_changed() under lock (Chris Wilson)
* Always set ifbdev->hpd_waiting (Chris Wilson)
Signed-off-by: Lyude Paul <lyude@redhat.com>
Fixes: 0e32b39ceed6 ("drm/i915: add DP 1.2 MST support (v0.7)")
Cc: Todd Previte <tprevite@gmail.com>
Cc: Dave Airlie <airlied@redhat.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Cc: <stable@vger.kernel.org> # v3.17+
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20190129191001.442-2-lyude@redhat.com
2019-01-30 02:09:59 +07:00
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/* Whether or not fbdev hpd processing is temporarily suspended */
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bool hpd_suspended : 1;
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/* Set when a hotplug was received while HPD processing was
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* suspended
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*/
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bool hpd_waiting : 1;
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/* Protects hpd_suspended */
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struct mutex hpd_lock;
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2010-08-26 04:45:57 +07:00
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};
|
DRM: i915: add mode setting support
This commit adds i915 driver support for the DRM mode setting APIs.
Currently, VGA, LVDS, SDVO DVI & VGA, TV and DVO LVDS outputs are
supported. HDMI, DisplayPort and additional SDVO output support will
follow.
Support for the mode setting code is controlled by the new 'modeset'
module option. A new config option, CONFIG_DRM_I915_KMS controls the
default behavior, and whether a PCI ID list is built into the module for
use by user level module utilities.
Note that if mode setting is enabled, user level drivers that access
display registers directly or that don't use the kernel graphics memory
manager will likely corrupt kernel graphics memory, disrupt output
configuration (possibly leading to hangs and/or blank displays), and
prevent panic/oops messages from appearing. So use caution when
enabling this code; be sure your user level code supports the new
interfaces.
A new SysRq key, 'g', provides emergency support for switching back to
the kernel's framebuffer console; which is useful for testing.
Co-authors: Dave Airlie <airlied@linux.ie>, Hong Liu <hong.liu@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2008-11-08 05:24:08 +07:00
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2010-03-26 01:11:14 +07:00
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struct intel_encoder {
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2010-09-09 21:14:28 +07:00
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struct drm_encoder base;
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drm/i915: stage modeset output changes
This is the core of the new modeset logic.
The current code which is based upon the crtc helper code first
updates all the link of the new display pipeline and then calls the
lower-level set_mode function to execute the required callbacks to get
there. The issue with this approach is that for disabling we need to
know the _current_ display pipe state, not the new one.
Hence we need to stage the new state of the display pipe and only
update it once we have disabled the current configuration and before we
start to update the hw registers with the new configuration.
This patch here just prepares the ground by switching the new output
state computation to these staging pointers. To make it clearer,
rename the old update_output_state function to stage_output_state.
A few peculiarities:
- We're also calling the set_mode function at various places to update
properties. Hence after a successfule modeset we need to stage the
current configuration (for otherwise we might fall back again). This
happens automatically because as part of the (successful) modeset we
need to copy the staged state to the real one. But for the hw
readout code we need to make sure that this happens, too.
- Teach the new staged output state computation code the required
smarts to handle the disabling of outputs. The current code handles
this in a special case, but to better handle global modeset changes
covering more than one crtc, we want to do this all in the same
low-level modeset code.
- The actual modeset code is still a bit ugly and wants to know the new
crtc->enabled state a bit early. Follow-on patches will clean that
up, for now we have to apply the staged output configuration early,
outside of the set_mode functions.
- Improve/add comments in stage_output_state.
Essentially all that is left to do now is move the disabling code into
set_mode and then move the staged state update code also into
set_mode, at the right place between disabling things and calling the
mode_set callbacks for the new configuration.
v2: Disabling a crtc works by passing in a NULL mode or fb, userspace
doesn't hand in the list of connectors. We therefore need to detect
this case manually and tear down all the output links.
v3: Properly update the output staging pointers after having read out
the hw state.
v4: Simplify the code, add more DRM_DEBUG_KMS output and check a few
assumptions with WARN_ON. Essentially all things that I've noticed
while debugging issues in other places of the code.
v4: Correctly disable the old set of connectors when enabling an
already enabled crtc on a new set of crtc. Reported by Paulo Zanoni.
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-07-06 03:34:27 +07:00
|
|
|
|
2014-10-28 02:47:52 +07:00
|
|
|
enum intel_output_type type;
|
2016-09-20 08:24:38 +07:00
|
|
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enum port port;
|
2014-03-03 21:15:28 +07:00
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unsigned int cloneable;
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2018-01-18 02:21:46 +07:00
|
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bool (*hotplug)(struct intel_encoder *encoder,
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struct intel_connector *connector);
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2017-10-28 02:31:24 +07:00
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enum intel_output_type (*compute_output_type)(struct intel_encoder *,
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struct intel_crtc_state *,
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struct drm_connector_state *);
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2019-01-16 03:08:00 +07:00
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int (*compute_config)(struct intel_encoder *,
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struct intel_crtc_state *,
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struct drm_connector_state *);
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2016-08-09 22:04:04 +07:00
|
|
|
void (*pre_pll_enable)(struct intel_encoder *,
|
2017-08-18 20:49:58 +07:00
|
|
|
const struct intel_crtc_state *,
|
|
|
|
const struct drm_connector_state *);
|
2016-08-09 22:04:04 +07:00
|
|
|
void (*pre_enable)(struct intel_encoder *,
|
2017-08-18 20:49:58 +07:00
|
|
|
const struct intel_crtc_state *,
|
|
|
|
const struct drm_connector_state *);
|
2016-08-09 22:04:04 +07:00
|
|
|
void (*enable)(struct intel_encoder *,
|
2017-08-18 20:49:58 +07:00
|
|
|
const struct intel_crtc_state *,
|
|
|
|
const struct drm_connector_state *);
|
2016-08-09 22:04:04 +07:00
|
|
|
void (*disable)(struct intel_encoder *,
|
2017-08-18 20:49:58 +07:00
|
|
|
const struct intel_crtc_state *,
|
|
|
|
const struct drm_connector_state *);
|
2016-08-09 22:04:04 +07:00
|
|
|
void (*post_disable)(struct intel_encoder *,
|
2017-08-18 20:49:58 +07:00
|
|
|
const struct intel_crtc_state *,
|
|
|
|
const struct drm_connector_state *);
|
2016-08-09 22:04:04 +07:00
|
|
|
void (*post_pll_disable)(struct intel_encoder *,
|
2017-08-18 20:49:58 +07:00
|
|
|
const struct intel_crtc_state *,
|
|
|
|
const struct drm_connector_state *);
|
2018-12-20 20:21:18 +07:00
|
|
|
void (*update_pipe)(struct intel_encoder *,
|
|
|
|
const struct intel_crtc_state *,
|
|
|
|
const struct drm_connector_state *);
|
2012-07-02 18:10:34 +07:00
|
|
|
/* Read out the current hw state of this connector, returning true if
|
|
|
|
* the encoder is active. If the encoder is enabled it also set the pipe
|
|
|
|
* it is connected to in the pipe parameter. */
|
|
|
|
bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
|
2013-05-15 07:08:26 +07:00
|
|
|
/* Reconstructs the equivalent mode flags for the current hardware
|
2013-06-12 16:47:24 +07:00
|
|
|
* state. This must be called _after_ display->get_pipe_config has
|
2013-06-28 11:59:06 +07:00
|
|
|
* pre-filled the pipe config. Note that intel_encoder->base.crtc must
|
|
|
|
* be set correctly before calling this function. */
|
2013-05-15 07:08:26 +07:00
|
|
|
void (*get_config)(struct intel_encoder *,
|
2015-01-15 19:55:21 +07:00
|
|
|
struct intel_crtc_state *pipe_config);
|
2019-04-07 19:46:55 +07:00
|
|
|
/*
|
|
|
|
* Acquires the power domains needed for an active encoder during
|
|
|
|
* hardware state readout.
|
|
|
|
*/
|
|
|
|
void (*get_power_domains)(struct intel_encoder *encoder,
|
|
|
|
struct intel_crtc_state *crtc_state);
|
2014-08-18 18:42:45 +07:00
|
|
|
/*
|
|
|
|
* Called during system suspend after all pending requests for the
|
|
|
|
* encoder are flushed (for example for DP AUX transactions) and
|
|
|
|
* device interrupts are disabled.
|
|
|
|
*/
|
|
|
|
void (*suspend)(struct intel_encoder *);
|
2009-08-24 12:50:24 +07:00
|
|
|
int crtc_mask;
|
2013-02-26 00:06:49 +07:00
|
|
|
enum hpd_pin hpd_pin;
|
2017-02-22 13:34:27 +07:00
|
|
|
enum intel_display_power_domain power_domain;
|
2016-09-20 08:24:40 +07:00
|
|
|
/* for communication with audio component; protected by av_mutex */
|
|
|
|
const struct drm_connector *audio_connector;
|
DRM: i915: add mode setting support
This commit adds i915 driver support for the DRM mode setting APIs.
Currently, VGA, LVDS, SDVO DVI & VGA, TV and DVO LVDS outputs are
supported. HDMI, DisplayPort and additional SDVO output support will
follow.
Support for the mode setting code is controlled by the new 'modeset'
module option. A new config option, CONFIG_DRM_I915_KMS controls the
default behavior, and whether a PCI ID list is built into the module for
use by user level module utilities.
Note that if mode setting is enabled, user level drivers that access
display registers directly or that don't use the kernel graphics memory
manager will likely corrupt kernel graphics memory, disrupt output
configuration (possibly leading to hangs and/or blank displays), and
prevent panic/oops messages from appearing. So use caution when
enabling this code; be sure your user level code supports the new
interfaces.
A new SysRq key, 'g', provides emergency support for switching back to
the kernel's framebuffer console; which is useful for testing.
Co-authors: Dave Airlie <airlied@linux.ie>, Hong Liu <hong.liu@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2008-11-08 05:24:08 +07:00
|
|
|
};
|
|
|
|
|
2012-10-19 18:51:49 +07:00
|
|
|
struct intel_panel {
|
2012-10-19 18:51:50 +07:00
|
|
|
struct drm_display_mode *fixed_mode;
|
2013-12-10 15:07:36 +07:00
|
|
|
struct drm_display_mode *downclock_mode;
|
2013-11-08 21:48:54 +07:00
|
|
|
|
|
|
|
/* backlight */
|
|
|
|
struct {
|
2013-11-08 21:48:55 +07:00
|
|
|
bool present;
|
2013-11-08 21:48:54 +07:00
|
|
|
u32 level;
|
2014-06-24 22:27:40 +07:00
|
|
|
u32 min;
|
2013-11-08 21:48:56 +07:00
|
|
|
u32 max;
|
2013-11-08 21:48:54 +07:00
|
|
|
bool enabled;
|
2013-11-08 21:49:02 +07:00
|
|
|
bool combination_mode; /* gen 2/4 only */
|
|
|
|
bool active_low_pwm;
|
2016-09-19 17:35:25 +07:00
|
|
|
bool alternate_pwm_increment; /* lpt+ */
|
2015-06-26 16:02:10 +07:00
|
|
|
|
|
|
|
/* PWM chip */
|
2015-10-01 00:04:57 +07:00
|
|
|
bool util_pin_active_low; /* bxt+ */
|
|
|
|
u8 controller; /* bxt+ only */
|
2015-06-26 16:02:10 +07:00
|
|
|
struct pwm_device *pwm;
|
|
|
|
|
2013-11-08 21:48:54 +07:00
|
|
|
struct backlight_device *device;
|
2014-08-13 16:10:12 +07:00
|
|
|
|
2015-09-14 18:03:48 +07:00
|
|
|
/* Connector and platform specific backlight functions */
|
|
|
|
int (*setup)(struct intel_connector *connector, enum pipe pipe);
|
2019-01-18 19:01:25 +07:00
|
|
|
u32 (*get)(struct intel_connector *connector);
|
|
|
|
void (*set)(const struct drm_connector_state *conn_state, u32 level);
|
2017-06-12 17:21:15 +07:00
|
|
|
void (*disable)(const struct drm_connector_state *conn_state);
|
|
|
|
void (*enable)(const struct intel_crtc_state *crtc_state,
|
|
|
|
const struct drm_connector_state *conn_state);
|
2019-01-18 19:01:25 +07:00
|
|
|
u32 (*hz_to_pwm)(struct intel_connector *connector, u32 hz);
|
2015-09-14 18:03:48 +07:00
|
|
|
void (*power)(struct intel_connector *, bool enable);
|
|
|
|
} backlight;
|
2012-10-19 18:51:49 +07:00
|
|
|
};
|
|
|
|
|
2018-07-05 23:43:53 +07:00
|
|
|
struct intel_digital_port;
|
|
|
|
|
2019-02-17 00:36:57 +07:00
|
|
|
enum check_link_response {
|
|
|
|
HDCP_LINK_PROTECTED = 0,
|
|
|
|
HDCP_TOPOLOGY_CHANGE,
|
|
|
|
HDCP_LINK_INTEGRITY_FAILURE,
|
|
|
|
HDCP_REAUTH_REQUEST
|
|
|
|
};
|
|
|
|
|
2018-01-09 02:55:39 +07:00
|
|
|
/*
|
|
|
|
* This structure serves as a translation layer between the generic HDCP code
|
|
|
|
* and the bus-specific code. What that means is that HDCP over HDMI differs
|
|
|
|
* from HDCP over DP, so to account for these differences, we need to
|
|
|
|
* communicate with the receiver through this shim.
|
|
|
|
*
|
|
|
|
* For completeness, the 2 buses differ in the following ways:
|
|
|
|
* - DP AUX vs. DDC
|
|
|
|
* HDCP registers on the receiver are set via DP AUX for DP, and
|
|
|
|
* they are set via DDC for HDMI.
|
|
|
|
* - Receiver register offsets
|
|
|
|
* The offsets of the registers are different for DP vs. HDMI
|
|
|
|
* - Receiver register masks/offsets
|
|
|
|
* For instance, the ready bit for the KSV fifo is in a different
|
|
|
|
* place on DP vs HDMI
|
|
|
|
* - Receiver register names
|
|
|
|
* Seriously. In the DP spec, the 16-bit register containing
|
|
|
|
* downstream information is called BINFO, on HDMI it's called
|
|
|
|
* BSTATUS. To confuse matters further, DP has a BSTATUS register
|
|
|
|
* with a completely different definition.
|
|
|
|
* - KSV FIFO
|
|
|
|
* On HDMI, the ksv fifo is read all at once, whereas on DP it must
|
|
|
|
* be read 3 keys at a time
|
|
|
|
* - Aksv output
|
|
|
|
* Since Aksv is hidden in hardware, there's different procedures
|
|
|
|
* to send it over DP AUX vs DDC
|
|
|
|
*/
|
|
|
|
struct intel_hdcp_shim {
|
|
|
|
/* Outputs the transmitter's An and Aksv values to the receiver. */
|
|
|
|
int (*write_an_aksv)(struct intel_digital_port *intel_dig_port, u8 *an);
|
|
|
|
|
|
|
|
/* Reads the receiver's key selection vector */
|
|
|
|
int (*read_bksv)(struct intel_digital_port *intel_dig_port, u8 *bksv);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Reads BINFO from DP receivers and BSTATUS from HDMI receivers. The
|
|
|
|
* definitions are the same in the respective specs, but the names are
|
|
|
|
* different. Call it BSTATUS since that's the name the HDMI spec
|
|
|
|
* uses and it was there first.
|
|
|
|
*/
|
|
|
|
int (*read_bstatus)(struct intel_digital_port *intel_dig_port,
|
|
|
|
u8 *bstatus);
|
|
|
|
|
|
|
|
/* Determines whether a repeater is present downstream */
|
|
|
|
int (*repeater_present)(struct intel_digital_port *intel_dig_port,
|
|
|
|
bool *repeater_present);
|
|
|
|
|
|
|
|
/* Reads the receiver's Ri' value */
|
|
|
|
int (*read_ri_prime)(struct intel_digital_port *intel_dig_port, u8 *ri);
|
|
|
|
|
|
|
|
/* Determines if the receiver's KSV FIFO is ready for consumption */
|
|
|
|
int (*read_ksv_ready)(struct intel_digital_port *intel_dig_port,
|
|
|
|
bool *ksv_ready);
|
|
|
|
|
|
|
|
/* Reads the ksv fifo for num_downstream devices */
|
|
|
|
int (*read_ksv_fifo)(struct intel_digital_port *intel_dig_port,
|
|
|
|
int num_downstream, u8 *ksv_fifo);
|
|
|
|
|
|
|
|
/* Reads a 32-bit part of V' from the receiver */
|
|
|
|
int (*read_v_prime_part)(struct intel_digital_port *intel_dig_port,
|
|
|
|
int i, u32 *part);
|
|
|
|
|
|
|
|
/* Enables HDCP signalling on the port */
|
|
|
|
int (*toggle_signalling)(struct intel_digital_port *intel_dig_port,
|
|
|
|
bool enable);
|
|
|
|
|
|
|
|
/* Ensures the link is still protected */
|
|
|
|
bool (*check_link)(struct intel_digital_port *intel_dig_port);
|
2018-02-03 05:09:08 +07:00
|
|
|
|
|
|
|
/* Detects panel's hdcp capability. This is optional for HDMI. */
|
|
|
|
int (*hdcp_capable)(struct intel_digital_port *intel_dig_port,
|
|
|
|
bool *hdcp_capable);
|
2019-02-17 00:36:51 +07:00
|
|
|
|
|
|
|
/* HDCP adaptation(DP/HDMI) required on the port */
|
|
|
|
enum hdcp_wired_protocol protocol;
|
2019-02-17 00:36:53 +07:00
|
|
|
|
|
|
|
/* Detects whether sink is HDCP2.2 capable */
|
|
|
|
int (*hdcp_2_2_capable)(struct intel_digital_port *intel_dig_port,
|
|
|
|
bool *capable);
|
2019-02-17 00:36:54 +07:00
|
|
|
|
|
|
|
/* Write HDCP2.2 messages */
|
|
|
|
int (*write_2_2_msg)(struct intel_digital_port *intel_dig_port,
|
|
|
|
void *buf, size_t size);
|
|
|
|
|
|
|
|
/* Read HDCP2.2 messages */
|
|
|
|
int (*read_2_2_msg)(struct intel_digital_port *intel_dig_port,
|
|
|
|
u8 msg_id, void *buf, size_t size);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Implementation of DP HDCP2.2 Errata for the communication of stream
|
|
|
|
* type to Receivers. In DP HDCP2.2 Stream type is one of the input to
|
|
|
|
* the HDCP2.2 Cipher for En/De-Cryption. Not applicable for HDMI.
|
|
|
|
*/
|
|
|
|
int (*config_stream_type)(struct intel_digital_port *intel_dig_port,
|
|
|
|
bool is_repeater, u8 type);
|
2019-02-17 00:36:57 +07:00
|
|
|
|
|
|
|
/* HDCP2.2 Link Integrity Check */
|
|
|
|
int (*check_2_2_link)(struct intel_digital_port *intel_dig_port);
|
2018-01-09 02:55:39 +07:00
|
|
|
};
|
|
|
|
|
2018-10-29 16:45:46 +07:00
|
|
|
struct intel_hdcp {
|
|
|
|
const struct intel_hdcp_shim *shim;
|
|
|
|
/* Mutex for hdcp state of the connector */
|
|
|
|
struct mutex mutex;
|
|
|
|
u64 value;
|
|
|
|
struct delayed_work check_work;
|
|
|
|
struct work_struct prop_work;
|
2019-02-17 00:36:50 +07:00
|
|
|
|
2019-02-17 00:36:52 +07:00
|
|
|
/* HDCP1.4 Encryption status */
|
|
|
|
bool hdcp_encrypted;
|
|
|
|
|
2019-02-17 00:36:50 +07:00
|
|
|
/* HDCP2.2 related definitions */
|
|
|
|
/* Flag indicates whether this connector supports HDCP2.2 or not. */
|
|
|
|
bool hdcp2_supported;
|
|
|
|
|
2019-02-17 00:36:53 +07:00
|
|
|
/* HDCP2.2 Encryption status */
|
|
|
|
bool hdcp2_encrypted;
|
|
|
|
|
2019-02-17 00:36:50 +07:00
|
|
|
/*
|
|
|
|
* Content Stream Type defined by content owner. TYPE0(0x0) content can
|
|
|
|
* flow in the link protected by HDCP2.2 or HDCP1.4, where as TYPE1(0x1)
|
|
|
|
* content can flow only through a link protected by HDCP2.2.
|
|
|
|
*/
|
|
|
|
u8 content_type;
|
2019-02-17 00:36:51 +07:00
|
|
|
struct hdcp_port_data port_data;
|
2019-02-17 00:36:54 +07:00
|
|
|
|
|
|
|
bool is_paired;
|
|
|
|
bool is_repeater;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Count of ReceiverID_List received. Initialized to 0 at AKE_INIT.
|
|
|
|
* Incremented after processing the RepeaterAuth_Send_ReceiverID_List.
|
|
|
|
* When it rolls over re-auth has to be triggered.
|
|
|
|
*/
|
|
|
|
u32 seq_num_v;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Count of RepeaterAuth_Stream_Manage msg propagated.
|
|
|
|
* Initialized to 0 on AKE_INIT. Incremented after every successful
|
|
|
|
* transmission of RepeaterAuth_Stream_Manage message. When it rolls
|
|
|
|
* over re-Auth has to be triggered.
|
|
|
|
*/
|
|
|
|
u32 seq_num_m;
|
2019-02-17 00:37:02 +07:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Work queue to signal the CP_IRQ. Used for the waiters to read the
|
|
|
|
* available information from HDCP DP sink.
|
|
|
|
*/
|
|
|
|
wait_queue_head_t cp_irq_queue;
|
|
|
|
atomic_t cp_irq_count;
|
|
|
|
int cp_irq_count_cached;
|
2018-10-29 16:45:46 +07:00
|
|
|
};
|
|
|
|
|
2010-03-30 13:39:28 +07:00
|
|
|
struct intel_connector {
|
|
|
|
struct drm_connector base;
|
drm/i915: stage modeset output changes
This is the core of the new modeset logic.
The current code which is based upon the crtc helper code first
updates all the link of the new display pipeline and then calls the
lower-level set_mode function to execute the required callbacks to get
there. The issue with this approach is that for disabling we need to
know the _current_ display pipe state, not the new one.
Hence we need to stage the new state of the display pipe and only
update it once we have disabled the current configuration and before we
start to update the hw registers with the new configuration.
This patch here just prepares the ground by switching the new output
state computation to these staging pointers. To make it clearer,
rename the old update_output_state function to stage_output_state.
A few peculiarities:
- We're also calling the set_mode function at various places to update
properties. Hence after a successfule modeset we need to stage the
current configuration (for otherwise we might fall back again). This
happens automatically because as part of the (successful) modeset we
need to copy the staged state to the real one. But for the hw
readout code we need to make sure that this happens, too.
- Teach the new staged output state computation code the required
smarts to handle the disabling of outputs. The current code handles
this in a special case, but to better handle global modeset changes
covering more than one crtc, we want to do this all in the same
low-level modeset code.
- The actual modeset code is still a bit ugly and wants to know the new
crtc->enabled state a bit early. Follow-on patches will clean that
up, for now we have to apply the staged output configuration early,
outside of the set_mode functions.
- Improve/add comments in stage_output_state.
Essentially all that is left to do now is move the disabling code into
set_mode and then move the staged state update code also into
set_mode, at the right place between disabling things and calling the
mode_set callbacks for the new configuration.
v2: Disabling a crtc works by passing in a NULL mode or fb, userspace
doesn't hand in the list of connectors. We therefore need to detect
this case manually and tear down all the output links.
v3: Properly update the output staging pointers after having read out
the hw state.
v4: Simplify the code, add more DRM_DEBUG_KMS output and check a few
assumptions with WARN_ON. Essentially all things that I've noticed
while debugging issues in other places of the code.
v4: Correctly disable the old set of connectors when enabling an
already enabled crtc on a new set of crtc. Reported by Paulo Zanoni.
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-07-06 03:34:27 +07:00
|
|
|
/*
|
|
|
|
* The fixed encoder this connector is connected to.
|
|
|
|
*/
|
2010-09-09 22:20:55 +07:00
|
|
|
struct intel_encoder *encoder;
|
drm/i915: stage modeset output changes
This is the core of the new modeset logic.
The current code which is based upon the crtc helper code first
updates all the link of the new display pipeline and then calls the
lower-level set_mode function to execute the required callbacks to get
there. The issue with this approach is that for disabling we need to
know the _current_ display pipe state, not the new one.
Hence we need to stage the new state of the display pipe and only
update it once we have disabled the current configuration and before we
start to update the hw registers with the new configuration.
This patch here just prepares the ground by switching the new output
state computation to these staging pointers. To make it clearer,
rename the old update_output_state function to stage_output_state.
A few peculiarities:
- We're also calling the set_mode function at various places to update
properties. Hence after a successfule modeset we need to stage the
current configuration (for otherwise we might fall back again). This
happens automatically because as part of the (successful) modeset we
need to copy the staged state to the real one. But for the hw
readout code we need to make sure that this happens, too.
- Teach the new staged output state computation code the required
smarts to handle the disabling of outputs. The current code handles
this in a special case, but to better handle global modeset changes
covering more than one crtc, we want to do this all in the same
low-level modeset code.
- The actual modeset code is still a bit ugly and wants to know the new
crtc->enabled state a bit early. Follow-on patches will clean that
up, for now we have to apply the staged output configuration early,
outside of the set_mode functions.
- Improve/add comments in stage_output_state.
Essentially all that is left to do now is move the disabling code into
set_mode and then move the staged state update code also into
set_mode, at the right place between disabling things and calling the
mode_set callbacks for the new configuration.
v2: Disabling a crtc works by passing in a NULL mode or fb, userspace
doesn't hand in the list of connectors. We therefore need to detect
this case manually and tear down all the output links.
v3: Properly update the output staging pointers after having read out
the hw state.
v4: Simplify the code, add more DRM_DEBUG_KMS output and check a few
assumptions with WARN_ON. Essentially all things that I've noticed
while debugging issues in other places of the code.
v4: Correctly disable the old set of connectors when enabling an
already enabled crtc on a new set of crtc. Reported by Paulo Zanoni.
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-07-06 03:34:27 +07:00
|
|
|
|
drm/i915: make i915 the source of acpi device ids for _DOD
The graphics driver is supposed to define the DIDL, which are used for
_DOD, not the BIOS. Restore that behaviour.
This is basically a revert of
commit 3143751ff51a163b77f7efd389043e038f3e008e
Author: Zhang Rui <rui.zhang@intel.com>
Date: Mon Mar 29 15:12:16 2010 +0800
drm/i915: set DIDL using the ACPI video output device _ADR method return.
which went out of its way to cater to a specific BIOS, setting up DIDL
based on _ADR method. Perhaps that approach worked on that specific
machine, but on the machines I checked the _ADR method invents the
device identifiers out of thin air if DIDL has not been set. The source
for _ADR is also supposed to be the DIDL set by the driver, not the
other way around.
With this, we'll also limit the number of outputs to what the driver
actually has.
A side effect of this change is that the DIDL, and by proxy CADL, will
be initialized in the order of the connector list. That, in turn, has
internal panels in front, ensuring they're included in the DIDL and CADL
lists. Hopefully this ensures the BIOS does not block backlight hotkey
events, thinking the internal panel is off.
v2: do not set ACPI_DEVICE_ID_SCHEME in the device id (Peter Wu)
v3: Rebase
Cc: Peter Wu <peter@lekensteyn.nl>
Cc: Rainer Koenig <Rainer.Koenig@ts.fujitsu.com>
Cc: Jan-Marek Glogowski <glogow@fbihome.de>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Marcos Paulo de Souza <marcos.souza.org@gmail.com>
Cc: Paolo Stivanin <paolostivanin@fastmail.fm>
Tested-by: Rainer Koenig <Rainer.Koenig@ts.fujitsu.com>
Tested-by: Paolo Stivanin <paolostivanin@fastmail.fm>
Tested-by: Marcos Paulo de Souza <marcos.souza.org@gmail.com>
Reviewed-and-tested-by: Peter Wu <peter@lekensteyn.nl>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/9660d29cf310c17bbf4d58c0e09d5b047446e2d5.1479295490.git.jani.nikula@intel.com
2016-11-16 18:29:56 +07:00
|
|
|
/* ACPI device id for ACPI and driver cooperation */
|
|
|
|
u32 acpi_device_id;
|
|
|
|
|
2012-07-02 18:10:34 +07:00
|
|
|
/* Reads out the current hw, returning true if the connector is enabled
|
|
|
|
* and active (i.e. dpms ON state). */
|
|
|
|
bool (*get_hw_state)(struct intel_connector *);
|
2012-10-19 18:51:49 +07:00
|
|
|
|
|
|
|
/* Panel info for eDP and LVDS */
|
|
|
|
struct intel_panel panel;
|
2012-10-19 18:51:52 +07:00
|
|
|
|
|
|
|
/* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
|
|
|
|
struct edid *edid;
|
2014-09-03 02:04:00 +07:00
|
|
|
struct edid *detect_edid;
|
2013-04-16 18:36:55 +07:00
|
|
|
|
|
|
|
/* since POLL and HPD connectors may use the same HPD line keep the native
|
|
|
|
state of connector->polled in case hotplug storm detection changes it */
|
|
|
|
u8 polled;
|
2014-05-02 11:02:48 +07:00
|
|
|
|
|
|
|
void *port; /* store this opaque as its illegal to dereference it */
|
|
|
|
|
|
|
|
struct intel_dp *mst_port;
|
2017-04-06 20:44:19 +07:00
|
|
|
|
|
|
|
/* Work struct to schedule a uevent on link train failure */
|
|
|
|
struct work_struct modeset_retry_work;
|
2018-01-09 02:55:39 +07:00
|
|
|
|
2018-10-29 16:45:46 +07:00
|
|
|
struct intel_hdcp hdcp;
|
2010-03-30 13:39:28 +07:00
|
|
|
};
|
|
|
|
|
2017-05-01 20:37:57 +07:00
|
|
|
struct intel_digital_connector_state {
|
|
|
|
struct drm_connector_state base;
|
|
|
|
|
|
|
|
enum hdmi_force_audio force_audio;
|
|
|
|
int broadcast_rgb;
|
|
|
|
};
|
|
|
|
|
|
|
|
#define to_intel_digital_connector_state(x) container_of(x, struct intel_digital_connector_state, base)
|
|
|
|
|
2016-05-04 16:11:57 +07:00
|
|
|
struct dpll {
|
2013-04-19 18:36:51 +07:00
|
|
|
/* given values */
|
|
|
|
int n;
|
|
|
|
int m1, m2;
|
|
|
|
int p1, p2;
|
|
|
|
/* derived values */
|
|
|
|
int dot;
|
|
|
|
int vco;
|
|
|
|
int m;
|
|
|
|
int p;
|
2016-05-04 16:11:57 +07:00
|
|
|
};
|
2013-04-19 18:36:51 +07:00
|
|
|
|
2015-06-04 15:21:28 +07:00
|
|
|
struct intel_atomic_state {
|
|
|
|
struct drm_atomic_state base;
|
|
|
|
|
2017-01-21 01:21:59 +07:00
|
|
|
struct {
|
|
|
|
/*
|
|
|
|
* Logical state of cdclk (used for all scaling, watermark,
|
|
|
|
* etc. calculations and checks). This is computed as if all
|
|
|
|
* enabled crtcs were active.
|
|
|
|
*/
|
|
|
|
struct intel_cdclk_state logical;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Actual state of cdclk, can be different from the logical
|
|
|
|
* state only when all crtc's are DPMS off.
|
|
|
|
*/
|
|
|
|
struct intel_cdclk_state actual;
|
2019-03-20 20:54:36 +07:00
|
|
|
|
|
|
|
int force_min_cdclk;
|
|
|
|
bool force_min_cdclk_changed;
|
2019-03-27 17:13:21 +07:00
|
|
|
/* pipe to which cd2x update is synchronized */
|
|
|
|
enum pipe pipe;
|
2017-01-21 01:21:59 +07:00
|
|
|
} cdclk;
|
2015-12-03 20:31:06 +07:00
|
|
|
|
2015-12-10 18:33:57 +07:00
|
|
|
bool dpll_set, modeset;
|
|
|
|
|
2016-05-12 21:06:00 +07:00
|
|
|
/*
|
|
|
|
* Does this transaction change the pipes that are active? This mask
|
|
|
|
* tracks which CRTC's have changed their active state at the end of
|
|
|
|
* the transaction (not counting the temporary disable during modesets).
|
|
|
|
* This mask should only be non-zero when intel_state->modeset is true,
|
|
|
|
* but the converse is not necessarily true; simply changing a mode may
|
|
|
|
* not flip the final active status of any CRTC's
|
|
|
|
*/
|
|
|
|
unsigned int active_pipe_changes;
|
|
|
|
|
2015-12-10 18:33:57 +07:00
|
|
|
unsigned int active_crtcs;
|
2017-08-31 01:57:03 +07:00
|
|
|
/* minimum acceptable cdclk for each pipe */
|
|
|
|
int min_cdclk[I915_MAX_PIPES];
|
2017-10-24 16:52:14 +07:00
|
|
|
/* minimum acceptable voltage level for each pipe */
|
|
|
|
u8 min_voltage_level[I915_MAX_PIPES];
|
2015-12-10 18:33:57 +07:00
|
|
|
|
2016-12-29 22:22:09 +07:00
|
|
|
struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS];
|
drm/i915: Add two-stage ILK-style watermark programming (v11)
In addition to calculating final watermarks, let's also pre-calculate a
set of intermediate watermark values at atomic check time. These
intermediate watermarks are a combination of the watermarks for the old
state and the new state; they should satisfy the requirements of both
states which means they can be programmed immediately when we commit the
atomic state (without waiting for a vblank). Once the vblank does
happen, we can then re-program watermarks to the more optimal final
value.
v2: Significant rebasing/rewriting.
v3:
- Move 'need_postvbl_update' flag to CRTC state (Daniel)
- Don't forget to check intermediate watermark values for validity
(Maarten)
- Don't due async watermark optimization; just do it at the end of the
atomic transaction, after waiting for vblanks. We do want it to be
async eventually, but adding that now will cause more trouble for
Maarten's in-progress work. (Maarten)
- Don't allocate space in crtc_state for intermediate watermarks on
platforms that don't need it (gen9+).
- Move WaCxSRDisabledForSpriteScaling:ivb into intel_begin_crtc_commit
now that ilk_update_wm is gone.
v4:
- Add a wm_mutex to cover updates to intel_crtc->active and the
need_postvbl_update flag. Since we don't have async yet it isn't
terribly important yet, but might as well add it now.
- Change interface to program watermarks. Platforms will now expose
.initial_watermarks() and .optimize_watermarks() functions to do
watermark programming. These should lock wm_mutex, copy the
appropriate state values into intel_crtc->active, and then call
the internal program watermarks function.
v5:
- Skip intermediate watermark calculation/check during initial hardware
readout since we don't trust the existing HW values (and don't have
valid values of our own yet).
- Don't try to call .optimize_watermarks() on platforms that don't have
atomic watermarks yet. (Maarten)
v6:
- Rebase
v7:
- Further rebase
v8:
- A few minor indentation and line length fixes
v9:
- Yet another rebase since Maarten's patches reworked a bunch of the
code (wm_pre, wm_post, etc.) that this was previously based on.
v10:
- Move wm_mutex to dev_priv to protect against racing commits against
disjoint CRTC sets. (Maarten)
- Drop unnecessary clearing of cstate->wm.need_postvbl_update (Maarten)
v11:
- Now that we've moved to atomic watermark updates, make sure we call
the proper function to program watermarks in
{ironlake,haswell}_crtc_enable(); the failure to do so on the
previous patch iteration led to us not actually programming the
watermarks before turning on the CRTC, which was the cause of the
underruns that the CI system was seeing.
- Fix inverted logic for determining when to optimize watermarks. We
were needlessly optimizing when the intermediate/optimal values were
the same (harmless), but not actually optimizing when they differed
(also harmless, but wasteful from a power/bandwidth perspective).
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1456276813-5689-1-git-send-email-matthew.d.roper@intel.com
2016-02-24 08:20:13 +07:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Current watermarks can't be trusted during hardware readout, so
|
|
|
|
* don't bother calculating intermediate watermarks.
|
|
|
|
*/
|
|
|
|
bool skip_intermediate_wm;
|
2016-05-12 21:06:03 +07:00
|
|
|
|
drm/i915: Interactive RPS mode
RPS provides a feedback loop where we use the load during the previous
evaluation interval to decide whether to up or down clock the GPU
frequency. Our responsiveness is split into 3 regimes, a high and low
plateau with the intent to keep the gpu clocked high to cover occasional
stalls under high load, and low despite occasional glitches under steady
low load, and inbetween. However, we run into situations like kodi where
we want to stay at low power (video decoding is done efficiently
inside the fixed function HW and doesn't need high clocks even for high
bitrate streams), but just occasionally the pipeline is more complex
than a video decode and we need a smidgen of extra GPU power to present
on time. In the high power regime, we sample at sub frame intervals with
a bias to upclocking, and conversely at low power we sample over a few
frames worth to provide what we consider to be the right levels of
responsiveness respectively. At low power, we more or less expect to be
kicked out to high power at the start of a busy sequence by waitboosting.
Prior to commit e9af4ea2b9e7 ("drm/i915: Avoid waitboosting on the active
request") whenever we missed the frame or stalled, we would immediate go
full throttle and upclock the GPU to max. But in commit e9af4ea2b9e7, we
relaxed the waitboosting to only apply if the pipeline was deep to avoid
over-committing resources for a near miss. Sadly though, a near miss is
still a miss, and perceptible as jitter in the frame delivery.
To try and prevent the near miss before having to resort to boosting
after the fact, we use the pageflip queue as an indication that we are
in an "interactive" regime and so should sample the load more frequently
to provide power before the frame misses it vblank. This will make us
more favorable to providing a small power increase (one or two bins) as
required rather than going all the way to maximum and then having to
work back down again. (We still keep the waitboosting mechanism around
just in case a dramatic change in system load requires urgent uplocking,
faster than we can provide in a few evaluation intervals.)
v2: Reduce rps_set_interactive to a boolean parameter to avoid the
confusion of what if they wanted a new power mode after pinning to a
different mode (which to choose?)
v3: Only reprogram RPS while the GT is awake, it will be set when we
wake the GT, and while off warns about being used outside of rpm.
v4: Fix deferred application of interactive mode
v5: s/state/interactive/
v6: Group the mutex with its principle in a substruct
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107111
Fixes: e9af4ea2b9e7 ("drm/i915: Avoid waitboosting on the active request")
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Radoslaw Szwichtenberg <radoslaw.szwichtenberg@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180731132629.3381-1-chris@chris-wilson.co.uk
2018-07-31 20:26:29 +07:00
|
|
|
bool rps_interactive;
|
|
|
|
|
2016-05-12 21:06:03 +07:00
|
|
|
/* Gen9+ only */
|
2018-04-09 10:41:00 +07:00
|
|
|
struct skl_ddb_values wm_results;
|
2016-10-28 19:58:45 +07:00
|
|
|
|
|
|
|
struct i915_sw_fence commit_ready;
|
2017-01-24 04:29:39 +07:00
|
|
|
|
|
|
|
struct llist_node freed;
|
2015-06-04 15:21:28 +07:00
|
|
|
};
|
|
|
|
|
2014-09-06 03:04:46 +07:00
|
|
|
struct intel_plane_state {
|
2014-12-02 06:40:13 +07:00
|
|
|
struct drm_plane_state base;
|
2018-09-07 22:24:06 +07:00
|
|
|
struct i915_ggtt_view view;
|
2017-01-16 22:21:27 +07:00
|
|
|
struct i915_vma *vma;
|
2018-02-20 20:42:06 +07:00
|
|
|
unsigned long flags;
|
|
|
|
#define PLANE_HAS_FENCE BIT(0)
|
2014-12-24 22:59:06 +07:00
|
|
|
|
2016-01-28 21:53:54 +07:00
|
|
|
struct {
|
|
|
|
u32 offset;
|
2018-09-11 22:01:39 +07:00
|
|
|
/*
|
|
|
|
* Plane stride in:
|
|
|
|
* bytes for 0/180 degree rotation
|
|
|
|
* pixels for 90/270 degree rotation
|
|
|
|
*/
|
|
|
|
u32 stride;
|
2016-01-28 21:53:54 +07:00
|
|
|
int x, y;
|
2018-09-07 22:24:04 +07:00
|
|
|
} color_plane[2];
|
2016-01-28 21:53:54 +07:00
|
|
|
|
2017-03-24 02:27:09 +07:00
|
|
|
/* plane control register */
|
|
|
|
u32 ctl;
|
|
|
|
|
2017-11-14 01:11:28 +07:00
|
|
|
/* plane color control register */
|
|
|
|
u32 color_ctl;
|
|
|
|
|
2015-04-08 05:28:36 +07:00
|
|
|
/*
|
|
|
|
* scaler_id
|
|
|
|
* = -1 : not using a scaler
|
|
|
|
* >= 0 : using a scalers
|
|
|
|
*
|
|
|
|
* plane requiring a scaler:
|
|
|
|
* - During check_plane, its bit is set in
|
|
|
|
* crtc_state->scaler_state.scaler_users by calling helper function
|
2015-06-22 14:50:32 +07:00
|
|
|
* update_scaler_plane.
|
2015-04-08 05:28:36 +07:00
|
|
|
* - scaler_id indicates the scaler it got assigned.
|
|
|
|
*
|
|
|
|
* plane doesn't require a scaler:
|
|
|
|
* - this can happen when scaling is no more required or plane simply
|
|
|
|
* got disabled.
|
|
|
|
* - During check_plane, corresponding bit is reset in
|
|
|
|
* crtc_state->scaler_state.scaler_users by calling helper function
|
2015-06-22 14:50:32 +07:00
|
|
|
* update_scaler_plane.
|
2015-04-08 05:28:36 +07:00
|
|
|
*/
|
|
|
|
int scaler_id;
|
2015-06-15 17:33:54 +07:00
|
|
|
|
drm/i915/gen11: Link nv12 Y and UV planes in the atomic state, v5.
To make NV12 working on icl, we need to update 2 planes simultaneously.
I've chosen to do this in the CRTC step after plane validation is done,
so we know what planes are (in)visible. The linked Y plane will get
updated in intel_plane_update_planes_on_crtc(), by the call to
update_slave, which gets the master's plane_state as argument.
The link requires both planes for atomic_update to work,
so make sure skl_ddb_add_affected_planes() adds both states.
Changes since v1:
- Introduce icl_is_nv12_y_plane(), instead of hardcoding sprite numbers.
- Put all the state updating login in intel_plane_atomic_check_with_state().
- Clean up changes in intel_plane_atomic_check().
Changes since v2:
- Fix intel_atomic_get_old_plane_state() to actually return old state.
- Move visibility changes to preparation patch.
- Only try to find a Y plane on gen11, earlier platforms only require
a single plane.
Changes since v3:
- Fix checkpatch warning about to_intel_crtc() usage.
- Add affected planes from icl_add_linked_planes() before check_planes(),
it's a cleaner way to do this. (Ville)
Changes since v4:
- Clear plane links in icl_check_nv12_planes() for clarity.
- Only pass crtc_state to icl_check_nv12_planes().
- Use for_each_new_intel_plane_in_state() in icl_check_nv12_planes.
- Rename aux to linked. (Ville)
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181022135152.15324-1-maarten.lankhorst@linux.intel.com
[mlankhorst: Change bool slave to u32, to satisfy checkpatch]
[mlankhorst: Add WARN_ON's based on Ville's suggestion]
2018-10-22 20:51:52 +07:00
|
|
|
/*
|
|
|
|
* linked_plane:
|
|
|
|
*
|
|
|
|
* ICL planar formats require 2 planes that are updated as pairs.
|
|
|
|
* This member is used to make sure the other plane is also updated
|
|
|
|
* when required, and for update_slave() to find the correct
|
|
|
|
* plane_state to pass as argument.
|
|
|
|
*/
|
|
|
|
struct intel_plane *linked_plane;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* slave:
|
|
|
|
* If set don't update use the linked plane's state for updating
|
|
|
|
* this plane during atomic commit with the update_slave() callback.
|
|
|
|
*
|
|
|
|
* It's also used by the watermark code to ignore wm calculations on
|
|
|
|
* this plane. They're calculated by the linked plane's wm code.
|
|
|
|
*/
|
|
|
|
u32 slave;
|
|
|
|
|
2015-06-15 17:33:54 +07:00
|
|
|
struct drm_intel_sprite_colorkey ckey;
|
2014-09-06 03:04:46 +07:00
|
|
|
};
|
|
|
|
|
2015-01-20 19:51:52 +07:00
|
|
|
struct intel_initial_plane_config {
|
2015-02-06 00:22:18 +07:00
|
|
|
struct intel_framebuffer *fb;
|
2015-01-20 19:51:44 +07:00
|
|
|
unsigned int tiling;
|
2014-03-07 23:57:48 +07:00
|
|
|
int size;
|
|
|
|
u32 base;
|
2018-11-20 20:54:50 +07:00
|
|
|
u8 rotation;
|
2014-03-07 23:57:48 +07:00
|
|
|
};
|
|
|
|
|
2015-04-08 05:28:36 +07:00
|
|
|
struct intel_scaler {
|
|
|
|
int in_use;
|
2019-01-18 19:01:25 +07:00
|
|
|
u32 mode;
|
2015-04-08 05:28:36 +07:00
|
|
|
};
|
|
|
|
|
|
|
|
struct intel_crtc_scaler_state {
|
|
|
|
#define SKL_NUM_SCALERS 2
|
|
|
|
struct intel_scaler scalers[SKL_NUM_SCALERS];
|
|
|
|
|
|
|
|
/*
|
|
|
|
* scaler_users: keeps track of users requesting scalers on this crtc.
|
|
|
|
*
|
|
|
|
* If a bit is set, a user is using a scaler.
|
|
|
|
* Here user can be a plane or crtc as defined below:
|
|
|
|
* bits 0-30 - plane (bit position is index from drm_plane_index)
|
|
|
|
* bit 31 - crtc
|
|
|
|
*
|
|
|
|
* Instead of creating a new index to cover planes and crtc, using
|
|
|
|
* existing drm_plane_index for planes which is well less than 31
|
|
|
|
* planes and bit 31 for crtc. This should be fine to cover all
|
|
|
|
* our platforms.
|
|
|
|
*
|
|
|
|
* intel_atomic_setup_scalers will setup available scalers to users
|
|
|
|
* requesting scalers. It will gracefully fail if request exceeds
|
|
|
|
* avilability.
|
|
|
|
*/
|
|
|
|
#define SKL_CRTC_INDEX 31
|
|
|
|
unsigned scaler_users;
|
|
|
|
|
|
|
|
/* scaler used by crtc for panel fitting purpose */
|
|
|
|
int scaler_id;
|
|
|
|
};
|
|
|
|
|
2015-07-15 19:15:51 +07:00
|
|
|
/* drm_mode->private_flags */
|
2019-01-26 01:19:31 +07:00
|
|
|
#define I915_MODE_FLAG_INHERITED (1<<0)
|
2017-09-25 20:56:01 +07:00
|
|
|
/* Flag to get scanline using frame time stamps */
|
|
|
|
#define I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP (1<<1)
|
2019-01-26 01:19:31 +07:00
|
|
|
/* Flag to use the scanline counter instead of the pixel counter */
|
|
|
|
#define I915_MODE_FLAG_USE_SCANLINE_COUNTER (1<<2)
|
2015-07-15 19:15:51 +07:00
|
|
|
|
2015-09-25 05:53:15 +07:00
|
|
|
struct intel_pipe_wm {
|
|
|
|
struct intel_wm_level wm[5];
|
2019-01-18 19:01:25 +07:00
|
|
|
u32 linetime;
|
2015-09-25 05:53:15 +07:00
|
|
|
bool fbc_wm_enabled;
|
|
|
|
bool pipe_enabled;
|
|
|
|
bool sprites_enabled;
|
|
|
|
bool sprites_scaled;
|
|
|
|
};
|
|
|
|
|
2016-10-05 01:28:20 +07:00
|
|
|
struct skl_plane_wm {
|
2015-09-25 05:53:15 +07:00
|
|
|
struct skl_wm_level wm[8];
|
2018-04-09 10:41:04 +07:00
|
|
|
struct skl_wm_level uv_wm[8];
|
2015-09-25 05:53:15 +07:00
|
|
|
struct skl_wm_level trans_wm;
|
2018-04-09 10:41:01 +07:00
|
|
|
bool is_planar;
|
2016-10-05 01:28:20 +07:00
|
|
|
};
|
|
|
|
|
|
|
|
struct skl_pipe_wm {
|
|
|
|
struct skl_plane_wm planes[I915_MAX_PLANES];
|
2019-01-18 19:01:25 +07:00
|
|
|
u32 linetime;
|
2015-09-25 05:53:15 +07:00
|
|
|
};
|
|
|
|
|
2017-03-03 00:14:54 +07:00
|
|
|
enum vlv_wm_level {
|
|
|
|
VLV_WM_LEVEL_PM2,
|
|
|
|
VLV_WM_LEVEL_PM5,
|
|
|
|
VLV_WM_LEVEL_DDR_DVFS,
|
|
|
|
NUM_VLV_WM_LEVELS,
|
|
|
|
};
|
|
|
|
|
|
|
|
struct vlv_wm_state {
|
2017-04-22 01:14:21 +07:00
|
|
|
struct g4x_pipe_wm wm[NUM_VLV_WM_LEVELS];
|
|
|
|
struct g4x_sr_wm sr[NUM_VLV_WM_LEVELS];
|
2019-01-18 19:01:25 +07:00
|
|
|
u8 num_levels;
|
2017-03-03 00:14:54 +07:00
|
|
|
bool cxsr;
|
|
|
|
};
|
|
|
|
|
2017-03-03 00:14:55 +07:00
|
|
|
struct vlv_fifo_state {
|
|
|
|
u16 plane[I915_MAX_PLANES];
|
|
|
|
};
|
|
|
|
|
2017-04-22 01:14:29 +07:00
|
|
|
enum g4x_wm_level {
|
|
|
|
G4X_WM_LEVEL_NORMAL,
|
|
|
|
G4X_WM_LEVEL_SR,
|
|
|
|
G4X_WM_LEVEL_HPLL,
|
|
|
|
NUM_G4X_WM_LEVELS,
|
|
|
|
};
|
|
|
|
|
|
|
|
struct g4x_wm_state {
|
|
|
|
struct g4x_pipe_wm wm;
|
|
|
|
struct g4x_sr_wm sr;
|
|
|
|
struct g4x_sr_wm hpll;
|
|
|
|
bool cxsr;
|
|
|
|
bool hpll_en;
|
|
|
|
bool fbc_en;
|
|
|
|
};
|
|
|
|
|
2016-05-12 21:05:55 +07:00
|
|
|
struct intel_crtc_wm_state {
|
|
|
|
union {
|
|
|
|
struct {
|
|
|
|
/*
|
|
|
|
* Intermediate watermarks; these can be
|
|
|
|
* programmed immediately since they satisfy
|
|
|
|
* both the current configuration we're
|
|
|
|
* switching away from and the new
|
|
|
|
* configuration we're switching to.
|
|
|
|
*/
|
|
|
|
struct intel_pipe_wm intermediate;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Optimal watermarks, programmed post-vblank
|
|
|
|
* when this state is committed.
|
|
|
|
*/
|
|
|
|
struct intel_pipe_wm optimal;
|
|
|
|
} ilk;
|
|
|
|
|
|
|
|
struct {
|
|
|
|
/* gen9+ only needs 1-step wm programming */
|
|
|
|
struct skl_pipe_wm optimal;
|
2016-09-15 21:46:35 +07:00
|
|
|
struct skl_ddb_entry ddb;
|
2018-11-27 23:59:00 +07:00
|
|
|
struct skl_ddb_entry plane_ddb_y[I915_MAX_PLANES];
|
|
|
|
struct skl_ddb_entry plane_ddb_uv[I915_MAX_PLANES];
|
2016-05-12 21:05:55 +07:00
|
|
|
} skl;
|
2017-03-03 00:14:54 +07:00
|
|
|
|
|
|
|
struct {
|
2017-03-03 00:14:56 +07:00
|
|
|
/* "raw" watermarks (not inverted) */
|
2017-04-22 01:14:21 +07:00
|
|
|
struct g4x_pipe_wm raw[NUM_VLV_WM_LEVELS];
|
2017-03-03 00:14:59 +07:00
|
|
|
/* intermediate watermarks (inverted) */
|
|
|
|
struct vlv_wm_state intermediate;
|
2017-03-03 00:14:54 +07:00
|
|
|
/* optimal watermarks (inverted) */
|
|
|
|
struct vlv_wm_state optimal;
|
2017-03-03 00:14:55 +07:00
|
|
|
/* display FIFO split */
|
|
|
|
struct vlv_fifo_state fifo_state;
|
2017-03-03 00:14:54 +07:00
|
|
|
} vlv;
|
2017-04-22 01:14:29 +07:00
|
|
|
|
|
|
|
struct {
|
|
|
|
/* "raw" watermarks */
|
|
|
|
struct g4x_pipe_wm raw[NUM_G4X_WM_LEVELS];
|
|
|
|
/* intermediate watermarks */
|
|
|
|
struct g4x_wm_state intermediate;
|
|
|
|
/* optimal watermarks */
|
|
|
|
struct g4x_wm_state optimal;
|
|
|
|
} g4x;
|
2016-05-12 21:05:55 +07:00
|
|
|
};
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Platforms with two-step watermark programming will need to
|
|
|
|
* update watermark programming post-vblank to switch from the
|
|
|
|
* safe intermediate watermarks to the optimal final
|
|
|
|
* watermarks.
|
|
|
|
*/
|
|
|
|
bool need_postvbl_update;
|
|
|
|
};
|
|
|
|
|
2018-10-12 13:23:07 +07:00
|
|
|
enum intel_output_format {
|
|
|
|
INTEL_OUTPUT_FORMAT_INVALID,
|
|
|
|
INTEL_OUTPUT_FORMAT_RGB,
|
2018-10-12 13:23:08 +07:00
|
|
|
INTEL_OUTPUT_FORMAT_YCBCR420,
|
2018-10-12 13:23:09 +07:00
|
|
|
INTEL_OUTPUT_FORMAT_YCBCR444,
|
2018-10-12 13:23:07 +07:00
|
|
|
};
|
|
|
|
|
2015-01-15 19:55:21 +07:00
|
|
|
struct intel_crtc_state {
|
2015-01-15 19:55:22 +07:00
|
|
|
struct drm_crtc_state base;
|
|
|
|
|
2013-06-06 19:55:52 +07:00
|
|
|
/**
|
|
|
|
* quirks - bitfield with hw state readout quirks
|
|
|
|
*
|
|
|
|
* For various reasons the hw state readout code might not be able to
|
|
|
|
* completely faithfully read out the current state. These cases are
|
|
|
|
* tracked with quirk flags so that fastboot and state checker can act
|
|
|
|
* accordingly.
|
|
|
|
*/
|
2014-04-13 17:00:33 +07:00
|
|
|
#define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
|
2013-06-06 19:55:52 +07:00
|
|
|
unsigned long quirks;
|
|
|
|
|
2016-03-09 16:35:44 +07:00
|
|
|
unsigned fb_bits; /* framebuffers to flip */
|
2015-11-19 22:07:14 +07:00
|
|
|
bool update_pipe; /* can a fast modeset be performed? */
|
|
|
|
bool disable_cxsr;
|
2016-03-10 00:07:25 +07:00
|
|
|
bool update_wm_pre, update_wm_post; /* watermarks are updated */
|
2016-02-24 17:24:26 +07:00
|
|
|
bool fb_changed; /* fb on any of the planes is changed */
|
2017-03-03 00:14:58 +07:00
|
|
|
bool fifo_changed; /* FIFO split is changed */
|
2015-08-27 20:44:05 +07:00
|
|
|
|
2013-09-04 22:25:28 +07:00
|
|
|
/* Pipe source size (ie. panel fitter input size)
|
|
|
|
* All planes will be positioned inside this space,
|
|
|
|
* and get clipped at the edges. */
|
|
|
|
int pipe_src_w, pipe_src_h;
|
|
|
|
|
2017-01-27 02:50:31 +07:00
|
|
|
/*
|
|
|
|
* Pipe pixel rate, adjusted for
|
|
|
|
* panel fitter/pipe scaler downscaling.
|
|
|
|
*/
|
|
|
|
unsigned int pixel_rate;
|
|
|
|
|
2013-03-27 06:44:55 +07:00
|
|
|
/* Whether to set up the PCH/FDI. Note that we never allow sharing
|
|
|
|
* between pch encoders and cpu encoders. */
|
|
|
|
bool has_pch_encoder;
|
2013-03-27 06:44:56 +07:00
|
|
|
|
2014-11-06 05:26:08 +07:00
|
|
|
/* Are we sending infoframes on the attached port */
|
|
|
|
bool has_infoframe;
|
|
|
|
|
2013-04-18 01:15:07 +07:00
|
|
|
/* CPU Transcoder for the pipe. Currently this can only differ from the
|
2016-03-18 22:05:42 +07:00
|
|
|
* pipe on Haswell and later (where we have a special eDP transcoder)
|
|
|
|
* and Broxton (where we have special DSI transcoders). */
|
2013-04-18 01:15:07 +07:00
|
|
|
enum transcoder cpu_transcoder;
|
|
|
|
|
2013-03-27 06:44:56 +07:00
|
|
|
/*
|
|
|
|
* Use reduced/limited/broadcast rbg range, compressing from the full
|
|
|
|
* range fed into the crtcs.
|
|
|
|
*/
|
|
|
|
bool limited_color_range;
|
|
|
|
|
2016-06-23 01:57:01 +07:00
|
|
|
/* Bitmask of encoder types (enum intel_output_type)
|
|
|
|
* driven by the pipe.
|
|
|
|
*/
|
|
|
|
unsigned int output_types;
|
|
|
|
|
2014-04-25 04:54:47 +07:00
|
|
|
/* Whether we should send NULL infoframes. Required for audio. */
|
|
|
|
bool has_hdmi_sink;
|
|
|
|
|
2014-04-25 04:54:52 +07:00
|
|
|
/* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
|
|
|
|
* has_dp_encoder is set. */
|
|
|
|
bool has_audio;
|
|
|
|
|
2013-04-25 22:54:44 +07:00
|
|
|
/*
|
|
|
|
* Enable dithering, used when the selected pipe bpp doesn't match the
|
|
|
|
* plane bpp.
|
|
|
|
*/
|
2013-03-27 06:44:57 +07:00
|
|
|
bool dither;
|
2013-03-28 16:42:02 +07:00
|
|
|
|
2017-01-24 23:21:49 +07:00
|
|
|
/*
|
|
|
|
* Dither gets enabled for 18bpp which causes CRC mismatch errors for
|
|
|
|
* compliance video pattern tests.
|
|
|
|
* Disable dither only if it is a compliance test request for
|
|
|
|
* 18bpp.
|
|
|
|
*/
|
|
|
|
bool dither_force_disable;
|
|
|
|
|
2013-03-28 16:42:02 +07:00
|
|
|
/* Controls for the clock computation, to override various stages. */
|
|
|
|
bool clock_set;
|
|
|
|
|
2013-04-30 19:01:45 +07:00
|
|
|
/* SDVO TV has a bunch of special case. To make multifunction encoders
|
|
|
|
* work correctly, we need to track this at runtime.*/
|
|
|
|
bool sdvo_tv_clock;
|
|
|
|
|
drm/i915: implement fdi auto-dithering
So on a bunch of setups we only have 2 fdi lanes available, e.g. hsw
VGA or 3 pipes on ivb. And seemingly a lot of modes don't quite fit
into this, among them the default 1080p mode.
The solution is to dither down the pipe a bit so that everything fits,
which this patch implements.
But ports compute their state under the assumption that the bpp they
pick will be the one selected, e.g. the display port bw computations
won't work otherwise. Now we could adjust our code to again up-dither
to the computed DP link parameters, but that's pointless.
So instead when the pipe needs to adjust parameters we need to retry
the pipe_config computation at the encoder stage. Furthermore we need
to inform encoders that they should not increase bandwidth
requirements if possible. This is required for the hdmi code, which
prefers the pipe to up-dither to either of the two possible hdmi bpc
values.
LVDS has a similar requirement, although that's probably only
theoretical in nature: It's unlikely that we'll ever see an 8bpc
high-res lvds panel (which is required to hit the 2 fdi lane limit).
eDP is the only thing which could increase the pipe_bpp setting again,
even when in the retry-loop. This could hit the WARN. Two reasons for
not bothering:
- On many eDP panels we'll get a black screen if the bpp settings
don't match vbt. So failing the modeset is the right thing to do.
But since that also means it's the only way to light up the panel,
it should work. So we shouldn't be able to hit this WARN.
- There are still opens around the eDP panel handling, and maybe we
need additional tricks. Before that happens it's imo no use trying
to be too clever.
Worst case we just need to kill that WARN or maybe fail the compute
config stage if the eDP connector can't get the bpp setting it wants.
And since this can only happen with an fdi link in between and so for
pch eDP panels it's rather unlikely to blow up, if ever.
v2: Rebased on top of a bikeshed from Paulo.
v3: Improve commit message around eDP handling with the stuff
things with Imre.
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-02-21 06:00:16 +07:00
|
|
|
/*
|
|
|
|
* crtc bandwidth limit, don't increase pipe bpp or clock if not really
|
|
|
|
* required. This is set in the 2nd loop of calling encoder's
|
|
|
|
* ->compute_config if the first pick doesn't work out.
|
|
|
|
*/
|
|
|
|
bool bw_constrained;
|
|
|
|
|
2013-03-28 16:42:02 +07:00
|
|
|
/* Settings for the intel dpll used on pretty much everything but
|
|
|
|
* haswell. */
|
2013-04-19 18:36:51 +07:00
|
|
|
struct dpll dpll;
|
2013-03-28 16:42:02 +07:00
|
|
|
|
2016-03-08 22:46:18 +07:00
|
|
|
/* Selected dpll when shared or NULL. */
|
|
|
|
struct intel_shared_dpll *shared_dpll;
|
2013-06-08 04:10:32 +07:00
|
|
|
|
2013-06-05 18:34:20 +07:00
|
|
|
/* Actual register state of the dpll, for shared dpll cross-checking. */
|
|
|
|
struct intel_dpll_hw_state dpll_hw_state;
|
|
|
|
|
2016-04-13 02:14:35 +07:00
|
|
|
/* DSI PLL registers */
|
|
|
|
struct {
|
|
|
|
u32 ctrl, div;
|
|
|
|
} dsi_pll;
|
|
|
|
|
2013-03-27 06:44:57 +07:00
|
|
|
int pipe_bpp;
|
drm/i915: clear up the fdi/dp set_m_n confusion
There's a rather decent confusion going on around transcoder m_n
values. So let's clarify:
- All dp encoders need this, either on the pch transcoder if it's a
pch port, or on the cpu transcoder/pipe if it's a cpu port.
- fdi links need to have the right m_n values for the fdi link set in
the cpu transcoder.
To handle the pch vs transcoder stuff a bit better, extract transcoder
set_m_n helpers. To make them simpler, set intel_crtc->cpu_transcoder
als in ironlake_crtc_mode_set, so that gen5+ (where the cpu m_n
registers are all at the same offset) can use it.
Haswell modeset is decently confused about dp vs. edp vs. fdi. dp vs.
edp works exactly the same as dp (since there's no pch dp any more),
so use that as a check. And only set up the fdi m_n values if we
really have a pch encoder present (which means we have a VGA encoder).
On ilk+ we've called ironlake_set_m_n both for cpu_edp and for pch
encoders. Now that dp_set_m_n handles all dp links (thanks to the
pch encoder check), we can ditch the cpu_edp stuff from the
fdi_set_m_n function.
Since the dp_m_n values are not readily available, we need to
carefully coax the edp values out of the encoder. Hence we can't (yet)
kill this superflous complexity.
v2: Rebase on top of the ivb fdi B/C check patch - we need to properly
clear intel_crtc->fdi_lane, otherwise those checks will misfire.
v3: Rebased on top of a s/IS_HASWELL/HAS_DDI/ patch from Paulo Zanoni.
v4: Drop the addition of has_dp_encoder, it's in the wrong patch (Jesse).
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-04-03 04:38:10 +07:00
|
|
|
struct intel_link_m_n dp_m_n;
|
2013-06-01 22:16:21 +07:00
|
|
|
|
2014-04-05 13:43:28 +07:00
|
|
|
/* m2_n2 for eDP downclock */
|
|
|
|
struct intel_link_m_n dp_m2_n2;
|
2014-08-05 21:51:22 +07:00
|
|
|
bool has_drrs;
|
2014-04-05 13:43:28 +07:00
|
|
|
|
2017-10-12 20:02:01 +07:00
|
|
|
bool has_psr;
|
|
|
|
bool has_psr2;
|
|
|
|
|
2013-06-01 22:16:21 +07:00
|
|
|
/*
|
|
|
|
* Frequence the dpll for the port should run at. Differs from the
|
2013-09-07 03:28:59 +07:00
|
|
|
* adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
|
|
|
|
* already multiplied by pixel_multiplier.
|
2013-03-28 16:41:58 +07:00
|
|
|
*/
|
2013-06-01 22:16:21 +07:00
|
|
|
int port_clock;
|
|
|
|
|
2013-03-27 06:44:53 +07:00
|
|
|
/* Used by SDVO (and if we ever fix it, HDMI). */
|
|
|
|
unsigned pixel_multiplier;
|
2013-04-26 02:55:01 +07:00
|
|
|
|
2019-01-18 19:01:25 +07:00
|
|
|
u8 lane_count;
|
2015-07-06 20:39:15 +07:00
|
|
|
|
2016-06-13 20:44:35 +07:00
|
|
|
/*
|
|
|
|
* Used by platforms having DP/HDMI PHY with programmable lane
|
|
|
|
* latency optimization.
|
|
|
|
*/
|
2019-01-18 19:01:25 +07:00
|
|
|
u8 lane_lat_optim_mask;
|
2016-06-13 20:44:35 +07:00
|
|
|
|
2017-10-24 16:52:14 +07:00
|
|
|
/* minimum acceptable voltage level */
|
|
|
|
u8 min_voltage_level;
|
|
|
|
|
2013-04-26 02:55:01 +07:00
|
|
|
/* Panel fitter controls for gen2-gen4 + VLV */
|
2013-04-26 02:55:02 +07:00
|
|
|
struct {
|
|
|
|
u32 control;
|
|
|
|
u32 pgm_ratios;
|
2013-04-26 03:52:16 +07:00
|
|
|
u32 lvds_border_bits;
|
2013-04-26 02:55:02 +07:00
|
|
|
} gmch_pfit;
|
|
|
|
|
|
|
|
/* Panel fitter placement and size for Ironlake+ */
|
|
|
|
struct {
|
|
|
|
u32 pos;
|
|
|
|
u32 size;
|
2013-08-27 23:04:17 +07:00
|
|
|
bool enabled;
|
2014-05-29 19:10:22 +07:00
|
|
|
bool force_thru;
|
2013-04-26 02:55:02 +07:00
|
|
|
} pch_pfit;
|
2013-02-14 00:04:45 +07:00
|
|
|
|
2013-02-14 22:54:22 +07:00
|
|
|
/* FDI configuration, only valid if has_pch_encoder is set. */
|
2013-02-14 00:04:45 +07:00
|
|
|
int fdi_lanes;
|
2013-02-14 22:54:22 +07:00
|
|
|
struct intel_link_m_n fdi_m_n;
|
2013-06-01 02:33:22 +07:00
|
|
|
|
|
|
|
bool ips_enabled;
|
2019-03-08 07:00:46 +07:00
|
|
|
|
|
|
|
bool crc_enabled;
|
2013-09-04 22:30:02 +07:00
|
|
|
|
2016-01-19 20:35:50 +07:00
|
|
|
bool enable_fbc;
|
|
|
|
|
2013-09-04 22:30:02 +07:00
|
|
|
bool double_wide;
|
2014-05-02 11:02:48 +07:00
|
|
|
|
|
|
|
int pbn;
|
2015-04-08 05:28:36 +07:00
|
|
|
|
|
|
|
struct intel_crtc_scaler_state scaler_state;
|
2015-06-01 17:50:09 +07:00
|
|
|
|
|
|
|
/* w/a for waiting 2 vblanks during crtc enable */
|
|
|
|
enum pipe hsw_workaround_pipe;
|
2015-09-25 05:53:12 +07:00
|
|
|
|
|
|
|
/* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */
|
|
|
|
bool disable_lp_wm;
|
2015-09-25 05:53:15 +07:00
|
|
|
|
2016-05-12 21:05:55 +07:00
|
|
|
struct intel_crtc_wm_state wm;
|
2016-03-16 17:57:15 +07:00
|
|
|
|
2019-05-24 22:36:14 +07:00
|
|
|
u32 data_rate[I915_MAX_PLANES];
|
|
|
|
|
2016-03-16 17:57:15 +07:00
|
|
|
/* Gamma mode programmed on the pipe */
|
2019-01-18 19:01:25 +07:00
|
|
|
u32 gamma_mode;
|
2017-03-03 00:14:51 +07:00
|
|
|
|
2019-02-19 02:31:32 +07:00
|
|
|
union {
|
|
|
|
/* CSC mode programmed on the pipe */
|
|
|
|
u32 csc_mode;
|
|
|
|
|
|
|
|
/* CHV CGM mode */
|
|
|
|
u32 cgm_mode;
|
|
|
|
};
|
2019-02-11 20:50:24 +07:00
|
|
|
|
2017-03-03 00:14:51 +07:00
|
|
|
/* bitmask of visible planes (enum plane_id) */
|
|
|
|
u8 active_planes;
|
2018-05-12 04:33:12 +07:00
|
|
|
u8 nv12_planes;
|
2019-02-08 03:21:45 +07:00
|
|
|
u8 c8_planes;
|
drm/i915: enable scrambling
Geminilake platform sports a native HDMI 2.0 controller, and is
capable of driving pixel-clocks upto 594Mhz. HDMI 2.0 spec
mendates scrambling for these higher clocks, for reduced RF footprint.
This patch checks if the monitor supports scrambling, and if required,
enables it during the modeset.
V2: Addressed review comments from Ville:
- Do not track scrambling status in DRM layer, track somewhere in
driver like in intel_crtc_state.
- Don't talk to monitor at such a low layer, set monitor scrambling
in intel_enable_ddi() before enabling the port.
V3: Addressed review comments from Jani
- In comments, function names, use "sink" instead of "monitor",
so that the implementation could be close to the language of
HDMI spec.
V4: Addressed review comment from Maarten
- scrambling -> hdmi_scrambling
- high_tmds_clock_ratio -> hdmi_high_tmds_clock_ratio
V5: Addressed review comments from Ville and Ander
- Do not modifiy the crtc_state after compute_config. Move all
scrambling and tmds_clock_ratio calcutations to compute_config.
- While setting scrambling for source/sink, do not check the
conditions again, just go by the crtc_state flags. This will
simplyfy the condition checks.
V6: Addressed review comments from Ville
- Do not add IS_GLK check in disable/enable function, instead add it
in compute_config, while setting state flags.
- Remove unnecessary paranthesis.
- Simplyfy handle_sink_scrambling function as suggested.
- Add readout code for scrambling status in get_ddi_config and add a
check for the same in pipe_config_compare.
V7: Addressed review comments from Ander/Ville
- No separate function for source scrambling, make it inline
- Align the last line of the macro TRANS_DDI_HDMI_SCRAMBLING_MASK
- Do not add platform check while setting source scrambling
- Use pipe_config instead of crtc->config to set sink scrambling
- To readout scrambling status, Compare with SCRAMBLING_MASK
not any of its bits
- Remove platform check in intel_pipe_config_compare while checking
scrambling status
V8: Fixed mege conflict, Addressed review comments from Ander
- Remove the desciption/comment about scrambling fom the caller, move
it to the function
- Move the IS_GLK check into scrambling function
- Fix alignment
V9: Fixed review comments from Ville, Ander
- Pass the scrambling state variables as bool input to the sink_scrambling
function and let the disable call be unconditional.
- Fix alignments in function calls and debug messages.
- Add kernel doc for function intel_hdmi_handle_sink_scrambling
V10: Rebase
Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
Reviewed-by: Ander Conselvan de Oliveira <conselvan2@gmail.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1489404244-16608-6-git-send-email-shashank.sharma@intel.com
2017-03-13 18:24:03 +07:00
|
|
|
|
2018-11-27 23:37:42 +07:00
|
|
|
/* bitmask of planes that will be updated during the commit */
|
|
|
|
u8 update_planes;
|
|
|
|
|
2019-02-26 00:41:00 +07:00
|
|
|
struct {
|
|
|
|
u32 enable;
|
2019-02-26 00:41:01 +07:00
|
|
|
u32 gcp;
|
|
|
|
union hdmi_infoframe avi;
|
|
|
|
union hdmi_infoframe spd;
|
|
|
|
union hdmi_infoframe hdmi;
|
2019-05-18 17:39:27 +07:00
|
|
|
union hdmi_infoframe drm;
|
2019-02-26 00:41:00 +07:00
|
|
|
} infoframes;
|
|
|
|
|
drm/i915: enable scrambling
Geminilake platform sports a native HDMI 2.0 controller, and is
capable of driving pixel-clocks upto 594Mhz. HDMI 2.0 spec
mendates scrambling for these higher clocks, for reduced RF footprint.
This patch checks if the monitor supports scrambling, and if required,
enables it during the modeset.
V2: Addressed review comments from Ville:
- Do not track scrambling status in DRM layer, track somewhere in
driver like in intel_crtc_state.
- Don't talk to monitor at such a low layer, set monitor scrambling
in intel_enable_ddi() before enabling the port.
V3: Addressed review comments from Jani
- In comments, function names, use "sink" instead of "monitor",
so that the implementation could be close to the language of
HDMI spec.
V4: Addressed review comment from Maarten
- scrambling -> hdmi_scrambling
- high_tmds_clock_ratio -> hdmi_high_tmds_clock_ratio
V5: Addressed review comments from Ville and Ander
- Do not modifiy the crtc_state after compute_config. Move all
scrambling and tmds_clock_ratio calcutations to compute_config.
- While setting scrambling for source/sink, do not check the
conditions again, just go by the crtc_state flags. This will
simplyfy the condition checks.
V6: Addressed review comments from Ville
- Do not add IS_GLK check in disable/enable function, instead add it
in compute_config, while setting state flags.
- Remove unnecessary paranthesis.
- Simplyfy handle_sink_scrambling function as suggested.
- Add readout code for scrambling status in get_ddi_config and add a
check for the same in pipe_config_compare.
V7: Addressed review comments from Ander/Ville
- No separate function for source scrambling, make it inline
- Align the last line of the macro TRANS_DDI_HDMI_SCRAMBLING_MASK
- Do not add platform check while setting source scrambling
- Use pipe_config instead of crtc->config to set sink scrambling
- To readout scrambling status, Compare with SCRAMBLING_MASK
not any of its bits
- Remove platform check in intel_pipe_config_compare while checking
scrambling status
V8: Fixed mege conflict, Addressed review comments from Ander
- Remove the desciption/comment about scrambling fom the caller, move
it to the function
- Move the IS_GLK check into scrambling function
- Fix alignment
V9: Fixed review comments from Ville, Ander
- Pass the scrambling state variables as bool input to the sink_scrambling
function and let the disable call be unconditional.
- Fix alignments in function calls and debug messages.
- Add kernel doc for function intel_hdmi_handle_sink_scrambling
V10: Rebase
Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
Reviewed-by: Ander Conselvan de Oliveira <conselvan2@gmail.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1489404244-16608-6-git-send-email-shashank.sharma@intel.com
2017-03-13 18:24:03 +07:00
|
|
|
/* HDMI scrambling status */
|
|
|
|
bool hdmi_scrambling;
|
|
|
|
|
|
|
|
/* HDMI High TMDS char rate ratio */
|
|
|
|
bool hdmi_high_tmds_clock_ratio;
|
2017-07-21 22:25:04 +07:00
|
|
|
|
2018-10-12 13:23:07 +07:00
|
|
|
/* Output format RGB/YCBCR etc */
|
|
|
|
enum intel_output_format output_format;
|
2018-10-12 13:23:14 +07:00
|
|
|
|
|
|
|
/* Output down scaling is done in LSPCON device */
|
|
|
|
bool lspcon_downsampling;
|
2018-11-29 03:26:12 +07:00
|
|
|
|
2019-02-08 03:39:13 +07:00
|
|
|
/* enable pipe gamma? */
|
|
|
|
bool gamma_enable;
|
|
|
|
|
2019-02-08 03:21:42 +07:00
|
|
|
/* enable pipe csc? */
|
|
|
|
bool csc_enable;
|
|
|
|
|
2018-11-29 03:26:12 +07:00
|
|
|
/* Display Stream compression state */
|
|
|
|
struct {
|
|
|
|
bool compression_enable;
|
|
|
|
bool dsc_split;
|
|
|
|
u16 compressed_bpp;
|
|
|
|
u8 slice_count;
|
|
|
|
} dsc_params;
|
|
|
|
struct drm_dsc_config dp_dsc_cfg;
|
2018-11-29 03:26:25 +07:00
|
|
|
|
|
|
|
/* Forward Error correction State */
|
|
|
|
bool fec_enable;
|
2013-03-27 06:44:50 +07:00
|
|
|
};
|
|
|
|
|
DRM: i915: add mode setting support
This commit adds i915 driver support for the DRM mode setting APIs.
Currently, VGA, LVDS, SDVO DVI & VGA, TV and DVO LVDS outputs are
supported. HDMI, DisplayPort and additional SDVO output support will
follow.
Support for the mode setting code is controlled by the new 'modeset'
module option. A new config option, CONFIG_DRM_I915_KMS controls the
default behavior, and whether a PCI ID list is built into the module for
use by user level module utilities.
Note that if mode setting is enabled, user level drivers that access
display registers directly or that don't use the kernel graphics memory
manager will likely corrupt kernel graphics memory, disrupt output
configuration (possibly leading to hangs and/or blank displays), and
prevent panic/oops messages from appearing. So use caution when
enabling this code; be sure your user level code supports the new
interfaces.
A new SysRq key, 'g', provides emergency support for switching back to
the kernel's framebuffer console; which is useful for testing.
Co-authors: Dave Airlie <airlied@linux.ie>, Hong Liu <hong.liu@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2008-11-08 05:24:08 +07:00
|
|
|
struct intel_crtc {
|
|
|
|
struct drm_crtc base;
|
2009-09-11 05:28:06 +07:00
|
|
|
enum pipe pipe;
|
2012-07-02 16:43:47 +07:00
|
|
|
/*
|
|
|
|
* Whether the crtc and the connected output pipeline is active. Implies
|
|
|
|
* that crtc->enabled is set, i.e. the current mode configuration has
|
|
|
|
* some outputs connected to this crtc.
|
|
|
|
*/
|
|
|
|
bool active;
|
2016-11-22 23:01:57 +07:00
|
|
|
u8 plane_ids_mask;
|
2017-02-09 16:31:21 +07:00
|
|
|
unsigned long long enabled_power_domains;
|
2009-09-16 03:57:34 +07:00
|
|
|
struct intel_overlay *overlay;
|
2010-07-09 14:45:04 +07:00
|
|
|
|
2015-01-15 19:55:25 +07:00
|
|
|
struct intel_crtc_state *config;
|
2013-03-27 06:44:50 +07:00
|
|
|
|
drm/i915: report Gen5+ CPU and PCH FIFO underruns
In this commit we enable both CPU and PCH FIFO underrun reporting and
start reporting them. We follow a few rules:
- after we receive one of these errors, we mask the interrupt, so
we won't get an "interrupt storm" and we also won't flood dmesg;
- at each mode set we enable the interrupts again, so we'll see each
message at most once per mode set;
- in the specific places where we need to ignore the errors, we
completely mask the interrupts.
The downside of this patch is that since we're completely disabling
(masking) the interrupts instead of just not printing error messages,
we will mask more than just what we want on IVB/HSW CPU interrupts
(due to GEN7_ERR_INT) and on CPT/PPT/LPT PCHs (due to SERR_INT). So
when we decide to mask PCH FIFO underruns for pipe A on CPT, we'll
also be masking PCH FIFO underruns for pipe B, because both are
reported by SERR_INT, which has to be either completely enabled or
completely disabled (in othe words, there's no way to disable/enable
specific bits of GEN7_ERR_INT and SERR_INT).
V2: Rename some functions and variables, downgrade messages to
DRM_DEBUG_DRIVER and rebase.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-04-13 03:57:57 +07:00
|
|
|
/* Access to these should be protected by dev_priv->irq_lock. */
|
|
|
|
bool cpu_fifo_underrun_disabled;
|
|
|
|
bool pch_fifo_underrun_disabled;
|
2013-10-09 23:17:55 +07:00
|
|
|
|
|
|
|
/* per-pipe watermark state */
|
|
|
|
struct {
|
|
|
|
/* watermarks currently being used */
|
2015-09-25 05:53:15 +07:00
|
|
|
union {
|
|
|
|
struct intel_pipe_wm ilk;
|
2017-03-03 00:14:53 +07:00
|
|
|
struct vlv_wm_state vlv;
|
2017-04-22 01:14:29 +07:00
|
|
|
struct g4x_wm_state g4x;
|
2015-09-25 05:53:15 +07:00
|
|
|
} active;
|
2013-10-09 23:17:55 +07:00
|
|
|
} wm;
|
2014-04-29 17:35:46 +07:00
|
|
|
|
2014-05-16 00:23:23 +07:00
|
|
|
int scanline_offset;
|
2014-12-24 22:59:06 +07:00
|
|
|
|
2015-09-16 04:19:32 +07:00
|
|
|
struct {
|
|
|
|
unsigned start_vbl_count;
|
|
|
|
ktime_t start_vbl_time;
|
|
|
|
int min_vbl, max_vbl;
|
|
|
|
int scanline_start;
|
|
|
|
} debug;
|
2015-09-01 17:15:33 +07:00
|
|
|
|
2015-04-08 05:28:36 +07:00
|
|
|
/* scalers available on this crtc */
|
|
|
|
int num_scalers;
|
DRM: i915: add mode setting support
This commit adds i915 driver support for the DRM mode setting APIs.
Currently, VGA, LVDS, SDVO DVI & VGA, TV and DVO LVDS outputs are
supported. HDMI, DisplayPort and additional SDVO output support will
follow.
Support for the mode setting code is controlled by the new 'modeset'
module option. A new config option, CONFIG_DRM_I915_KMS controls the
default behavior, and whether a PCI ID list is built into the module for
use by user level module utilities.
Note that if mode setting is enabled, user level drivers that access
display registers directly or that don't use the kernel graphics memory
manager will likely corrupt kernel graphics memory, disrupt output
configuration (possibly leading to hangs and/or blank displays), and
prevent panic/oops messages from appearing. So use caution when
enabling this code; be sure your user level code supports the new
interfaces.
A new SysRq key, 'g', provides emergency support for switching back to
the kernel's framebuffer console; which is useful for testing.
Co-authors: Dave Airlie <airlied@linux.ie>, Hong Liu <hong.liu@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2008-11-08 05:24:08 +07:00
|
|
|
};
|
|
|
|
|
2011-12-14 04:19:38 +07:00
|
|
|
struct intel_plane {
|
|
|
|
struct drm_plane base;
|
2017-11-18 02:19:10 +07:00
|
|
|
enum i9xx_plane_id i9xx_plane;
|
2016-11-22 23:01:56 +07:00
|
|
|
enum plane_id id;
|
2011-12-14 04:19:38 +07:00
|
|
|
enum pipe pipe;
|
2018-02-22 00:31:01 +07:00
|
|
|
bool has_fbc;
|
2018-05-18 23:21:59 +07:00
|
|
|
bool has_ccs;
|
2019-01-18 19:01:25 +07:00
|
|
|
u32 frontbuffer_bit;
|
2013-05-24 21:59:18 +07:00
|
|
|
|
2017-03-28 01:55:35 +07:00
|
|
|
struct {
|
|
|
|
u32 base, cntl, size;
|
|
|
|
} cursor;
|
|
|
|
|
2015-01-22 07:35:41 +07:00
|
|
|
/*
|
|
|
|
* NOTE: Do not place new plane state fields here (e.g., when adding
|
|
|
|
* new plane properties). New runtime state should now be placed in
|
2016-01-07 17:54:06 +07:00
|
|
|
* the intel_plane_state structure and accessed via plane_state.
|
2015-01-22 07:35:41 +07:00
|
|
|
*/
|
|
|
|
|
2018-09-07 22:24:02 +07:00
|
|
|
unsigned int (*max_stride)(struct intel_plane *plane,
|
|
|
|
u32 pixel_format, u64 modifier,
|
|
|
|
unsigned int rotation);
|
2017-03-28 01:55:33 +07:00
|
|
|
void (*update_plane)(struct intel_plane *plane,
|
2016-01-07 17:54:06 +07:00
|
|
|
const struct intel_crtc_state *crtc_state,
|
|
|
|
const struct intel_plane_state *plane_state);
|
drm/i915/gen11: Link nv12 Y and UV planes in the atomic state, v5.
To make NV12 working on icl, we need to update 2 planes simultaneously.
I've chosen to do this in the CRTC step after plane validation is done,
so we know what planes are (in)visible. The linked Y plane will get
updated in intel_plane_update_planes_on_crtc(), by the call to
update_slave, which gets the master's plane_state as argument.
The link requires both planes for atomic_update to work,
so make sure skl_ddb_add_affected_planes() adds both states.
Changes since v1:
- Introduce icl_is_nv12_y_plane(), instead of hardcoding sprite numbers.
- Put all the state updating login in intel_plane_atomic_check_with_state().
- Clean up changes in intel_plane_atomic_check().
Changes since v2:
- Fix intel_atomic_get_old_plane_state() to actually return old state.
- Move visibility changes to preparation patch.
- Only try to find a Y plane on gen11, earlier platforms only require
a single plane.
Changes since v3:
- Fix checkpatch warning about to_intel_crtc() usage.
- Add affected planes from icl_add_linked_planes() before check_planes(),
it's a cleaner way to do this. (Ville)
Changes since v4:
- Clear plane links in icl_check_nv12_planes() for clarity.
- Only pass crtc_state to icl_check_nv12_planes().
- Use for_each_new_intel_plane_in_state() in icl_check_nv12_planes.
- Rename aux to linked. (Ville)
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181022135152.15324-1-maarten.lankhorst@linux.intel.com
[mlankhorst: Change bool slave to u32, to satisfy checkpatch]
[mlankhorst: Add WARN_ON's based on Ville's suggestion]
2018-10-22 20:51:52 +07:00
|
|
|
void (*update_slave)(struct intel_plane *plane,
|
|
|
|
const struct intel_crtc_state *crtc_state,
|
|
|
|
const struct intel_plane_state *plane_state);
|
2017-03-28 01:55:33 +07:00
|
|
|
void (*disable_plane)(struct intel_plane *plane,
|
2018-11-15 04:07:20 +07:00
|
|
|
const struct intel_crtc_state *crtc_state);
|
2018-01-31 03:38:03 +07:00
|
|
|
bool (*get_hw_state)(struct intel_plane *plane, enum pipe *pipe);
|
2018-08-28 21:27:06 +07:00
|
|
|
int (*check_plane)(struct intel_crtc_state *crtc_state,
|
|
|
|
struct intel_plane_state *plane_state);
|
2011-12-14 04:19:38 +07:00
|
|
|
};
|
|
|
|
|
2012-04-17 08:20:35 +07:00
|
|
|
struct intel_watermark_params {
|
2016-10-13 17:09:25 +07:00
|
|
|
u16 fifo_size;
|
|
|
|
u16 max_wm;
|
|
|
|
u8 default_wm;
|
|
|
|
u8 guard_size;
|
|
|
|
u8 cacheline_size;
|
2012-04-17 08:20:35 +07:00
|
|
|
};
|
|
|
|
|
|
|
|
struct cxsr_latency {
|
2016-10-14 20:55:02 +07:00
|
|
|
bool is_desktop : 1;
|
|
|
|
bool is_ddr3 : 1;
|
2016-10-13 17:09:23 +07:00
|
|
|
u16 fsb_freq;
|
|
|
|
u16 mem_freq;
|
|
|
|
u16 display_sr;
|
|
|
|
u16 display_hpll_disable;
|
|
|
|
u16 cursor_sr;
|
|
|
|
u16 cursor_hpll_disable;
|
2012-04-17 08:20:35 +07:00
|
|
|
};
|
|
|
|
|
2015-06-04 15:21:28 +07:00
|
|
|
#define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
|
DRM: i915: add mode setting support
This commit adds i915 driver support for the DRM mode setting APIs.
Currently, VGA, LVDS, SDVO DVI & VGA, TV and DVO LVDS outputs are
supported. HDMI, DisplayPort and additional SDVO output support will
follow.
Support for the mode setting code is controlled by the new 'modeset'
module option. A new config option, CONFIG_DRM_I915_KMS controls the
default behavior, and whether a PCI ID list is built into the module for
use by user level module utilities.
Note that if mode setting is enabled, user level drivers that access
display registers directly or that don't use the kernel graphics memory
manager will likely corrupt kernel graphics memory, disrupt output
configuration (possibly leading to hangs and/or blank displays), and
prevent panic/oops messages from appearing. So use caution when
enabling this code; be sure your user level code supports the new
interfaces.
A new SysRq key, 'g', provides emergency support for switching back to
the kernel's framebuffer console; which is useful for testing.
Co-authors: Dave Airlie <airlied@linux.ie>, Hong Liu <hong.liu@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2008-11-08 05:24:08 +07:00
|
|
|
#define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
|
2015-03-20 21:18:01 +07:00
|
|
|
#define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
|
2010-03-30 13:39:28 +07:00
|
|
|
#define to_intel_connector(x) container_of(x, struct intel_connector, base)
|
2010-09-09 21:14:28 +07:00
|
|
|
#define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
|
DRM: i915: add mode setting support
This commit adds i915 driver support for the DRM mode setting APIs.
Currently, VGA, LVDS, SDVO DVI & VGA, TV and DVO LVDS outputs are
supported. HDMI, DisplayPort and additional SDVO output support will
follow.
Support for the mode setting code is controlled by the new 'modeset'
module option. A new config option, CONFIG_DRM_I915_KMS controls the
default behavior, and whether a PCI ID list is built into the module for
use by user level module utilities.
Note that if mode setting is enabled, user level drivers that access
display registers directly or that don't use the kernel graphics memory
manager will likely corrupt kernel graphics memory, disrupt output
configuration (possibly leading to hangs and/or blank displays), and
prevent panic/oops messages from appearing. So use caution when
enabling this code; be sure your user level code supports the new
interfaces.
A new SysRq key, 'g', provides emergency support for switching back to
the kernel's framebuffer console; which is useful for testing.
Co-authors: Dave Airlie <airlied@linux.ie>, Hong Liu <hong.liu@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2008-11-08 05:24:08 +07:00
|
|
|
#define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
|
2011-12-14 04:19:38 +07:00
|
|
|
#define to_intel_plane(x) container_of(x, struct intel_plane, base)
|
2014-12-24 01:41:52 +07:00
|
|
|
#define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
|
2018-05-18 21:30:08 +07:00
|
|
|
#define intel_fb_obj(x) ((x) ? to_intel_bo((x)->obj[0]) : NULL)
|
DRM: i915: add mode setting support
This commit adds i915 driver support for the DRM mode setting APIs.
Currently, VGA, LVDS, SDVO DVI & VGA, TV and DVO LVDS outputs are
supported. HDMI, DisplayPort and additional SDVO output support will
follow.
Support for the mode setting code is controlled by the new 'modeset'
module option. A new config option, CONFIG_DRM_I915_KMS controls the
default behavior, and whether a PCI ID list is built into the module for
use by user level module utilities.
Note that if mode setting is enabled, user level drivers that access
display registers directly or that don't use the kernel graphics memory
manager will likely corrupt kernel graphics memory, disrupt output
configuration (possibly leading to hangs and/or blank displays), and
prevent panic/oops messages from appearing. So use caution when
enabling this code; be sure your user level code supports the new
interfaces.
A new SysRq key, 'g', provides emergency support for switching back to
the kernel's framebuffer console; which is useful for testing.
Co-authors: Dave Airlie <airlied@linux.ie>, Hong Liu <hong.liu@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2008-11-08 05:24:08 +07:00
|
|
|
|
2012-05-10 01:37:30 +07:00
|
|
|
struct intel_hdmi {
|
drm/i915: Type safe register read/write
Make I915_READ and I915_WRITE more type safe by wrapping the register
offset in a struct. This should eliminate most of the fumbles we've had
with misplaced parens.
This only takes care of normal mmio registers. We could extend the idea
to other register types and define each with its own struct. That way
you wouldn't be able to accidentally pass the wrong thing to a specific
register access function.
The gpio_reg setup is probably the ugliest thing left. But I figure I'd
just leave it for now, and wait for some divine inspiration to strike
before making it nice.
As for the generated code, it's actually a bit better sometimes. Eg.
looking at i915_irq_handler(), we can see the following change:
lea 0x70024(%rdx,%rax,1),%r9d
mov $0x1,%edx
- movslq %r9d,%r9
- mov %r9,%rsi
- mov %r9,-0x58(%rbp)
- callq *0xd8(%rbx)
+ mov %r9d,%esi
+ mov %r9d,-0x48(%rbp)
callq *0xd8(%rbx)
So previously gcc thought the register offset might be signed and
decided to sign extend it, just in case. The rest appears to be
mostly just minor shuffling of instructions.
v2: i915_mmio_reg_{offset,equal,valid}() helpers added
s/_REG/_MMIO/ in the register defines
mo more switch statements left to worry about
ring_emit stuff got sorted in a prep patch
cmd parser, lrc context and w/a batch buildup also in prep patch
vgpu stuff cleaned up and moved to a prep patch
all other unrelated changes split out
v3: Rebased due to BXT DSI/BLC, MOCS, etc.
v4: Rebased due to churn, s/i915_mmio_reg_t/i915_reg_t/
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: http://patchwork.freedesktop.org/patch/msgid/1447853606-2751-1-git-send-email-ville.syrjala@linux.intel.com
2015-11-18 20:33:26 +07:00
|
|
|
i915_reg_t hdmi_reg;
|
2012-05-10 01:37:30 +07:00
|
|
|
int ddc_bus;
|
2016-05-03 02:08:23 +07:00
|
|
|
struct {
|
|
|
|
enum drm_dp_dual_mode_type type;
|
|
|
|
int max_tmds_clock;
|
|
|
|
} dp_dual_mode;
|
2012-05-10 01:37:30 +07:00
|
|
|
bool has_hdmi_sink;
|
|
|
|
bool has_audio;
|
2015-09-04 20:26:11 +07:00
|
|
|
struct intel_connector *attached_connector;
|
2018-07-04 22:08:17 +07:00
|
|
|
struct cec_notifier *cec_notifier;
|
2012-05-10 01:37:30 +07:00
|
|
|
};
|
|
|
|
|
2014-05-02 11:02:48 +07:00
|
|
|
struct intel_dp_mst_encoder;
|
2012-09-18 21:58:49 +07:00
|
|
|
#define DP_MAX_DOWNSTREAM_PORTS 0x10
|
2012-06-30 02:03:35 +07:00
|
|
|
|
2015-02-13 17:02:59 +07:00
|
|
|
/*
|
|
|
|
* enum link_m_n_set:
|
|
|
|
* When platform provides two set of M_N registers for dp, we can
|
|
|
|
* program them and switch between them incase of DRRS.
|
|
|
|
* But When only one such register is provided, we have to program the
|
|
|
|
* required divider value on that registers itself based on the DRRS state.
|
|
|
|
*
|
|
|
|
* M1_N1 : Program dp_m_n on M1_N1 registers
|
|
|
|
* dp_m2_n2 on M2_N2 registers (If supported)
|
|
|
|
*
|
|
|
|
* M2_N2 : Program dp_m2_n2 on M1_N1 registers
|
|
|
|
* M2_N2 registers are not supported
|
|
|
|
*/
|
|
|
|
|
|
|
|
enum link_m_n_set {
|
|
|
|
/* Sets the m1_n1 and m2_n2 */
|
|
|
|
M1_N1 = 0,
|
|
|
|
M2_N2
|
|
|
|
};
|
|
|
|
|
2016-12-10 07:22:50 +07:00
|
|
|
struct intel_dp_compliance_data {
|
|
|
|
unsigned long edid;
|
2019-01-18 19:01:25 +07:00
|
|
|
u8 video_pattern;
|
|
|
|
u16 hdisplay, vdisplay;
|
|
|
|
u8 bpc;
|
2016-12-10 07:22:50 +07:00
|
|
|
};
|
|
|
|
|
|
|
|
struct intel_dp_compliance {
|
|
|
|
unsigned long test_type;
|
|
|
|
struct intel_dp_compliance_data test_data;
|
|
|
|
bool test_active;
|
2017-01-24 23:16:34 +07:00
|
|
|
int test_link_rate;
|
|
|
|
u8 test_lane_count;
|
2016-12-10 07:22:50 +07:00
|
|
|
};
|
|
|
|
|
2012-06-30 02:03:35 +07:00
|
|
|
struct intel_dp {
|
drm/i915: Type safe register read/write
Make I915_READ and I915_WRITE more type safe by wrapping the register
offset in a struct. This should eliminate most of the fumbles we've had
with misplaced parens.
This only takes care of normal mmio registers. We could extend the idea
to other register types and define each with its own struct. That way
you wouldn't be able to accidentally pass the wrong thing to a specific
register access function.
The gpio_reg setup is probably the ugliest thing left. But I figure I'd
just leave it for now, and wait for some divine inspiration to strike
before making it nice.
As for the generated code, it's actually a bit better sometimes. Eg.
looking at i915_irq_handler(), we can see the following change:
lea 0x70024(%rdx,%rax,1),%r9d
mov $0x1,%edx
- movslq %r9d,%r9
- mov %r9,%rsi
- mov %r9,-0x58(%rbp)
- callq *0xd8(%rbx)
+ mov %r9d,%esi
+ mov %r9d,-0x48(%rbp)
callq *0xd8(%rbx)
So previously gcc thought the register offset might be signed and
decided to sign extend it, just in case. The rest appears to be
mostly just minor shuffling of instructions.
v2: i915_mmio_reg_{offset,equal,valid}() helpers added
s/_REG/_MMIO/ in the register defines
mo more switch statements left to worry about
ring_emit stuff got sorted in a prep patch
cmd parser, lrc context and w/a batch buildup also in prep patch
vgpu stuff cleaned up and moved to a prep patch
all other unrelated changes split out
v3: Rebased due to BXT DSI/BLC, MOCS, etc.
v4: Rebased due to churn, s/i915_mmio_reg_t/i915_reg_t/
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: http://patchwork.freedesktop.org/patch/msgid/1447853606-2751-1-git-send-email-ville.syrjala@linux.intel.com
2015-11-18 20:33:26 +07:00
|
|
|
i915_reg_t output_reg;
|
2019-01-18 19:01:25 +07:00
|
|
|
u32 DP;
|
2015-08-17 22:05:12 +07:00
|
|
|
int link_rate;
|
2019-01-18 19:01:25 +07:00
|
|
|
u8 lane_count;
|
|
|
|
u8 sink_count;
|
2016-07-28 21:50:39 +07:00
|
|
|
bool link_mst;
|
2018-01-18 02:21:49 +07:00
|
|
|
bool link_trained;
|
2012-06-30 02:03:35 +07:00
|
|
|
bool has_audio;
|
2017-02-08 07:54:11 +07:00
|
|
|
bool reset_link_params;
|
2019-01-18 19:01:25 +07:00
|
|
|
u8 dpcd[DP_RECEIVER_CAP_SIZE];
|
|
|
|
u8 psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
|
|
|
|
u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
|
|
|
|
u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
|
2018-10-31 07:19:19 +07:00
|
|
|
u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE];
|
2018-11-02 11:14:54 +07:00
|
|
|
u8 fec_capable;
|
2017-03-28 21:59:04 +07:00
|
|
|
/* source rates */
|
|
|
|
int num_source_rates;
|
|
|
|
const int *source_rates;
|
2017-03-28 21:59:05 +07:00
|
|
|
/* sink rates as reported by DP_MAX_LINK_RATE/DP_SUPPORTED_LINK_RATES */
|
|
|
|
int num_sink_rates;
|
2015-03-14 00:40:31 +07:00
|
|
|
int sink_rates[DP_MAX_SUPPORTED_RATES];
|
2017-03-28 21:59:05 +07:00
|
|
|
bool use_rate_select;
|
2017-04-06 20:44:10 +07:00
|
|
|
/* intersection of source and sink rates */
|
|
|
|
int num_common_rates;
|
|
|
|
int common_rates[DP_MAX_SUPPORTED_RATES];
|
2017-04-06 20:44:12 +07:00
|
|
|
/* Max lane count for the current link */
|
|
|
|
int max_link_lane_count;
|
|
|
|
/* Max rate for the current link */
|
|
|
|
int max_link_rate;
|
2016-10-25 20:12:39 +07:00
|
|
|
/* sink or branch descriptor */
|
2017-05-18 18:10:23 +07:00
|
|
|
struct drm_dp_desc desc;
|
2014-03-14 21:51:15 +07:00
|
|
|
struct drm_dp_aux aux;
|
2019-01-18 19:01:25 +07:00
|
|
|
u8 train_set[4];
|
2012-06-30 02:03:35 +07:00
|
|
|
int panel_power_up_delay;
|
|
|
|
int panel_power_down_delay;
|
|
|
|
int panel_power_cycle_delay;
|
|
|
|
int backlight_on_delay;
|
|
|
|
int backlight_off_delay;
|
|
|
|
struct delayed_work panel_vdd_work;
|
|
|
|
bool want_panel_vdd;
|
2013-12-19 23:29:40 +07:00
|
|
|
unsigned long last_power_on;
|
|
|
|
unsigned long last_backlight_off;
|
2016-01-23 08:39:04 +07:00
|
|
|
ktime_t panel_power_off_time;
|
2014-08-05 06:04:59 +07:00
|
|
|
|
2014-07-08 03:01:46 +07:00
|
|
|
struct notifier_block edp_notifier;
|
|
|
|
|
2014-09-04 18:54:20 +07:00
|
|
|
/*
|
|
|
|
* Pipe whose power sequencer is currently locked into
|
|
|
|
* this port. Only relevant on VLV/CHV.
|
|
|
|
*/
|
|
|
|
enum pipe pps_pipe;
|
2016-12-15 01:00:23 +07:00
|
|
|
/*
|
|
|
|
* Pipe currently driving the port. Used for preventing
|
|
|
|
* the use of the PPS for any pipe currentrly driving
|
|
|
|
* external DP as that will mess things up on VLV.
|
|
|
|
*/
|
|
|
|
enum pipe active_pipe;
|
2016-06-16 20:37:20 +07:00
|
|
|
/*
|
|
|
|
* Set if the sequencer may be reset due to a power transition,
|
|
|
|
* requiring a reinitialization. Only relevant on BXT.
|
|
|
|
*/
|
|
|
|
bool pps_reset;
|
2014-10-17 01:27:30 +07:00
|
|
|
struct edp_power_seq pps_delays;
|
2014-09-04 18:54:20 +07:00
|
|
|
|
2014-05-02 11:02:48 +07:00
|
|
|
bool can_mst; /* this port supports mst */
|
|
|
|
bool is_mst;
|
2016-08-05 23:05:42 +07:00
|
|
|
int active_mst_links;
|
2014-05-02 11:02:48 +07:00
|
|
|
/* connector directly attached - won't be use for modeset in mst world */
|
2012-10-19 18:51:50 +07:00
|
|
|
struct intel_connector *attached_connector;
|
2014-01-21 20:35:39 +07:00
|
|
|
|
2014-05-02 11:02:48 +07:00
|
|
|
/* mst connector list */
|
|
|
|
struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
|
|
|
|
struct drm_dp_mst_topology_mgr mst_mgr;
|
|
|
|
|
2019-01-18 19:01:25 +07:00
|
|
|
u32 (*get_aux_clock_divider)(struct intel_dp *dp, int index);
|
2014-01-21 20:37:15 +07:00
|
|
|
/*
|
|
|
|
* This function returns the value we have to program the AUX_CTL
|
|
|
|
* register with to kick off an AUX transaction.
|
|
|
|
*/
|
2019-01-18 19:01:25 +07:00
|
|
|
u32 (*get_aux_send_ctl)(struct intel_dp *dp, int send_bytes,
|
|
|
|
u32 aux_clock_divider);
|
2015-10-23 17:01:49 +07:00
|
|
|
|
2018-02-23 01:10:31 +07:00
|
|
|
i915_reg_t (*aux_ch_ctl_reg)(struct intel_dp *dp);
|
|
|
|
i915_reg_t (*aux_ch_data_reg)(struct intel_dp *dp, int index);
|
|
|
|
|
2015-10-23 17:01:49 +07:00
|
|
|
/* This is called before a link training is starterd */
|
|
|
|
void (*prepare_link_retrain)(struct intel_dp *intel_dp);
|
|
|
|
|
2015-04-15 22:38:38 +07:00
|
|
|
/* Displayport compliance testing */
|
2016-12-10 07:22:50 +07:00
|
|
|
struct intel_dp_compliance compliance;
|
2018-12-06 07:54:07 +07:00
|
|
|
|
|
|
|
/* Display stream compression testing */
|
|
|
|
bool force_dsc_en;
|
2012-06-30 02:03:35 +07:00
|
|
|
};
|
|
|
|
|
2018-10-12 13:23:10 +07:00
|
|
|
enum lspcon_vendor {
|
|
|
|
LSPCON_VENDOR_MCA,
|
|
|
|
LSPCON_VENDOR_PARADE
|
|
|
|
};
|
|
|
|
|
2016-10-14 21:26:49 +07:00
|
|
|
struct intel_lspcon {
|
|
|
|
bool active;
|
|
|
|
enum drm_lspcon_mode mode;
|
2018-10-12 13:23:10 +07:00
|
|
|
enum lspcon_vendor vendor;
|
2016-10-14 21:26:49 +07:00
|
|
|
};
|
|
|
|
|
2012-10-27 04:05:46 +07:00
|
|
|
struct intel_digital_port {
|
|
|
|
struct intel_encoder base;
|
2013-07-13 03:54:41 +07:00
|
|
|
u32 saved_port_bits;
|
2012-10-27 04:05:46 +07:00
|
|
|
struct intel_dp dp;
|
|
|
|
struct intel_hdmi hdmi;
|
2016-10-14 21:26:49 +07:00
|
|
|
struct intel_lspcon lspcon;
|
2015-01-23 12:00:31 +07:00
|
|
|
enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
|
drm/i915: Trick CL2 into life on CHV when using pipe B with port B
Normmally the common lane in a PHY channel gets powered up when some
of the data lanes get powered up. But when we're driving port B with
pipe B we don't want to enabled any of the data lanes, and just want
the DPLL in the common lane to be active.
To make that happens we have to temporarily enable some data lanes
after which we can access the DPLL registers in the common lane. Once
the pipe is up and running we can drop the power override on the data
lanes allowing them to shut down. From this point forward the common
lane will in fact stay powered on until the data lanes in the other
channel get powered down.
Ville's extended explanation from the review thread:
On Wed, Aug 19, 2015 at 07:47:41AM +0530, Deepak wrote:
> One Q, why only for port B? Port C is also in same common lane right?
Port B is in the first PHY channel which also houses CL1. CL1 always
powers up whenever any lanes in either PHY channel are powered up.
CL2 only powers up if lanes in the second channel (ie. the one with
port C) powers up.
So in this scenario (pipe B->port B) we want the DPLL from CL2, but
ideally we only want to power up the lanes for port B. Powering up
port B lanes will only power up CL1, but as we need CL2 instead we
need to, temporarily, power up some lanes in port C as well.
Crossing the streams the other way (pipe A->port C) is not a problem
since CL1 powers up whenever anything else powers up. So powering up
some port C lanes is enough on its own to make the CL1 DPLL
operational, even though CL1 and the lanes live in separate channels.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Deepak S <deepak.s@linux.intel.com>
[danvet: Amend commit message with extended explanation.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-07-09 03:45:55 +07:00
|
|
|
bool release_cl2_override;
|
2019-01-18 19:01:25 +07:00
|
|
|
u8 max_lanes;
|
2018-11-01 21:04:21 +07:00
|
|
|
/* Used for DP and ICL+ TypeC/DP and TypeC/HDMI ports. */
|
|
|
|
enum aux_ch aux_ch;
|
2017-02-24 21:19:59 +07:00
|
|
|
enum intel_display_power_domain ddi_io_power_domain;
|
2018-12-15 01:27:02 +07:00
|
|
|
bool tc_legacy_port:1;
|
2018-07-25 07:28:10 +07:00
|
|
|
enum tc_port_type tc_type;
|
2017-08-18 20:49:54 +07:00
|
|
|
|
2018-09-21 01:51:36 +07:00
|
|
|
void (*write_infoframe)(struct intel_encoder *encoder,
|
2017-08-18 20:49:54 +07:00
|
|
|
const struct intel_crtc_state *crtc_state,
|
2017-10-14 02:40:51 +07:00
|
|
|
unsigned int type,
|
2017-08-18 20:49:54 +07:00
|
|
|
const void *frame, ssize_t len);
|
2019-02-26 00:41:02 +07:00
|
|
|
void (*read_infoframe)(struct intel_encoder *encoder,
|
|
|
|
const struct intel_crtc_state *crtc_state,
|
|
|
|
unsigned int type,
|
|
|
|
void *frame, ssize_t len);
|
2018-09-21 01:51:36 +07:00
|
|
|
void (*set_infoframes)(struct intel_encoder *encoder,
|
2017-08-18 20:49:54 +07:00
|
|
|
bool enable,
|
|
|
|
const struct intel_crtc_state *crtc_state,
|
|
|
|
const struct drm_connector_state *conn_state);
|
2019-02-26 00:40:59 +07:00
|
|
|
u32 (*infoframes_enabled)(struct intel_encoder *encoder,
|
2017-08-18 20:49:54 +07:00
|
|
|
const struct intel_crtc_state *pipe_config);
|
2012-10-27 04:05:46 +07:00
|
|
|
};
|
|
|
|
|
2014-05-02 11:02:48 +07:00
|
|
|
struct intel_dp_mst_encoder {
|
|
|
|
struct intel_encoder base;
|
|
|
|
enum pipe pipe;
|
|
|
|
struct intel_digital_port *primary;
|
2016-03-09 08:14:38 +07:00
|
|
|
struct intel_connector *connector;
|
2014-05-02 11:02:48 +07:00
|
|
|
};
|
|
|
|
|
2015-07-09 03:45:53 +07:00
|
|
|
static inline enum dpio_channel
|
2013-04-19 04:51:36 +07:00
|
|
|
vlv_dport_to_channel(struct intel_digital_port *dport)
|
|
|
|
{
|
2017-11-09 22:24:34 +07:00
|
|
|
switch (dport->base.port) {
|
2013-04-19 04:51:36 +07:00
|
|
|
case PORT_B:
|
2014-04-09 17:28:15 +07:00
|
|
|
case PORT_D:
|
2013-11-06 13:36:35 +07:00
|
|
|
return DPIO_CH0;
|
2013-04-19 04:51:36 +07:00
|
|
|
case PORT_C:
|
2013-11-06 13:36:35 +07:00
|
|
|
return DPIO_CH1;
|
2013-04-19 04:51:36 +07:00
|
|
|
default:
|
|
|
|
BUG();
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2015-07-09 03:45:53 +07:00
|
|
|
static inline enum dpio_phy
|
|
|
|
vlv_dport_to_phy(struct intel_digital_port *dport)
|
|
|
|
{
|
2017-11-09 22:24:34 +07:00
|
|
|
switch (dport->base.port) {
|
2015-07-09 03:45:53 +07:00
|
|
|
case PORT_B:
|
|
|
|
case PORT_C:
|
|
|
|
return DPIO_PHY0;
|
|
|
|
case PORT_D:
|
|
|
|
return DPIO_PHY1;
|
|
|
|
default:
|
|
|
|
BUG();
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline enum dpio_channel
|
2014-04-09 17:28:16 +07:00
|
|
|
vlv_pipe_to_channel(enum pipe pipe)
|
|
|
|
{
|
|
|
|
switch (pipe) {
|
|
|
|
case PIPE_A:
|
|
|
|
case PIPE_C:
|
|
|
|
return DPIO_CH0;
|
|
|
|
case PIPE_B:
|
|
|
|
return DPIO_CH1;
|
|
|
|
default:
|
|
|
|
BUG();
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2016-11-01 03:37:05 +07:00
|
|
|
static inline struct intel_crtc *
|
2016-11-01 03:37:09 +07:00
|
|
|
intel_get_crtc_for_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
|
2010-09-09 21:44:14 +07:00
|
|
|
{
|
|
|
|
return dev_priv->pipe_to_crtc_mapping[pipe];
|
|
|
|
}
|
|
|
|
|
2016-11-01 03:37:05 +07:00
|
|
|
static inline struct intel_crtc *
|
2017-11-18 02:19:10 +07:00
|
|
|
intel_get_crtc_for_plane(struct drm_i915_private *dev_priv, enum i9xx_plane_id plane)
|
2011-01-19 22:04:42 +07:00
|
|
|
{
|
|
|
|
return dev_priv->plane_to_crtc_mapping[plane];
|
|
|
|
}
|
|
|
|
|
2013-09-24 23:52:53 +07:00
|
|
|
struct intel_load_detect_pipe {
|
2016-02-17 15:18:35 +07:00
|
|
|
struct drm_atomic_state *restore_state;
|
2013-09-24 23:52:53 +07:00
|
|
|
};
|
DRM: i915: add mode setting support
This commit adds i915 driver support for the DRM mode setting APIs.
Currently, VGA, LVDS, SDVO DVI & VGA, TV and DVO LVDS outputs are
supported. HDMI, DisplayPort and additional SDVO output support will
follow.
Support for the mode setting code is controlled by the new 'modeset'
module option. A new config option, CONFIG_DRM_I915_KMS controls the
default behavior, and whether a PCI ID list is built into the module for
use by user level module utilities.
Note that if mode setting is enabled, user level drivers that access
display registers directly or that don't use the kernel graphics memory
manager will likely corrupt kernel graphics memory, disrupt output
configuration (possibly leading to hangs and/or blank displays), and
prevent panic/oops messages from appearing. So use caution when
enabling this code; be sure your user level code supports the new
interfaces.
A new SysRq key, 'g', provides emergency support for switching back to
the kernel's framebuffer console; which is useful for testing.
Co-authors: Dave Airlie <airlied@linux.ie>, Hong Liu <hong.liu@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2008-11-08 05:24:08 +07:00
|
|
|
|
2013-09-24 23:52:53 +07:00
|
|
|
static inline struct intel_encoder *
|
|
|
|
intel_attached_encoder(struct drm_connector *connector)
|
2010-09-09 22:20:55 +07:00
|
|
|
{
|
|
|
|
return to_intel_connector(connector)->encoder;
|
|
|
|
}
|
|
|
|
|
2018-07-05 23:43:51 +07:00
|
|
|
static inline bool intel_encoder_is_dig_port(struct intel_encoder *encoder)
|
2012-10-27 04:05:46 +07:00
|
|
|
{
|
2018-07-05 23:43:51 +07:00
|
|
|
switch (encoder->type) {
|
2017-10-28 02:31:24 +07:00
|
|
|
case INTEL_OUTPUT_DDI:
|
2017-02-24 21:18:45 +07:00
|
|
|
case INTEL_OUTPUT_DP:
|
|
|
|
case INTEL_OUTPUT_EDP:
|
|
|
|
case INTEL_OUTPUT_HDMI:
|
2018-07-05 23:43:51 +07:00
|
|
|
return true;
|
|
|
|
default:
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline struct intel_digital_port *
|
|
|
|
enc_to_dig_port(struct drm_encoder *encoder)
|
|
|
|
{
|
|
|
|
struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
|
|
|
|
|
|
|
|
if (intel_encoder_is_dig_port(intel_encoder))
|
2017-02-24 21:18:45 +07:00
|
|
|
return container_of(encoder, struct intel_digital_port,
|
|
|
|
base.base);
|
2018-07-05 23:43:51 +07:00
|
|
|
else
|
2017-02-24 21:18:45 +07:00
|
|
|
return NULL;
|
2013-05-08 17:14:02 +07:00
|
|
|
}
|
|
|
|
|
2018-10-23 16:22:29 +07:00
|
|
|
static inline struct intel_digital_port *
|
|
|
|
conn_to_dig_port(struct intel_connector *connector)
|
|
|
|
{
|
|
|
|
return enc_to_dig_port(&intel_attached_encoder(&connector->base)->base);
|
|
|
|
}
|
|
|
|
|
2014-05-02 11:02:48 +07:00
|
|
|
static inline struct intel_dp_mst_encoder *
|
|
|
|
enc_to_mst(struct drm_encoder *encoder)
|
|
|
|
{
|
|
|
|
return container_of(encoder, struct intel_dp_mst_encoder, base.base);
|
|
|
|
}
|
|
|
|
|
2013-05-08 17:14:02 +07:00
|
|
|
static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
|
|
|
|
{
|
|
|
|
return &enc_to_dig_port(encoder)->dp;
|
2012-10-27 04:05:46 +07:00
|
|
|
}
|
|
|
|
|
2018-07-05 23:43:50 +07:00
|
|
|
static inline bool intel_encoder_is_dp(struct intel_encoder *encoder)
|
|
|
|
{
|
|
|
|
switch (encoder->type) {
|
|
|
|
case INTEL_OUTPUT_DP:
|
|
|
|
case INTEL_OUTPUT_EDP:
|
|
|
|
return true;
|
|
|
|
case INTEL_OUTPUT_DDI:
|
|
|
|
/* Skip pure HDMI/DVI DDI encoders */
|
|
|
|
return i915_mmio_reg_valid(enc_to_intel_dp(&encoder->base)->output_reg);
|
|
|
|
default:
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2018-10-12 13:23:11 +07:00
|
|
|
static inline struct intel_lspcon *
|
|
|
|
enc_to_intel_lspcon(struct drm_encoder *encoder)
|
|
|
|
{
|
|
|
|
return &enc_to_dig_port(encoder)->lspcon;
|
|
|
|
}
|
|
|
|
|
2012-10-27 04:05:46 +07:00
|
|
|
static inline struct intel_digital_port *
|
|
|
|
dp_to_dig_port(struct intel_dp *intel_dp)
|
|
|
|
{
|
|
|
|
return container_of(intel_dp, struct intel_digital_port, dp);
|
|
|
|
}
|
|
|
|
|
2016-11-22 02:15:05 +07:00
|
|
|
static inline struct intel_lspcon *
|
|
|
|
dp_to_lspcon(struct intel_dp *intel_dp)
|
|
|
|
{
|
|
|
|
return &dp_to_dig_port(intel_dp)->lspcon;
|
|
|
|
}
|
|
|
|
|
2018-08-28 05:30:20 +07:00
|
|
|
static inline struct drm_i915_private *
|
|
|
|
dp_to_i915(struct intel_dp *intel_dp)
|
|
|
|
{
|
|
|
|
return to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
|
|
|
|
}
|
|
|
|
|
2012-10-27 04:05:46 +07:00
|
|
|
static inline struct intel_digital_port *
|
|
|
|
hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
|
|
|
|
{
|
|
|
|
return container_of(intel_hdmi, struct intel_digital_port, hdmi);
|
2012-10-16 01:51:29 +07:00
|
|
|
}
|
|
|
|
|
drm/i915/gen11: Link nv12 Y and UV planes in the atomic state, v5.
To make NV12 working on icl, we need to update 2 planes simultaneously.
I've chosen to do this in the CRTC step after plane validation is done,
so we know what planes are (in)visible. The linked Y plane will get
updated in intel_plane_update_planes_on_crtc(), by the call to
update_slave, which gets the master's plane_state as argument.
The link requires both planes for atomic_update to work,
so make sure skl_ddb_add_affected_planes() adds both states.
Changes since v1:
- Introduce icl_is_nv12_y_plane(), instead of hardcoding sprite numbers.
- Put all the state updating login in intel_plane_atomic_check_with_state().
- Clean up changes in intel_plane_atomic_check().
Changes since v2:
- Fix intel_atomic_get_old_plane_state() to actually return old state.
- Move visibility changes to preparation patch.
- Only try to find a Y plane on gen11, earlier platforms only require
a single plane.
Changes since v3:
- Fix checkpatch warning about to_intel_crtc() usage.
- Add affected planes from icl_add_linked_planes() before check_planes(),
it's a cleaner way to do this. (Ville)
Changes since v4:
- Clear plane links in icl_check_nv12_planes() for clarity.
- Only pass crtc_state to icl_check_nv12_planes().
- Use for_each_new_intel_plane_in_state() in icl_check_nv12_planes.
- Rename aux to linked. (Ville)
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181022135152.15324-1-maarten.lankhorst@linux.intel.com
[mlankhorst: Change bool slave to u32, to satisfy checkpatch]
[mlankhorst: Add WARN_ON's based on Ville's suggestion]
2018-10-22 20:51:52 +07:00
|
|
|
static inline struct intel_plane_state *
|
|
|
|
intel_atomic_get_plane_state(struct intel_atomic_state *state,
|
|
|
|
struct intel_plane *plane)
|
|
|
|
{
|
|
|
|
struct drm_plane_state *ret =
|
|
|
|
drm_atomic_get_plane_state(&state->base, &plane->base);
|
|
|
|
|
|
|
|
if (IS_ERR(ret))
|
|
|
|
return ERR_CAST(ret);
|
|
|
|
|
|
|
|
return to_intel_plane_state(ret);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline struct intel_plane_state *
|
|
|
|
intel_atomic_get_old_plane_state(struct intel_atomic_state *state,
|
|
|
|
struct intel_plane *plane)
|
|
|
|
{
|
|
|
|
return to_intel_plane_state(drm_atomic_get_old_plane_state(&state->base,
|
|
|
|
&plane->base));
|
|
|
|
}
|
|
|
|
|
2017-08-23 22:22:23 +07:00
|
|
|
static inline struct intel_plane_state *
|
|
|
|
intel_atomic_get_new_plane_state(struct intel_atomic_state *state,
|
|
|
|
struct intel_plane *plane)
|
|
|
|
{
|
|
|
|
return to_intel_plane_state(drm_atomic_get_new_plane_state(&state->base,
|
|
|
|
&plane->base));
|
|
|
|
}
|
|
|
|
|
2017-08-23 22:22:22 +07:00
|
|
|
static inline struct intel_crtc_state *
|
|
|
|
intel_atomic_get_old_crtc_state(struct intel_atomic_state *state,
|
|
|
|
struct intel_crtc *crtc)
|
|
|
|
{
|
|
|
|
return to_intel_crtc_state(drm_atomic_get_old_crtc_state(&state->base,
|
|
|
|
&crtc->base));
|
|
|
|
}
|
|
|
|
|
2017-08-23 22:22:21 +07:00
|
|
|
static inline struct intel_crtc_state *
|
|
|
|
intel_atomic_get_new_crtc_state(struct intel_atomic_state *state,
|
|
|
|
struct intel_crtc *crtc)
|
|
|
|
{
|
|
|
|
return to_intel_crtc_state(drm_atomic_get_new_crtc_state(&state->base,
|
|
|
|
&crtc->base));
|
|
|
|
}
|
|
|
|
|
2014-09-19 23:27:27 +07:00
|
|
|
/* intel_display.c */
|
2019-04-05 18:00:17 +07:00
|
|
|
void intel_plane_destroy(struct drm_plane *plane);
|
2017-06-01 21:36:16 +07:00
|
|
|
void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
|
|
|
|
void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
|
2017-07-18 01:14:03 +07:00
|
|
|
enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc);
|
2017-02-08 01:33:45 +07:00
|
|
|
int vlv_get_hpll_vco(struct drm_i915_private *dev_priv);
|
2016-03-05 02:43:02 +07:00
|
|
|
int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
|
|
|
|
const char *name, u32 reg, int ref_freq);
|
2017-02-08 01:33:05 +07:00
|
|
|
int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
|
|
|
|
const char *name, u32 reg);
|
2016-08-23 21:18:08 +07:00
|
|
|
void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv);
|
|
|
|
void lpt_disable_iclkip(struct drm_i915_private *dev_priv);
|
2016-03-16 18:38:53 +07:00
|
|
|
void intel_init_display_hooks(struct drm_i915_private *dev_priv);
|
drm/i915: Rewrite fb rotation GTT handling
Redo the fb rotation handling in order to:
- eliminate the NV12 special casing
- handle fb->offsets[] properly
- make the rotation handling easier for the plane code
To achieve these goals we reduce intel_rotation_info to only contain
(for each plane) the rotated view width,height,stride in tile units,
and the page offset into the object where the plane starts. Each plane
is handled exactly the same way, no special casing for NV12 or other
formats. We then store the computed rotation_info under
intel_framebuffer so that we don't have to recompute it again.
To handle fb->offsets[] we treat them as a linear offsets and convert
them to x/y offsets from the start of the relevant GTT mapping (either
normal or rotated). We store the x/y offsets under intel_framebuffer,
and for some extra convenience we also store the rotated pitch (ie.
tile aligned plane height). So for each plane we have the normal
x/y offsets, rotated x/y offsets, and the rotated pitch. The normal
pitch is available already in fb->pitches[].
While we're gathering up all that extra information, we can also easily
compute the storage requirements for the framebuffer, so that we can
check that the object is big enough to hold it.
When it comes time to deal with the plane source coordinates, we first
rotate the clipped src coordinates to match the relevant GTT view
orientation, then add to them the fb x/y offsets. Next we compute
the aligned surface page offset, and as a result we're left with some
residual x/y offsets. Finally, if required by the hardware, we convert
the remaining x/y offsets into a linear offset.
For gen2/3 we simply skip computing the final page offset, and just
convert the src+fb x/y offsets directly into a linear offset since
that's what the hardware wants.
After this all platforms, incluing SKL+, compute these things in exactly
the same way (excluding alignemnt differences).
v2: Use BIT(DRM_ROTATE_270) instead of ROTATE_270 when rotating
plane src coordinates
Drop some spurious changes that got left behind during
development
v3: Split out more changes to prep patches (Daniel)
s/intel_fb->plane[].foo.bar/intel_fb->foo[].bar/ for brevity
Rename intel_surf_gtt_offset to intel_fb_gtt_offset
Kill the pointless 'plane' parameter from intel_fb_gtt_offset()
v4: Fix alignment vs. alignment-1 when calling
_intel_compute_tile_offset() from intel_fill_fb_info()
Pass the pitch in tiles in
stad of pixels to intel_adjust_tile_offset() from intel_fill_fb_info()
Pass the full width/height of the rotated area to
drm_rect_rotate() for clarity
Use u32 for more offsets
v5: Preserve the upper_32_bits()/lower_32_bits() handling for the
fb ggtt offset (Sivakumar)
v6: Rebase due to drm_plane_state src/dst rects
Cc: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1470821001-25272-2-git-send-email-ville.syrjala@linux.intel.com
Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-09-15 17:16:41 +07:00
|
|
|
unsigned int intel_fb_xy_to_linear(int x, int y,
|
2016-01-20 23:02:50 +07:00
|
|
|
const struct intel_plane_state *state,
|
|
|
|
int plane);
|
2019-04-05 18:00:05 +07:00
|
|
|
unsigned int intel_fb_align_height(const struct drm_framebuffer *fb,
|
|
|
|
int color_plane, unsigned int height);
|
drm/i915: Rewrite fb rotation GTT handling
Redo the fb rotation handling in order to:
- eliminate the NV12 special casing
- handle fb->offsets[] properly
- make the rotation handling easier for the plane code
To achieve these goals we reduce intel_rotation_info to only contain
(for each plane) the rotated view width,height,stride in tile units,
and the page offset into the object where the plane starts. Each plane
is handled exactly the same way, no special casing for NV12 or other
formats. We then store the computed rotation_info under
intel_framebuffer so that we don't have to recompute it again.
To handle fb->offsets[] we treat them as a linear offsets and convert
them to x/y offsets from the start of the relevant GTT mapping (either
normal or rotated). We store the x/y offsets under intel_framebuffer,
and for some extra convenience we also store the rotated pitch (ie.
tile aligned plane height). So for each plane we have the normal
x/y offsets, rotated x/y offsets, and the rotated pitch. The normal
pitch is available already in fb->pitches[].
While we're gathering up all that extra information, we can also easily
compute the storage requirements for the framebuffer, so that we can
check that the object is big enough to hold it.
When it comes time to deal with the plane source coordinates, we first
rotate the clipped src coordinates to match the relevant GTT view
orientation, then add to them the fb x/y offsets. Next we compute
the aligned surface page offset, and as a result we're left with some
residual x/y offsets. Finally, if required by the hardware, we convert
the remaining x/y offsets into a linear offset.
For gen2/3 we simply skip computing the final page offset, and just
convert the src+fb x/y offsets directly into a linear offset since
that's what the hardware wants.
After this all platforms, incluing SKL+, compute these things in exactly
the same way (excluding alignemnt differences).
v2: Use BIT(DRM_ROTATE_270) instead of ROTATE_270 when rotating
plane src coordinates
Drop some spurious changes that got left behind during
development
v3: Split out more changes to prep patches (Daniel)
s/intel_fb->plane[].foo.bar/intel_fb->foo[].bar/ for brevity
Rename intel_surf_gtt_offset to intel_fb_gtt_offset
Kill the pointless 'plane' parameter from intel_fb_gtt_offset()
v4: Fix alignment vs. alignment-1 when calling
_intel_compute_tile_offset() from intel_fill_fb_info()
Pass the pitch in tiles in
stad of pixels to intel_adjust_tile_offset() from intel_fill_fb_info()
Pass the full width/height of the rotated area to
drm_rect_rotate() for clarity
Use u32 for more offsets
v5: Preserve the upper_32_bits()/lower_32_bits() handling for the
fb ggtt offset (Sivakumar)
v6: Rebase due to drm_plane_state src/dst rects
Cc: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1470821001-25272-2-git-send-email-ville.syrjala@linux.intel.com
Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-09-15 17:16:41 +07:00
|
|
|
void intel_add_fb_offsets(int *x, int *y,
|
2016-01-20 23:02:50 +07:00
|
|
|
const struct intel_plane_state *state, int plane);
|
2016-02-16 03:54:45 +07:00
|
|
|
unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info);
|
2019-05-09 19:21:52 +07:00
|
|
|
unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info);
|
2016-11-29 16:50:08 +07:00
|
|
|
bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv);
|
2016-04-28 18:57:00 +07:00
|
|
|
void intel_mark_busy(struct drm_i915_private *dev_priv);
|
|
|
|
void intel_mark_idle(struct drm_i915_private *dev_priv);
|
2015-07-13 21:30:29 +07:00
|
|
|
int intel_display_suspend(struct drm_device *dev);
|
2016-08-10 18:07:33 +07:00
|
|
|
void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv);
|
2013-09-25 01:48:31 +07:00
|
|
|
void intel_encoder_destroy(struct drm_encoder *encoder);
|
2017-10-09 23:19:50 +07:00
|
|
|
struct drm_display_mode *
|
|
|
|
intel_encoder_current_mode(struct intel_encoder *encoder);
|
2018-10-04 15:50:43 +07:00
|
|
|
bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum port port);
|
2018-05-22 07:25:37 +07:00
|
|
|
bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port port);
|
|
|
|
enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv,
|
|
|
|
enum port port);
|
2018-02-07 23:48:41 +07:00
|
|
|
int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
|
|
|
|
struct drm_file *file_priv);
|
2013-09-25 01:48:31 +07:00
|
|
|
enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
|
|
|
|
enum pipe pipe);
|
2016-06-23 01:57:02 +07:00
|
|
|
static inline bool
|
|
|
|
intel_crtc_has_type(const struct intel_crtc_state *crtc_state,
|
|
|
|
enum intel_output_type type)
|
|
|
|
{
|
|
|
|
return crtc_state->output_types & (1 << type);
|
|
|
|
}
|
2016-06-23 01:57:04 +07:00
|
|
|
static inline bool
|
|
|
|
intel_crtc_has_dp_encoder(const struct intel_crtc_state *crtc_state)
|
|
|
|
{
|
|
|
|
return crtc_state->output_types &
|
2016-06-23 01:57:06 +07:00
|
|
|
((1 << INTEL_OUTPUT_DP) |
|
2016-06-23 01:57:04 +07:00
|
|
|
(1 << INTEL_OUTPUT_DP_MST) |
|
|
|
|
(1 << INTEL_OUTPUT_EDP));
|
|
|
|
}
|
2014-09-15 19:12:21 +07:00
|
|
|
static inline void
|
2016-11-01 03:37:06 +07:00
|
|
|
intel_wait_for_vblank(struct drm_i915_private *dev_priv, enum pipe pipe)
|
2014-09-15 19:12:21 +07:00
|
|
|
{
|
2016-11-01 03:37:06 +07:00
|
|
|
drm_wait_one_vblank(&dev_priv->drm, pipe);
|
2014-09-15 19:12:21 +07:00
|
|
|
}
|
2015-10-31 00:23:22 +07:00
|
|
|
static inline void
|
2016-11-01 03:37:06 +07:00
|
|
|
intel_wait_for_vblank_if_active(struct drm_i915_private *dev_priv, int pipe)
|
2015-10-31 00:23:22 +07:00
|
|
|
{
|
2016-11-01 03:37:09 +07:00
|
|
|
const struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
|
2015-10-31 00:23:22 +07:00
|
|
|
|
|
|
|
if (crtc->active)
|
2016-11-01 03:37:06 +07:00
|
|
|
intel_wait_for_vblank(dev_priv, pipe);
|
2015-10-31 00:23:22 +07:00
|
|
|
}
|
2016-05-17 20:07:48 +07:00
|
|
|
|
|
|
|
u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc);
|
|
|
|
|
2013-09-25 01:48:31 +07:00
|
|
|
int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
|
2013-11-06 13:36:35 +07:00
|
|
|
void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
|
2015-04-10 22:21:31 +07:00
|
|
|
struct intel_digital_port *dport,
|
|
|
|
unsigned int expected_mask);
|
2017-04-07 01:55:20 +07:00
|
|
|
int intel_get_load_detect_pipe(struct drm_connector *connector,
|
2017-05-19 02:38:37 +07:00
|
|
|
const struct drm_display_mode *mode,
|
2017-04-07 01:55:20 +07:00
|
|
|
struct intel_load_detect_pipe *old,
|
|
|
|
struct drm_modeset_acquire_ctx *ctx);
|
2013-09-25 01:48:31 +07:00
|
|
|
void intel_release_load_detect_pipe(struct drm_connector *connector,
|
2015-03-20 21:18:02 +07:00
|
|
|
struct intel_load_detect_pipe *old,
|
|
|
|
struct drm_modeset_acquire_ctx *ctx);
|
2016-08-15 16:49:06 +07:00
|
|
|
struct i915_vma *
|
2018-02-20 20:42:06 +07:00
|
|
|
intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
|
2018-09-07 22:24:06 +07:00
|
|
|
const struct i915_ggtt_view *view,
|
2018-02-22 01:48:07 +07:00
|
|
|
bool uses_fence,
|
2018-02-20 20:42:06 +07:00
|
|
|
unsigned long *out_flags);
|
|
|
|
void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags);
|
2014-02-11 00:00:39 +07:00
|
|
|
struct drm_framebuffer *
|
2017-02-15 17:59:18 +07:00
|
|
|
intel_framebuffer_create(struct drm_i915_gem_object *obj,
|
|
|
|
struct drm_mode_fb_cmd2 *mode_cmd);
|
2014-12-02 06:40:14 +07:00
|
|
|
int intel_prepare_plane_fb(struct drm_plane *plane,
|
2016-08-19 01:00:16 +07:00
|
|
|
struct drm_plane_state *new_state);
|
2014-12-02 22:45:25 +07:00
|
|
|
void intel_cleanup_plane_fb(struct drm_plane *plane,
|
2016-08-19 01:00:16 +07:00
|
|
|
struct drm_plane_state *old_state);
|
2015-01-22 07:35:43 +07:00
|
|
|
int intel_plane_atomic_get_property(struct drm_plane *plane,
|
|
|
|
const struct drm_plane_state *state,
|
|
|
|
struct drm_property *property,
|
2019-01-18 19:01:25 +07:00
|
|
|
u64 *val);
|
2015-01-22 07:35:43 +07:00
|
|
|
int intel_plane_atomic_set_property(struct drm_plane *plane,
|
|
|
|
struct drm_plane_state *state,
|
|
|
|
struct drm_property *property,
|
2019-01-18 19:01:25 +07:00
|
|
|
u64 val);
|
2017-08-23 22:22:23 +07:00
|
|
|
int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state,
|
|
|
|
struct drm_crtc_state *crtc_state,
|
|
|
|
const struct intel_plane_state *old_plane_state,
|
2015-06-15 17:33:44 +07:00
|
|
|
struct drm_plane_state *plane_state);
|
2014-06-26 02:02:02 +07:00
|
|
|
|
2016-03-08 22:46:15 +07:00
|
|
|
void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
|
|
|
|
enum pipe pipe);
|
|
|
|
|
2016-11-01 03:37:07 +07:00
|
|
|
int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
|
2016-01-19 22:25:17 +07:00
|
|
|
const struct dpll *dpll);
|
2016-11-01 03:37:07 +07:00
|
|
|
void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe);
|
2016-02-18 02:41:12 +07:00
|
|
|
int lpt_get_iclkip(struct drm_i915_private *dev_priv);
|
2014-10-28 18:20:22 +07:00
|
|
|
|
2014-06-26 02:02:02 +07:00
|
|
|
/* modesetting asserts */
|
2014-09-19 23:27:27 +07:00
|
|
|
void assert_panel_unlocked(struct drm_i915_private *dev_priv,
|
|
|
|
enum pipe pipe);
|
2013-06-17 02:42:39 +07:00
|
|
|
void assert_pll(struct drm_i915_private *dev_priv,
|
|
|
|
enum pipe pipe, bool state);
|
|
|
|
#define assert_pll_enabled(d, p) assert_pll(d, p, true)
|
|
|
|
#define assert_pll_disabled(d, p) assert_pll(d, p, false)
|
2016-03-16 17:57:14 +07:00
|
|
|
void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state);
|
|
|
|
#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
|
|
|
|
#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
|
2013-06-17 02:42:39 +07:00
|
|
|
void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
|
|
|
|
enum pipe pipe, bool state);
|
|
|
|
#define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
|
|
|
|
#define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
|
2013-09-25 01:48:31 +07:00
|
|
|
void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
|
2011-12-14 04:19:38 +07:00
|
|
|
#define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
|
|
|
|
#define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
|
2016-05-06 21:40:21 +07:00
|
|
|
void intel_prepare_reset(struct drm_i915_private *dev_priv);
|
|
|
|
void intel_finish_reset(struct drm_i915_private *dev_priv);
|
2016-05-14 03:41:21 +07:00
|
|
|
unsigned int skl_cdclk_get_vco(unsigned int freq);
|
2013-09-25 01:48:31 +07:00
|
|
|
void intel_dp_get_m_n(struct intel_crtc *crtc,
|
2015-01-15 19:55:21 +07:00
|
|
|
struct intel_crtc_state *pipe_config);
|
2018-10-11 17:04:49 +07:00
|
|
|
void intel_dp_set_m_n(const struct intel_crtc_state *crtc_state,
|
|
|
|
enum link_m_n_set m_n);
|
2019-05-21 19:17:18 +07:00
|
|
|
void intel_dp_ycbcr_420_enable(struct intel_dp *intel_dp,
|
|
|
|
const struct intel_crtc_state *crtc_state);
|
2013-09-25 01:48:31 +07:00
|
|
|
int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
|
2019-02-08 00:32:22 +07:00
|
|
|
bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state,
|
2016-05-04 16:11:57 +07:00
|
|
|
struct dpll *best_clock);
|
|
|
|
int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
|
2015-06-23 03:35:51 +07:00
|
|
|
|
2016-11-01 03:37:02 +07:00
|
|
|
bool intel_crtc_active(struct intel_crtc *crtc);
|
2017-11-23 01:39:01 +07:00
|
|
|
bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state);
|
2017-11-10 18:35:00 +07:00
|
|
|
void hsw_enable_ips(const struct intel_crtc_state *crtc_state);
|
|
|
|
void hsw_disable_ips(const struct intel_crtc_state *crtc_state);
|
2017-02-22 13:34:27 +07:00
|
|
|
enum intel_display_power_domain intel_port_to_power_domain(enum port port);
|
2018-11-01 21:04:23 +07:00
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enum intel_display_power_domain
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intel_aux_power_domain(struct intel_digital_port *dig_port);
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2014-02-12 06:28:57 +07:00
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void intel_mode_from_pipe_config(struct drm_display_mode *mode,
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2015-01-15 19:55:21 +07:00
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struct intel_crtc_state *pipe_config);
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2018-03-28 17:05:26 +07:00
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void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
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struct intel_crtc_state *crtc_state);
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2015-06-22 14:50:32 +07:00
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2018-10-30 01:18:20 +07:00
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u16 skl_scaler_calc_phase(int sub, int scale, bool chroma_center);
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2015-07-13 21:30:15 +07:00
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int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
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2018-09-07 22:24:09 +07:00
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int skl_max_scale(const struct intel_crtc_state *crtc_state,
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u32 pixel_format);
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2012-01-03 23:05:39 +07:00
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2017-01-16 22:21:27 +07:00
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static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *state)
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{
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return i915_ggtt_offset(state->vma);
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}
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2015-09-21 16:45:35 +07:00
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2017-11-14 01:11:28 +07:00
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u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
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const struct intel_plane_state *plane_state);
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2019-02-05 23:08:36 +07:00
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u32 glk_plane_color_ctl_crtc(const struct intel_crtc_state *crtc_state);
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2017-03-18 04:17:56 +07:00
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u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
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const struct intel_plane_state *plane_state);
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2019-02-05 23:08:36 +07:00
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u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state);
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2018-09-11 22:01:39 +07:00
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u32 skl_plane_stride(const struct intel_plane_state *plane_state,
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int plane);
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2018-09-07 22:24:11 +07:00
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int skl_check_plane_surface(struct intel_plane_state *plane_state);
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2017-03-24 02:27:12 +07:00
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int i9xx_check_plane_surface(struct intel_plane_state *plane_state);
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2018-04-09 10:41:03 +07:00
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int skl_format_to_fourcc(int format, bool rgb_order, bool alpha);
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2018-09-07 22:24:02 +07:00
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unsigned int i9xx_plane_max_stride(struct intel_plane *plane,
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u32 pixel_format, u64 modifier,
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unsigned int rotation);
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2019-05-02 22:11:00 +07:00
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int bdw_get_pipemisc_bpp(struct intel_crtc *crtc);
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2015-03-23 18:10:37 +07:00
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2014-09-30 15:56:38 +07:00
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/* intel_runtime_pm.c */
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2019-05-10 00:34:36 +07:00
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#define BITS_PER_WAKEREF \
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BITS_PER_TYPE(struct_member(struct i915_runtime_pm, wakeref_count))
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#define INTEL_RPM_WAKELOCK_SHIFT (BITS_PER_WAKEREF / 2)
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#define INTEL_RPM_WAKELOCK_BIAS (1 << INTEL_RPM_WAKELOCK_SHIFT)
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#define INTEL_RPM_RAW_WAKEREF_MASK (INTEL_RPM_WAKELOCK_BIAS - 1)
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static inline int
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intel_rpm_raw_wakeref_count(int wakeref_count)
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{
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return wakeref_count & INTEL_RPM_RAW_WAKEREF_MASK;
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}
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static inline int
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intel_rpm_wakelock_count(int wakeref_count)
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{
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return wakeref_count >> INTEL_RPM_WAKELOCK_SHIFT;
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}
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|
2015-12-16 01:10:33 +07:00
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static inline void
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2019-03-26 04:49:35 +07:00
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assert_rpm_device_not_suspended(struct i915_runtime_pm *rpm)
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2015-12-16 01:10:33 +07:00
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{
|
2019-03-26 04:49:35 +07:00
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WARN_ONCE(rpm->suspended,
|
2015-12-16 01:10:33 +07:00
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"Device suspended during HW access\n");
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}
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static inline void
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2019-05-10 00:34:36 +07:00
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____assert_rpm_raw_wakeref_held(struct i915_runtime_pm *rpm, int wakeref_count)
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2015-12-16 01:10:33 +07:00
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|
|
{
|
2019-03-26 04:49:35 +07:00
|
|
|
assert_rpm_device_not_suspended(rpm);
|
2019-05-10 00:34:36 +07:00
|
|
|
WARN_ONCE(!intel_rpm_raw_wakeref_count(wakeref_count),
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|
"RPM raw-wakeref not held\n");
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|
|
|
}
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static inline void
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____assert_rpm_wakelock_held(struct i915_runtime_pm *rpm, int wakeref_count)
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|
|
{
|
|
|
|
____assert_rpm_raw_wakeref_held(rpm, wakeref_count);
|
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|
|
WARN_ONCE(!intel_rpm_wakelock_count(wakeref_count),
|
|
|
|
"RPM wakelock ref not held during HW access\n");
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|
|
|
}
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|
|
static inline void
|
|
|
|
assert_rpm_raw_wakeref_held(struct drm_i915_private *i915)
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|
|
|
{
|
|
|
|
struct i915_runtime_pm *rpm = &i915->runtime_pm;
|
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|
|
|
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|
____assert_rpm_raw_wakeref_held(rpm, atomic_read(&rpm->wakeref_count));
|
|
|
|
}
|
|
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|
|
|
static inline void
|
|
|
|
__assert_rpm_wakelock_held(struct i915_runtime_pm *rpm)
|
|
|
|
{
|
|
|
|
____assert_rpm_wakelock_held(rpm, atomic_read(&rpm->wakeref_count));
|
2015-12-16 01:10:33 +07:00
|
|
|
}
|
|
|
|
|
2019-03-26 04:49:35 +07:00
|
|
|
static inline void
|
|
|
|
assert_rpm_wakelock_held(struct drm_i915_private *i915)
|
|
|
|
{
|
|
|
|
__assert_rpm_wakelock_held(&i915->runtime_pm);
|
|
|
|
}
|
|
|
|
|
2015-12-16 07:52:19 +07:00
|
|
|
/**
|
|
|
|
* disable_rpm_wakeref_asserts - disable the RPM assert checks
|
2019-01-14 21:21:09 +07:00
|
|
|
* @i915: i915 device instance
|
2015-12-16 07:52:19 +07:00
|
|
|
*
|
|
|
|
* This function disable asserts that check if we hold an RPM wakelock
|
|
|
|
* reference, while keeping the device-not-suspended checks still enabled.
|
|
|
|
* It's meant to be used only in special circumstances where our rule about
|
|
|
|
* the wakelock refcount wrt. the device power state doesn't hold. According
|
|
|
|
* to this rule at any point where we access the HW or want to keep the HW in
|
|
|
|
* an active state we must hold an RPM wakelock reference acquired via one of
|
|
|
|
* the intel_runtime_pm_get() helpers. Currently there are a few special spots
|
|
|
|
* where this rule doesn't hold: the IRQ and suspend/resume handlers, the
|
|
|
|
* forcewake release timer, and the GPU RPS and hangcheck works. All other
|
|
|
|
* users should avoid using this function.
|
|
|
|
*
|
|
|
|
* Any calls to this function must have a symmetric call to
|
|
|
|
* enable_rpm_wakeref_asserts().
|
|
|
|
*/
|
|
|
|
static inline void
|
2019-01-14 21:21:09 +07:00
|
|
|
disable_rpm_wakeref_asserts(struct drm_i915_private *i915)
|
2015-12-16 07:52:19 +07:00
|
|
|
{
|
2019-05-10 00:34:36 +07:00
|
|
|
atomic_add(INTEL_RPM_WAKELOCK_BIAS + 1,
|
|
|
|
&i915->runtime_pm.wakeref_count);
|
2015-12-16 07:52:19 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* enable_rpm_wakeref_asserts - re-enable the RPM assert checks
|
2019-01-14 21:21:09 +07:00
|
|
|
* @i915: i915 device instance
|
2015-12-16 07:52:19 +07:00
|
|
|
*
|
|
|
|
* This function re-enables the RPM assert checks after disabling them with
|
|
|
|
* disable_rpm_wakeref_asserts. It's meant to be used only in special
|
|
|
|
* circumstances otherwise its use should be avoided.
|
|
|
|
*
|
|
|
|
* Any calls to this function must have a symmetric call to
|
|
|
|
* disable_rpm_wakeref_asserts().
|
|
|
|
*/
|
|
|
|
static inline void
|
2019-01-14 21:21:09 +07:00
|
|
|
enable_rpm_wakeref_asserts(struct drm_i915_private *i915)
|
2015-12-16 07:52:19 +07:00
|
|
|
{
|
2019-05-10 00:34:36 +07:00
|
|
|
atomic_sub(INTEL_RPM_WAKELOCK_BIAS + 1,
|
|
|
|
&i915->runtime_pm.wakeref_count);
|
2015-12-16 07:52:19 +07:00
|
|
|
}
|
|
|
|
|
DRM: i915: add mode setting support
This commit adds i915 driver support for the DRM mode setting APIs.
Currently, VGA, LVDS, SDVO DVI & VGA, TV and DVO LVDS outputs are
supported. HDMI, DisplayPort and additional SDVO output support will
follow.
Support for the mode setting code is controlled by the new 'modeset'
module option. A new config option, CONFIG_DRM_I915_KMS controls the
default behavior, and whether a PCI ID list is built into the module for
use by user level module utilities.
Note that if mode setting is enabled, user level drivers that access
display registers directly or that don't use the kernel graphics memory
manager will likely corrupt kernel graphics memory, disrupt output
configuration (possibly leading to hangs and/or blank displays), and
prevent panic/oops messages from appearing. So use caution when
enabling this code; be sure your user level code supports the new
interfaces.
A new SysRq key, 'g', provides emergency support for switching back to
the kernel's framebuffer console; which is useful for testing.
Co-authors: Dave Airlie <airlied@linux.ie>, Hong Liu <hong.liu@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2008-11-08 05:24:08 +07:00
|
|
|
#endif /* __INTEL_DRV_H__ */
|