License cleanup: add SPDX GPL-2.0 license identifier to files with no license
Many source files in the tree are missing licensing information, which
makes it harder for compliance tools to determine the correct license.
By default all files without license information are under the default
license of the kernel, which is GPL version 2.
Update the files which contain no license information with the 'GPL-2.0'
SPDX license identifier. The SPDX identifier is a legally binding
shorthand, which can be used instead of the full boiler plate text.
This patch is based on work done by Thomas Gleixner and Kate Stewart and
Philippe Ombredanne.
How this work was done:
Patches were generated and checked against linux-4.14-rc6 for a subset of
the use cases:
- file had no licensing information it it.
- file was a */uapi/* one with no licensing information in it,
- file was a */uapi/* one with existing licensing information,
Further patches will be generated in subsequent months to fix up cases
where non-standard license headers were used, and references to license
had to be inferred by heuristics based on keywords.
The analysis to determine which SPDX License Identifier to be applied to
a file was done in a spreadsheet of side by side results from of the
output of two independent scanners (ScanCode & Windriver) producing SPDX
tag:value files created by Philippe Ombredanne. Philippe prepared the
base worksheet, and did an initial spot review of a few 1000 files.
The 4.13 kernel was the starting point of the analysis with 60,537 files
assessed. Kate Stewart did a file by file comparison of the scanner
results in the spreadsheet to determine which SPDX license identifier(s)
to be applied to the file. She confirmed any determination that was not
immediately clear with lawyers working with the Linux Foundation.
Criteria used to select files for SPDX license identifier tagging was:
- Files considered eligible had to be source code files.
- Make and config files were included as candidates if they contained >5
lines of source
- File already had some variant of a license header in it (even if <5
lines).
All documentation files were explicitly excluded.
The following heuristics were used to determine which SPDX license
identifiers to apply.
- when both scanners couldn't find any license traces, file was
considered to have no license information in it, and the top level
COPYING file license applied.
For non */uapi/* files that summary was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 11139
and resulted in the first patch in this series.
If that file was a */uapi/* path one, it was "GPL-2.0 WITH
Linux-syscall-note" otherwise it was "GPL-2.0". Results of that was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 WITH Linux-syscall-note 930
and resulted in the second patch in this series.
- if a file had some form of licensing information in it, and was one
of the */uapi/* ones, it was denoted with the Linux-syscall-note if
any GPL family license was found in the file or had no licensing in
it (per prior point). Results summary:
SPDX license identifier # files
---------------------------------------------------|------
GPL-2.0 WITH Linux-syscall-note 270
GPL-2.0+ WITH Linux-syscall-note 169
((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) 21
((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 17
LGPL-2.1+ WITH Linux-syscall-note 15
GPL-1.0+ WITH Linux-syscall-note 14
((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) 5
LGPL-2.0+ WITH Linux-syscall-note 4
LGPL-2.1 WITH Linux-syscall-note 3
((GPL-2.0 WITH Linux-syscall-note) OR MIT) 3
((GPL-2.0 WITH Linux-syscall-note) AND MIT) 1
and that resulted in the third patch in this series.
- when the two scanners agreed on the detected license(s), that became
the concluded license(s).
- when there was disagreement between the two scanners (one detected a
license but the other didn't, or they both detected different
licenses) a manual inspection of the file occurred.
- In most cases a manual inspection of the information in the file
resulted in a clear resolution of the license that should apply (and
which scanner probably needed to revisit its heuristics).
- When it was not immediately clear, the license identifier was
confirmed with lawyers working with the Linux Foundation.
- If there was any question as to the appropriate license identifier,
the file was flagged for further research and to be revisited later
in time.
In total, over 70 hours of logged manual review was done on the
spreadsheet to determine the SPDX license identifiers to apply to the
source files by Kate, Philippe, Thomas and, in some cases, confirmation
by lawyers working with the Linux Foundation.
Kate also obtained a third independent scan of the 4.13 code base from
FOSSology, and compared selected files where the other two scanners
disagreed against that SPDX file, to see if there was new insights. The
Windriver scanner is based on an older version of FOSSology in part, so
they are related.
Thomas did random spot checks in about 500 files from the spreadsheets
for the uapi headers and agreed with SPDX license identifier in the
files he inspected. For the non-uapi files Thomas did random spot checks
in about 15000 files.
In initial set of patches against 4.14-rc6, 3 files were found to have
copy/paste license identifier errors, and have been fixed to reflect the
correct identifier.
Additionally Philippe spent 10 hours this week doing a detailed manual
inspection and review of the 12,461 patched files from the initial patch
version early this week with:
- a full scancode scan run, collecting the matched texts, detected
license ids and scores
- reviewing anything where there was a license detected (about 500+
files) to ensure that the applied SPDX license was correct
- reviewing anything where there was no detection but the patch license
was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied
SPDX license was correct
This produced a worksheet with 20 files needing minor correction. This
worksheet was then exported into 3 different .csv files for the
different types of files to be modified.
These .csv files were then reviewed by Greg. Thomas wrote a script to
parse the csv files and add the proper SPDX tag to the file, in the
format that the file expected. This script was further refined by Greg
based on the output to detect more types of files automatically and to
distinguish between header and source .c files (which need different
comment types.) Finally Greg ran the script using the .csv files to
generate the patches.
Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-11-01 21:07:57 +07:00
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// SPDX-License-Identifier: GPL-2.0
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2013-05-22 23:45:32 +07:00
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#include <dt-bindings/clock/tegra20-car.h>
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2013-02-13 07:25:15 +07:00
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#include <dt-bindings/gpio/tegra-gpio.h>
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2013-12-05 17:44:08 +07:00
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#include <dt-bindings/pinctrl/pinctrl-tegra.h>
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2013-02-14 02:51:51 +07:00
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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2013-02-13 07:25:15 +07:00
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2012-10-18 05:38:21 +07:00
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#include "skeleton.dtsi"
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2011-07-20 06:26:54 +07:00
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/ {
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compatible = "nvidia,tegra20";
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2015-03-11 22:43:01 +07:00
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interrupt-parent = <&lic>;
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2011-07-20 06:26:54 +07:00
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2013-11-26 07:53:16 +07:00
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host1x@50000000 {
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2012-11-16 04:07:54 +07:00
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compatible = "nvidia,tegra20-host1x", "simple-bus";
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reg = <0x50000000 0x00024000>;
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2013-02-14 02:51:51 +07:00
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interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
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<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
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2013-05-22 23:45:32 +07:00
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clocks = <&tegra_car TEGRA20_CLK_HOST1X>;
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2013-11-07 04:01:16 +07:00
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resets = <&tegra_car 28>;
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reset-names = "host1x";
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2012-11-16 04:07:54 +07:00
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x54000000 0x54000000 0x04000000>;
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2013-11-26 07:53:16 +07:00
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mpe@54040000 {
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2012-11-16 04:07:54 +07:00
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compatible = "nvidia,tegra20-mpe";
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reg = <0x54040000 0x00040000>;
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2013-02-14 02:51:51 +07:00
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interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
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2013-05-22 23:45:32 +07:00
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clocks = <&tegra_car TEGRA20_CLK_MPE>;
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2013-11-07 04:01:16 +07:00
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resets = <&tegra_car 60>;
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reset-names = "mpe";
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2012-11-16 04:07:54 +07:00
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};
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2013-11-26 07:53:16 +07:00
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vi@54080000 {
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2012-11-16 04:07:54 +07:00
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compatible = "nvidia,tegra20-vi";
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reg = <0x54080000 0x00040000>;
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2013-02-14 02:51:51 +07:00
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interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
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2013-05-22 23:45:32 +07:00
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clocks = <&tegra_car TEGRA20_CLK_VI>;
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2013-11-07 04:01:16 +07:00
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resets = <&tegra_car 20>;
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reset-names = "vi";
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2012-11-16 04:07:54 +07:00
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};
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2013-11-26 07:53:16 +07:00
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epp@540c0000 {
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2012-11-16 04:07:54 +07:00
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compatible = "nvidia,tegra20-epp";
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reg = <0x540c0000 0x00040000>;
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2013-02-14 02:51:51 +07:00
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interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
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2013-05-22 23:45:32 +07:00
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clocks = <&tegra_car TEGRA20_CLK_EPP>;
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2013-11-07 04:01:16 +07:00
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resets = <&tegra_car 19>;
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reset-names = "epp";
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2012-11-16 04:07:54 +07:00
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};
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2013-11-26 07:53:16 +07:00
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isp@54100000 {
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2012-11-16 04:07:54 +07:00
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compatible = "nvidia,tegra20-isp";
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reg = <0x54100000 0x00040000>;
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2013-02-14 02:51:51 +07:00
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interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
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2013-05-22 23:45:32 +07:00
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clocks = <&tegra_car TEGRA20_CLK_ISP>;
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2013-11-07 04:01:16 +07:00
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resets = <&tegra_car 23>;
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reset-names = "isp";
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2012-11-16 04:07:54 +07:00
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};
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2013-11-26 07:53:16 +07:00
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gr2d@54140000 {
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2012-11-16 04:07:54 +07:00
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compatible = "nvidia,tegra20-gr2d";
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reg = <0x54140000 0x00040000>;
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2013-02-14 02:51:51 +07:00
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interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
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2013-05-22 23:45:32 +07:00
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clocks = <&tegra_car TEGRA20_CLK_GR2D>;
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2013-11-07 04:01:16 +07:00
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resets = <&tegra_car 21>;
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reset-names = "2d";
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2012-11-16 04:07:54 +07:00
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};
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2014-12-12 22:19:19 +07:00
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gr3d@54180000 {
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2012-11-16 04:07:54 +07:00
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compatible = "nvidia,tegra20-gr3d";
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2014-12-12 22:19:19 +07:00
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reg = <0x54180000 0x00040000>;
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2013-05-22 23:45:32 +07:00
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clocks = <&tegra_car TEGRA20_CLK_GR3D>;
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2013-11-07 04:01:16 +07:00
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resets = <&tegra_car 24>;
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reset-names = "3d";
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2012-11-16 04:07:54 +07:00
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};
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dc@54200000 {
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compatible = "nvidia,tegra20-dc";
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reg = <0x54200000 0x00040000>;
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2013-02-14 02:51:51 +07:00
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interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
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2013-05-22 23:45:32 +07:00
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clocks = <&tegra_car TEGRA20_CLK_DISP1>,
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<&tegra_car TEGRA20_CLK_PLL_P>;
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2013-11-07 04:00:25 +07:00
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clock-names = "dc", "parent";
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2013-11-07 04:01:16 +07:00
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resets = <&tegra_car 27>;
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reset-names = "dc";
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2012-11-16 04:07:54 +07:00
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2014-02-19 05:03:31 +07:00
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nvidia,head = <0>;
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2012-11-16 04:07:54 +07:00
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rgb {
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status = "disabled";
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};
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};
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dc@54240000 {
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compatible = "nvidia,tegra20-dc";
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reg = <0x54240000 0x00040000>;
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2013-02-14 02:51:51 +07:00
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interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
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2013-05-22 23:45:32 +07:00
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clocks = <&tegra_car TEGRA20_CLK_DISP2>,
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<&tegra_car TEGRA20_CLK_PLL_P>;
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2013-11-07 04:00:25 +07:00
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clock-names = "dc", "parent";
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2013-11-07 04:01:16 +07:00
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resets = <&tegra_car 26>;
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reset-names = "dc";
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2012-11-16 04:07:54 +07:00
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2014-02-19 05:03:31 +07:00
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nvidia,head = <1>;
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2012-11-16 04:07:54 +07:00
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rgb {
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status = "disabled";
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};
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};
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2013-11-26 07:53:16 +07:00
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hdmi@54280000 {
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2012-11-16 04:07:54 +07:00
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compatible = "nvidia,tegra20-hdmi";
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reg = <0x54280000 0x00040000>;
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2013-02-14 02:51:51 +07:00
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interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
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2013-05-22 23:45:32 +07:00
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clocks = <&tegra_car TEGRA20_CLK_HDMI>,
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<&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
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2013-01-11 15:01:21 +07:00
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clock-names = "hdmi", "parent";
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2013-11-07 04:01:16 +07:00
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resets = <&tegra_car 51>;
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reset-names = "hdmi";
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2012-11-16 04:07:54 +07:00
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status = "disabled";
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};
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2013-11-26 07:53:16 +07:00
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tvo@542c0000 {
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2012-11-16 04:07:54 +07:00
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compatible = "nvidia,tegra20-tvo";
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reg = <0x542c0000 0x00040000>;
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2013-02-14 02:51:51 +07:00
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interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
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2013-05-22 23:45:32 +07:00
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clocks = <&tegra_car TEGRA20_CLK_TVO>;
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2012-11-16 04:07:54 +07:00
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status = "disabled";
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};
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2014-12-12 22:19:19 +07:00
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dsi@54300000 {
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2012-11-16 04:07:54 +07:00
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compatible = "nvidia,tegra20-dsi";
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2014-12-12 22:19:19 +07:00
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reg = <0x54300000 0x00040000>;
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2013-05-22 23:45:32 +07:00
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clocks = <&tegra_car TEGRA20_CLK_DSI>;
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2013-11-07 04:01:16 +07:00
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resets = <&tegra_car 48>;
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reset-names = "dsi";
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2012-11-16 04:07:54 +07:00
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status = "disabled";
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};
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};
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2015-01-08 19:24:33 +07:00
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timer@50040600 {
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2012-09-20 03:17:24 +07:00
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compatible = "arm,cortex-a9-twd-timer";
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2015-03-11 22:43:01 +07:00
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interrupt-parent = <&intc>;
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2012-09-20 03:17:24 +07:00
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reg = <0x50040600 0x20>;
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2013-02-14 02:51:51 +07:00
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interrupts = <GIC_PPI 13
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2016-03-17 21:19:05 +07:00
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(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
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2013-05-22 23:45:32 +07:00
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clocks = <&tegra_car TEGRA20_CLK_TWD>;
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2012-09-20 03:17:24 +07:00
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};
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2013-11-26 07:53:16 +07:00
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intc: interrupt-controller@50041000 {
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2011-11-30 08:29:19 +07:00
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compatible = "arm,cortex-a9-gic";
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2012-05-12 05:26:03 +07:00
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reg = <0x50041000 0x1000
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0x50040100 0x0100>;
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2012-05-12 06:12:52 +07:00
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interrupt-controller;
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#interrupt-cells = <3>;
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2015-03-11 22:43:01 +07:00
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interrupt-parent = <&intc>;
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2011-07-20 06:26:54 +07:00
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};
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2013-11-26 07:53:16 +07:00
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cache-controller@50043000 {
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2013-01-15 00:09:16 +07:00
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compatible = "arm,pl310-cache";
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reg = <0x50043000 0x1000>;
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arm,data-latency = <5 5 2>;
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arm,tag-latency = <4 4 2>;
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cache-unified;
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cache-level = <2>;
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};
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2015-03-11 22:43:01 +07:00
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lic: interrupt-controller@60004000 {
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compatible = "nvidia,tegra20-ictlr";
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reg = <0x60004000 0x100>,
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<0x60004100 0x50>,
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<0x60004200 0x50>,
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<0x60004300 0x50>;
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interrupt-controller;
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#interrupt-cells = <3>;
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interrupt-parent = <&intc>;
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};
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2012-09-20 01:02:31 +07:00
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timer@60005000 {
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compatible = "nvidia,tegra20-timer";
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reg = <0x60005000 0x60>;
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2013-02-14 02:51:51 +07:00
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interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
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2013-05-22 23:45:32 +07:00
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clocks = <&tegra_car TEGRA20_CLK_TIMER>;
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2012-09-20 01:02:31 +07:00
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};
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2013-11-26 07:53:16 +07:00
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tegra_car: clock@60006000 {
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2013-01-11 14:46:22 +07:00
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|
|
compatible = "nvidia,tegra20-car";
|
|
|
|
|
reg = <0x60006000 0x1000>;
|
|
|
|
|
#clock-cells = <1>;
|
2013-11-07 04:01:16 +07:00
|
|
|
#reset-cells = <1>;
|
2013-01-11 14:46:22 +07:00
|
|
|
};
|
|
|
|
|
|
2014-08-26 13:14:03 +07:00
|
|
|
flow-controller@60007000 {
|
|
|
|
|
compatible = "nvidia,tegra20-flowctrl";
|
|
|
|
|
reg = <0x60007000 0x1000>;
|
|
|
|
|
};
|
|
|
|
|
|
2013-11-26 07:53:16 +07:00
|
|
|
apbdma: dma@6000a000 {
|
2012-01-12 06:09:54 +07:00
|
|
|
compatible = "nvidia,tegra20-apbdma";
|
|
|
|
|
reg = <0x6000a000 0x1200>;
|
2013-02-14 02:51:51 +07:00
|
|
|
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
|
2013-05-22 23:45:32 +07:00
|
|
|
clocks = <&tegra_car TEGRA20_CLK_APBDMA>;
|
2013-11-07 04:01:16 +07:00
|
|
|
resets = <&tegra_car 34>;
|
|
|
|
|
reset-names = "dma";
|
2013-11-12 03:05:59 +07:00
|
|
|
#dma-cells = <1>;
|
2012-01-12 06:09:54 +07:00
|
|
|
};
|
|
|
|
|
|
2015-08-08 20:58:12 +07:00
|
|
|
ahb@6000c000 {
|
2012-05-12 06:03:26 +07:00
|
|
|
compatible = "nvidia,tegra20-ahb";
|
2015-08-08 20:58:12 +07:00
|
|
|
reg = <0x6000c000 0x110>; /* AHB Arbitration + Gizmo Controller */
|
2011-07-20 06:26:54 +07:00
|
|
|
};
|
|
|
|
|
|
2013-11-26 07:53:16 +07:00
|
|
|
gpio: gpio@6000d000 {
|
2011-07-20 06:26:54 +07:00
|
|
|
compatible = "nvidia,tegra20-gpio";
|
2012-05-12 05:11:38 +07:00
|
|
|
reg = <0x6000d000 0x1000>;
|
2013-02-14 02:51:51 +07:00
|
|
|
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
|
2011-07-20 06:26:54 +07:00
|
|
|
#gpio-cells = <2>;
|
|
|
|
|
gpio-controller;
|
2012-01-04 15:39:37 +07:00
|
|
|
#interrupt-cells = <2>;
|
|
|
|
|
interrupt-controller;
|
2015-10-09 22:51:47 +07:00
|
|
|
/*
|
2015-07-14 15:29:56 +07:00
|
|
|
gpio-ranges = <&pinmux 0 0 224>;
|
2015-10-09 22:51:47 +07:00
|
|
|
*/
|
2011-07-20 06:26:54 +07:00
|
|
|
};
|
|
|
|
|
|
2014-06-12 22:36:38 +07:00
|
|
|
apbmisc@70000800 {
|
|
|
|
|
compatible = "nvidia,tegra20-apbmisc";
|
|
|
|
|
reg = <0x70000800 0x64 /* Chip revision */
|
|
|
|
|
0x70000008 0x04>; /* Strapping options */
|
|
|
|
|
};
|
|
|
|
|
|
2013-11-26 07:53:16 +07:00
|
|
|
pinmux: pinmux@70000014 {
|
2011-10-12 05:16:13 +07:00
|
|
|
compatible = "nvidia,tegra20-pinmux";
|
2012-05-12 05:11:38 +07:00
|
|
|
reg = <0x70000014 0x10 /* Tri-state registers */
|
|
|
|
|
0x70000080 0x20 /* Mux registers */
|
|
|
|
|
0x700000a0 0x14 /* Pull-up/down registers */
|
|
|
|
|
0x70000868 0xa8>; /* Pad control registers */
|
2011-10-12 05:16:13 +07:00
|
|
|
};
|
|
|
|
|
|
2013-11-26 07:53:16 +07:00
|
|
|
das@70000c00 {
|
2012-05-12 06:03:26 +07:00
|
|
|
compatible = "nvidia,tegra20-das";
|
|
|
|
|
reg = <0x70000c00 0x80>;
|
|
|
|
|
};
|
2013-03-07 01:28:32 +07:00
|
|
|
|
2013-11-26 07:53:16 +07:00
|
|
|
tegra_ac97: ac97@70002000 {
|
2013-01-05 08:18:44 +07:00
|
|
|
compatible = "nvidia,tegra20-ac97";
|
|
|
|
|
reg = <0x70002000 0x200>;
|
2013-02-14 02:51:51 +07:00
|
|
|
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
|
2013-05-22 23:45:32 +07:00
|
|
|
clocks = <&tegra_car TEGRA20_CLK_AC97>;
|
2013-11-07 04:01:16 +07:00
|
|
|
resets = <&tegra_car 3>;
|
|
|
|
|
reset-names = "ac97";
|
2013-11-12 03:05:59 +07:00
|
|
|
dmas = <&apbdma 12>, <&apbdma 12>;
|
|
|
|
|
dma-names = "rx", "tx";
|
2013-01-05 08:18:44 +07:00
|
|
|
status = "disabled";
|
|
|
|
|
};
|
2012-05-12 06:03:26 +07:00
|
|
|
|
|
|
|
|
tegra_i2s1: i2s@70002800 {
|
|
|
|
|
compatible = "nvidia,tegra20-i2s";
|
|
|
|
|
reg = <0x70002800 0x200>;
|
2013-02-14 02:51:51 +07:00
|
|
|
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
|
2013-05-22 23:45:32 +07:00
|
|
|
clocks = <&tegra_car TEGRA20_CLK_I2S1>;
|
2013-11-07 04:01:16 +07:00
|
|
|
resets = <&tegra_car 11>;
|
|
|
|
|
reset-names = "i2s";
|
2013-11-12 03:05:59 +07:00
|
|
|
dmas = <&apbdma 2>, <&apbdma 2>;
|
|
|
|
|
dma-names = "rx", "tx";
|
2012-06-12 02:09:45 +07:00
|
|
|
status = "disabled";
|
2012-05-12 06:03:26 +07:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
tegra_i2s2: i2s@70002a00 {
|
|
|
|
|
compatible = "nvidia,tegra20-i2s";
|
|
|
|
|
reg = <0x70002a00 0x200>;
|
2013-02-14 02:51:51 +07:00
|
|
|
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
|
2013-05-22 23:45:32 +07:00
|
|
|
clocks = <&tegra_car TEGRA20_CLK_I2S2>;
|
2013-11-07 04:01:16 +07:00
|
|
|
resets = <&tegra_car 18>;
|
|
|
|
|
reset-names = "i2s";
|
2013-11-12 03:05:59 +07:00
|
|
|
dmas = <&apbdma 1>, <&apbdma 1>;
|
|
|
|
|
dma-names = "rx", "tx";
|
2012-06-12 02:09:45 +07:00
|
|
|
status = "disabled";
|
2012-05-12 06:03:26 +07:00
|
|
|
};
|
|
|
|
|
|
2012-12-19 13:31:11 +07:00
|
|
|
/*
|
|
|
|
|
* There are two serial driver i.e. 8250 based simple serial
|
|
|
|
|
* driver and APB DMA based serial driver for higher baudrate
|
|
|
|
|
* and performace. To enable the 8250 based driver, the compatible
|
|
|
|
|
* is "nvidia,tegra20-uart" and to enable the APB DMA based serial
|
2016-01-26 23:59:17 +07:00
|
|
|
* driver, the compatible is "nvidia,tegra20-hsuart".
|
2012-12-19 13:31:11 +07:00
|
|
|
*/
|
|
|
|
|
uarta: serial@70006000 {
|
2011-07-20 06:26:54 +07:00
|
|
|
compatible = "nvidia,tegra20-uart";
|
|
|
|
|
reg = <0x70006000 0x40>;
|
|
|
|
|
reg-shift = <2>;
|
2013-02-14 02:51:51 +07:00
|
|
|
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
|
2013-05-22 23:45:32 +07:00
|
|
|
clocks = <&tegra_car TEGRA20_CLK_UARTA>;
|
2013-11-07 04:01:16 +07:00
|
|
|
resets = <&tegra_car 6>;
|
|
|
|
|
reset-names = "serial";
|
2013-11-12 03:05:59 +07:00
|
|
|
dmas = <&apbdma 8>, <&apbdma 8>;
|
|
|
|
|
dma-names = "rx", "tx";
|
2012-06-12 02:09:45 +07:00
|
|
|
status = "disabled";
|
2011-07-20 06:26:54 +07:00
|
|
|
};
|
|
|
|
|
|
2012-12-19 13:31:11 +07:00
|
|
|
uartb: serial@70006040 {
|
2011-07-20 06:26:54 +07:00
|
|
|
compatible = "nvidia,tegra20-uart";
|
|
|
|
|
reg = <0x70006040 0x40>;
|
|
|
|
|
reg-shift = <2>;
|
2013-02-14 02:51:51 +07:00
|
|
|
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
|
2013-05-22 23:45:32 +07:00
|
|
|
clocks = <&tegra_car TEGRA20_CLK_UARTB>;
|
2013-11-07 04:01:16 +07:00
|
|
|
resets = <&tegra_car 7>;
|
|
|
|
|
reset-names = "serial";
|
2013-11-12 03:05:59 +07:00
|
|
|
dmas = <&apbdma 9>, <&apbdma 9>;
|
|
|
|
|
dma-names = "rx", "tx";
|
2012-06-12 02:09:45 +07:00
|
|
|
status = "disabled";
|
2011-07-20 06:26:54 +07:00
|
|
|
};
|
|
|
|
|
|
2012-12-19 13:31:11 +07:00
|
|
|
uartc: serial@70006200 {
|
2011-07-20 06:26:54 +07:00
|
|
|
compatible = "nvidia,tegra20-uart";
|
|
|
|
|
reg = <0x70006200 0x100>;
|
|
|
|
|
reg-shift = <2>;
|
2013-02-14 02:51:51 +07:00
|
|
|
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
|
2013-05-22 23:45:32 +07:00
|
|
|
clocks = <&tegra_car TEGRA20_CLK_UARTC>;
|
2013-11-07 04:01:16 +07:00
|
|
|
resets = <&tegra_car 55>;
|
|
|
|
|
reset-names = "serial";
|
2013-11-12 03:05:59 +07:00
|
|
|
dmas = <&apbdma 10>, <&apbdma 10>;
|
|
|
|
|
dma-names = "rx", "tx";
|
2012-06-12 02:09:45 +07:00
|
|
|
status = "disabled";
|
2011-07-20 06:26:54 +07:00
|
|
|
};
|
|
|
|
|
|
2012-12-19 13:31:11 +07:00
|
|
|
uartd: serial@70006300 {
|
2011-07-20 06:26:54 +07:00
|
|
|
compatible = "nvidia,tegra20-uart";
|
|
|
|
|
reg = <0x70006300 0x100>;
|
|
|
|
|
reg-shift = <2>;
|
2013-02-14 02:51:51 +07:00
|
|
|
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
|
2013-05-22 23:45:32 +07:00
|
|
|
clocks = <&tegra_car TEGRA20_CLK_UARTD>;
|
2013-11-07 04:01:16 +07:00
|
|
|
resets = <&tegra_car 65>;
|
|
|
|
|
reset-names = "serial";
|
2013-11-12 03:05:59 +07:00
|
|
|
dmas = <&apbdma 19>, <&apbdma 19>;
|
|
|
|
|
dma-names = "rx", "tx";
|
2012-06-12 02:09:45 +07:00
|
|
|
status = "disabled";
|
2011-07-20 06:26:54 +07:00
|
|
|
};
|
|
|
|
|
|
2012-12-19 13:31:11 +07:00
|
|
|
uarte: serial@70006400 {
|
2011-07-20 06:26:54 +07:00
|
|
|
compatible = "nvidia,tegra20-uart";
|
|
|
|
|
reg = <0x70006400 0x100>;
|
|
|
|
|
reg-shift = <2>;
|
2013-02-14 02:51:51 +07:00
|
|
|
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
|
2013-05-22 23:45:32 +07:00
|
|
|
clocks = <&tegra_car TEGRA20_CLK_UARTE>;
|
2013-11-07 04:01:16 +07:00
|
|
|
resets = <&tegra_car 66>;
|
|
|
|
|
reset-names = "serial";
|
2013-11-12 03:05:59 +07:00
|
|
|
dmas = <&apbdma 20>, <&apbdma 20>;
|
|
|
|
|
dma-names = "rx", "tx";
|
2012-06-12 02:09:45 +07:00
|
|
|
status = "disabled";
|
2011-07-20 06:26:54 +07:00
|
|
|
};
|
|
|
|
|
|
2016-11-07 15:30:04 +07:00
|
|
|
gmi@70009000 {
|
|
|
|
|
compatible = "nvidia,tegra20-gmi";
|
|
|
|
|
reg = <0x70009000 0x1000>;
|
|
|
|
|
#address-cells = <2>;
|
|
|
|
|
#size-cells = <1>;
|
|
|
|
|
ranges = <0 0 0xd0000000 0xfffffff>;
|
|
|
|
|
clocks = <&tegra_car TEGRA20_CLK_NOR>;
|
|
|
|
|
clock-names = "gmi";
|
|
|
|
|
resets = <&tegra_car 42>;
|
|
|
|
|
reset-names = "gmi";
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
2013-11-26 07:53:16 +07:00
|
|
|
pwm: pwm@7000a000 {
|
2011-12-21 14:04:13 +07:00
|
|
|
compatible = "nvidia,tegra20-pwm";
|
|
|
|
|
reg = <0x7000a000 0x100>;
|
|
|
|
|
#pwm-cells = <2>;
|
2013-05-22 23:45:32 +07:00
|
|
|
clocks = <&tegra_car TEGRA20_CLK_PWM>;
|
2013-11-07 04:01:16 +07:00
|
|
|
resets = <&tegra_car 17>;
|
|
|
|
|
reset-names = "pwm";
|
2013-03-13 06:40:51 +07:00
|
|
|
status = "disabled";
|
2011-12-21 14:04:13 +07:00
|
|
|
};
|
|
|
|
|
|
2013-11-26 07:53:16 +07:00
|
|
|
rtc@7000e000 {
|
2012-09-20 01:13:16 +07:00
|
|
|
compatible = "nvidia,tegra20-rtc";
|
|
|
|
|
reg = <0x7000e000 0x100>;
|
2013-02-14 02:51:51 +07:00
|
|
|
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
|
2013-05-22 23:45:32 +07:00
|
|
|
clocks = <&tegra_car TEGRA20_CLK_RTC>;
|
2012-09-20 01:13:16 +07:00
|
|
|
};
|
|
|
|
|
|
2012-05-12 06:03:26 +07:00
|
|
|
i2c@7000c000 {
|
|
|
|
|
compatible = "nvidia,tegra20-i2c";
|
|
|
|
|
reg = <0x7000c000 0x100>;
|
2013-02-14 02:51:51 +07:00
|
|
|
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
|
2012-05-12 06:12:52 +07:00
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
2013-05-22 23:45:32 +07:00
|
|
|
clocks = <&tegra_car TEGRA20_CLK_I2C1>,
|
|
|
|
|
<&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
|
2013-01-11 15:01:21 +07:00
|
|
|
clock-names = "div-clk", "fast-clk";
|
2013-11-07 04:01:16 +07:00
|
|
|
resets = <&tegra_car 12>;
|
|
|
|
|
reset-names = "i2c";
|
2013-11-12 03:05:59 +07:00
|
|
|
dmas = <&apbdma 21>, <&apbdma 21>;
|
|
|
|
|
dma-names = "rx", "tx";
|
2012-06-12 02:09:45 +07:00
|
|
|
status = "disabled";
|
2011-10-13 16:14:55 +07:00
|
|
|
};
|
|
|
|
|
|
2012-11-13 12:03:39 +07:00
|
|
|
spi@7000c380 {
|
|
|
|
|
compatible = "nvidia,tegra20-sflash";
|
|
|
|
|
reg = <0x7000c380 0x80>;
|
2013-02-14 02:51:51 +07:00
|
|
|
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
|
2012-11-13 12:03:39 +07:00
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
2013-05-22 23:45:32 +07:00
|
|
|
clocks = <&tegra_car TEGRA20_CLK_SPI>;
|
2013-11-07 04:01:16 +07:00
|
|
|
resets = <&tegra_car 43>;
|
|
|
|
|
reset-names = "spi";
|
2013-11-12 03:05:59 +07:00
|
|
|
dmas = <&apbdma 11>, <&apbdma 11>;
|
|
|
|
|
dma-names = "rx", "tx";
|
2012-11-13 12:03:39 +07:00
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
2012-05-12 06:03:26 +07:00
|
|
|
i2c@7000c400 {
|
|
|
|
|
compatible = "nvidia,tegra20-i2c";
|
|
|
|
|
reg = <0x7000c400 0x100>;
|
2013-02-14 02:51:51 +07:00
|
|
|
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
|
2012-05-12 06:12:52 +07:00
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
2013-05-22 23:45:32 +07:00
|
|
|
clocks = <&tegra_car TEGRA20_CLK_I2C2>,
|
|
|
|
|
<&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
|
2013-01-11 15:01:21 +07:00
|
|
|
clock-names = "div-clk", "fast-clk";
|
2013-11-07 04:01:16 +07:00
|
|
|
resets = <&tegra_car 54>;
|
|
|
|
|
reset-names = "i2c";
|
2013-11-12 03:05:59 +07:00
|
|
|
dmas = <&apbdma 22>, <&apbdma 22>;
|
|
|
|
|
dma-names = "rx", "tx";
|
2012-06-12 02:09:45 +07:00
|
|
|
status = "disabled";
|
2011-07-20 06:26:54 +07:00
|
|
|
};
|
|
|
|
|
|
2012-05-12 06:03:26 +07:00
|
|
|
i2c@7000c500 {
|
|
|
|
|
compatible = "nvidia,tegra20-i2c";
|
|
|
|
|
reg = <0x7000c500 0x100>;
|
2013-02-14 02:51:51 +07:00
|
|
|
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
|
2012-05-12 06:12:52 +07:00
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
2013-05-22 23:45:32 +07:00
|
|
|
clocks = <&tegra_car TEGRA20_CLK_I2C3>,
|
|
|
|
|
<&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
|
2013-01-11 15:01:21 +07:00
|
|
|
clock-names = "div-clk", "fast-clk";
|
2013-11-07 04:01:16 +07:00
|
|
|
resets = <&tegra_car 67>;
|
|
|
|
|
reset-names = "i2c";
|
2013-11-12 03:05:59 +07:00
|
|
|
dmas = <&apbdma 23>, <&apbdma 23>;
|
|
|
|
|
dma-names = "rx", "tx";
|
2012-06-12 02:09:45 +07:00
|
|
|
status = "disabled";
|
2011-07-20 06:26:54 +07:00
|
|
|
};
|
|
|
|
|
|
2012-05-12 06:03:26 +07:00
|
|
|
i2c@7000d000 {
|
|
|
|
|
compatible = "nvidia,tegra20-i2c-dvc";
|
|
|
|
|
reg = <0x7000d000 0x200>;
|
2013-02-14 02:51:51 +07:00
|
|
|
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
|
2012-05-12 06:12:52 +07:00
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
2013-05-22 23:45:32 +07:00
|
|
|
clocks = <&tegra_car TEGRA20_CLK_DVC>,
|
|
|
|
|
<&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
|
2013-01-11 15:01:21 +07:00
|
|
|
clock-names = "div-clk", "fast-clk";
|
2013-11-07 04:01:16 +07:00
|
|
|
resets = <&tegra_car 47>;
|
|
|
|
|
reset-names = "i2c";
|
2013-11-12 03:05:59 +07:00
|
|
|
dmas = <&apbdma 24>, <&apbdma 24>;
|
|
|
|
|
dma-names = "rx", "tx";
|
2012-06-12 02:09:45 +07:00
|
|
|
status = "disabled";
|
2011-07-20 06:26:54 +07:00
|
|
|
};
|
|
|
|
|
|
2012-10-30 14:05:23 +07:00
|
|
|
spi@7000d400 {
|
|
|
|
|
compatible = "nvidia,tegra20-slink";
|
|
|
|
|
reg = <0x7000d400 0x200>;
|
2013-02-14 02:51:51 +07:00
|
|
|
interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
|
2012-10-30 14:05:23 +07:00
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
2013-05-22 23:45:32 +07:00
|
|
|
clocks = <&tegra_car TEGRA20_CLK_SBC1>;
|
2013-11-07 04:01:16 +07:00
|
|
|
resets = <&tegra_car 41>;
|
|
|
|
|
reset-names = "spi";
|
2013-11-12 03:05:59 +07:00
|
|
|
dmas = <&apbdma 15>, <&apbdma 15>;
|
|
|
|
|
dma-names = "rx", "tx";
|
2012-10-30 14:05:23 +07:00
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
spi@7000d600 {
|
|
|
|
|
compatible = "nvidia,tegra20-slink";
|
|
|
|
|
reg = <0x7000d600 0x200>;
|
2013-02-14 02:51:51 +07:00
|
|
|
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
|
2012-10-30 14:05:23 +07:00
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
2013-05-22 23:45:32 +07:00
|
|
|
clocks = <&tegra_car TEGRA20_CLK_SBC2>;
|
2013-11-07 04:01:16 +07:00
|
|
|
resets = <&tegra_car 44>;
|
|
|
|
|
reset-names = "spi";
|
2013-11-12 03:05:59 +07:00
|
|
|
dmas = <&apbdma 16>, <&apbdma 16>;
|
|
|
|
|
dma-names = "rx", "tx";
|
2012-10-30 14:05:23 +07:00
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
spi@7000d800 {
|
|
|
|
|
compatible = "nvidia,tegra20-slink";
|
2013-03-23 01:35:06 +07:00
|
|
|
reg = <0x7000d800 0x200>;
|
2013-02-14 02:51:51 +07:00
|
|
|
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
|
2012-10-30 14:05:23 +07:00
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
2013-05-22 23:45:32 +07:00
|
|
|
clocks = <&tegra_car TEGRA20_CLK_SBC3>;
|
2013-11-07 04:01:16 +07:00
|
|
|
resets = <&tegra_car 46>;
|
|
|
|
|
reset-names = "spi";
|
2013-11-12 03:05:59 +07:00
|
|
|
dmas = <&apbdma 17>, <&apbdma 17>;
|
|
|
|
|
dma-names = "rx", "tx";
|
2012-10-30 14:05:23 +07:00
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
spi@7000da00 {
|
|
|
|
|
compatible = "nvidia,tegra20-slink";
|
|
|
|
|
reg = <0x7000da00 0x200>;
|
2013-02-14 02:51:51 +07:00
|
|
|
interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
|
2012-10-30 14:05:23 +07:00
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
2013-05-22 23:45:32 +07:00
|
|
|
clocks = <&tegra_car TEGRA20_CLK_SBC4>;
|
2013-11-07 04:01:16 +07:00
|
|
|
resets = <&tegra_car 68>;
|
|
|
|
|
reset-names = "spi";
|
2013-11-12 03:05:59 +07:00
|
|
|
dmas = <&apbdma 18>, <&apbdma 18>;
|
|
|
|
|
dma-names = "rx", "tx";
|
2012-10-30 14:05:23 +07:00
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
2013-11-26 07:53:16 +07:00
|
|
|
kbc@7000e200 {
|
2013-01-11 20:33:03 +07:00
|
|
|
compatible = "nvidia,tegra20-kbc";
|
|
|
|
|
reg = <0x7000e200 0x100>;
|
2013-02-14 02:51:51 +07:00
|
|
|
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
|
2013-05-22 23:45:32 +07:00
|
|
|
clocks = <&tegra_car TEGRA20_CLK_KBC>;
|
2013-11-07 04:01:16 +07:00
|
|
|
resets = <&tegra_car 36>;
|
|
|
|
|
reset-names = "kbc";
|
2013-01-11 20:33:03 +07:00
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
2013-11-26 07:53:16 +07:00
|
|
|
pmc@7000e400 {
|
2012-05-12 06:03:26 +07:00
|
|
|
compatible = "nvidia,tegra20-pmc";
|
|
|
|
|
reg = <0x7000e400 0x400>;
|
2013-05-22 23:45:32 +07:00
|
|
|
clocks = <&tegra_car TEGRA20_CLK_PCLK>, <&clk32k_in>;
|
2013-04-03 18:31:27 +07:00
|
|
|
clock-names = "pclk", "clk32k_in";
|
2012-05-12 06:03:26 +07:00
|
|
|
};
|
|
|
|
|
|
2012-10-03 02:10:47 +07:00
|
|
|
memory-controller@7000f000 {
|
2012-05-12 06:03:26 +07:00
|
|
|
compatible = "nvidia,tegra20-mc";
|
|
|
|
|
reg = <0x7000f000 0x024
|
|
|
|
|
0x7000f03c 0x3c4>;
|
2013-02-14 02:51:51 +07:00
|
|
|
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
|
2012-05-12 06:03:26 +07:00
|
|
|
};
|
|
|
|
|
|
2013-11-26 07:53:16 +07:00
|
|
|
iommu@7000f024 {
|
2012-05-12 06:03:26 +07:00
|
|
|
compatible = "nvidia,tegra20-gart";
|
|
|
|
|
reg = <0x7000f024 0x00000018 /* controller registers */
|
|
|
|
|
0x58000000 0x02000000>; /* GART aperture */
|
|
|
|
|
};
|
|
|
|
|
|
2012-10-03 02:10:47 +07:00
|
|
|
memory-controller@7000f400 {
|
2012-05-12 06:03:26 +07:00
|
|
|
compatible = "nvidia,tegra20-emc";
|
|
|
|
|
reg = <0x7000f400 0x200>;
|
2012-05-12 06:12:52 +07:00
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
2011-07-20 06:26:54 +07:00
|
|
|
};
|
2011-11-04 16:12:39 +07:00
|
|
|
|
2014-06-12 22:36:38 +07:00
|
|
|
fuse@7000f800 {
|
|
|
|
|
compatible = "nvidia,tegra20-efuse";
|
2015-04-29 18:53:21 +07:00
|
|
|
reg = <0x7000f800 0x400>;
|
2014-06-12 22:36:38 +07:00
|
|
|
clocks = <&tegra_car TEGRA20_CLK_FUSE>;
|
|
|
|
|
clock-names = "fuse";
|
|
|
|
|
resets = <&tegra_car 39>;
|
|
|
|
|
reset-names = "fuse";
|
|
|
|
|
};
|
|
|
|
|
|
2017-03-22 09:03:06 +07:00
|
|
|
pcie@80003000 {
|
2013-08-09 21:49:19 +07:00
|
|
|
compatible = "nvidia,tegra20-pcie";
|
|
|
|
|
device_type = "pci";
|
|
|
|
|
reg = <0x80003000 0x00000800 /* PADS registers */
|
|
|
|
|
0x80003800 0x00000200 /* AFI registers */
|
|
|
|
|
0x90000000 0x10000000>; /* configuration space */
|
|
|
|
|
reg-names = "pads", "afi", "cs";
|
|
|
|
|
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH /* controller interrupt */
|
|
|
|
|
GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
|
|
|
|
|
interrupt-names = "intr", "msi";
|
|
|
|
|
|
2014-03-05 20:25:46 +07:00
|
|
|
#interrupt-cells = <1>;
|
|
|
|
|
interrupt-map-mask = <0 0 0 0>;
|
|
|
|
|
interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
|
2013-08-09 21:49:19 +07:00
|
|
|
bus-range = <0x00 0xff>;
|
|
|
|
|
#address-cells = <3>;
|
|
|
|
|
#size-cells = <2>;
|
|
|
|
|
|
|
|
|
|
ranges = <0x82000000 0 0x80000000 0x80000000 0 0x00001000 /* port 0 registers */
|
|
|
|
|
0x82000000 0 0x80001000 0x80001000 0 0x00001000 /* port 1 registers */
|
|
|
|
|
0x81000000 0 0 0x82000000 0 0x00010000 /* downstream I/O */
|
2013-08-09 21:49:31 +07:00
|
|
|
0x82000000 0 0xa0000000 0xa0000000 0 0x08000000 /* non-prefetchable memory */
|
|
|
|
|
0xc2000000 0 0xa8000000 0xa8000000 0 0x18000000>; /* prefetchable memory */
|
2013-08-09 21:49:19 +07:00
|
|
|
|
|
|
|
|
clocks = <&tegra_car TEGRA20_CLK_PEX>,
|
|
|
|
|
<&tegra_car TEGRA20_CLK_AFI>,
|
|
|
|
|
<&tegra_car TEGRA20_CLK_PLL_E>;
|
2013-11-08 00:59:42 +07:00
|
|
|
clock-names = "pex", "afi", "pll_e";
|
2013-11-07 04:01:16 +07:00
|
|
|
resets = <&tegra_car 70>,
|
2015-08-27 16:44:48 +07:00
|
|
|
<&tegra_car 72>,
|
|
|
|
|
<&tegra_car 74>;
|
2013-11-07 04:01:16 +07:00
|
|
|
reset-names = "pex", "afi", "pcie_x";
|
2013-08-09 21:49:19 +07:00
|
|
|
status = "disabled";
|
|
|
|
|
|
|
|
|
|
pci@1,0 {
|
|
|
|
|
device_type = "pci";
|
|
|
|
|
assigned-addresses = <0x82000800 0 0x80000000 0 0x1000>;
|
|
|
|
|
reg = <0x000800 0 0 0 0>;
|
2017-03-22 09:03:06 +07:00
|
|
|
bus-range = <0x00 0xff>;
|
2013-08-09 21:49:19 +07:00
|
|
|
status = "disabled";
|
|
|
|
|
|
|
|
|
|
#address-cells = <3>;
|
|
|
|
|
#size-cells = <2>;
|
|
|
|
|
ranges;
|
|
|
|
|
|
|
|
|
|
nvidia,num-lanes = <2>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pci@2,0 {
|
|
|
|
|
device_type = "pci";
|
|
|
|
|
assigned-addresses = <0x82001000 0 0x80001000 0 0x1000>;
|
|
|
|
|
reg = <0x001000 0 0 0 0>;
|
2017-03-22 09:03:06 +07:00
|
|
|
bus-range = <0x00 0xff>;
|
2013-08-09 21:49:19 +07:00
|
|
|
status = "disabled";
|
|
|
|
|
|
|
|
|
|
#address-cells = <3>;
|
|
|
|
|
#size-cells = <2>;
|
|
|
|
|
ranges;
|
|
|
|
|
|
|
|
|
|
nvidia,num-lanes = <2>;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
2011-11-04 16:12:39 +07:00
|
|
|
usb@c5000000 {
|
|
|
|
|
compatible = "nvidia,tegra20-ehci", "usb-ehci";
|
|
|
|
|
reg = <0xc5000000 0x4000>;
|
2013-02-14 02:51:51 +07:00
|
|
|
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
|
2011-11-04 16:12:39 +07:00
|
|
|
phy_type = "utmi";
|
2012-03-07 12:04:33 +07:00
|
|
|
nvidia,has-legacy-mode;
|
2013-05-22 23:45:32 +07:00
|
|
|
clocks = <&tegra_car TEGRA20_CLK_USBD>;
|
2013-11-07 04:01:16 +07:00
|
|
|
resets = <&tegra_car 22>;
|
|
|
|
|
reset-names = "usb";
|
2012-12-14 03:59:07 +07:00
|
|
|
nvidia,needs-double-reset;
|
2013-01-16 10:30:19 +07:00
|
|
|
nvidia,phy = <&phy1>;
|
2012-06-12 02:09:45 +07:00
|
|
|
status = "disabled";
|
2011-11-04 16:12:39 +07:00
|
|
|
};
|
|
|
|
|
|
2013-05-16 21:12:57 +07:00
|
|
|
phy1: usb-phy@c5000000 {
|
2013-03-07 01:28:33 +07:00
|
|
|
compatible = "nvidia,tegra20-usb-phy";
|
2013-05-16 21:12:57 +07:00
|
|
|
reg = <0xc5000000 0x4000 0xc5000000 0x4000>;
|
2013-03-07 01:28:33 +07:00
|
|
|
phy_type = "utmi";
|
2013-05-22 23:45:32 +07:00
|
|
|
clocks = <&tegra_car TEGRA20_CLK_USBD>,
|
|
|
|
|
<&tegra_car TEGRA20_CLK_PLL_U>,
|
|
|
|
|
<&tegra_car TEGRA20_CLK_CLK_M>,
|
|
|
|
|
<&tegra_car TEGRA20_CLK_USBD>;
|
2013-05-16 21:12:57 +07:00
|
|
|
clock-names = "reg", "pll_u", "timer", "utmi-pads";
|
2014-07-04 08:09:37 +07:00
|
|
|
resets = <&tegra_car 22>, <&tegra_car 22>;
|
|
|
|
|
reset-names = "usb", "utmi-pads";
|
2013-03-07 01:28:33 +07:00
|
|
|
nvidia,has-legacy-mode;
|
2013-07-17 13:31:00 +07:00
|
|
|
nvidia,hssync-start-delay = <9>;
|
|
|
|
|
nvidia,idle-wait-delay = <17>;
|
|
|
|
|
nvidia,elastic-limit = <16>;
|
|
|
|
|
nvidia,term-range-adj = <6>;
|
|
|
|
|
nvidia,xcvr-setup = <9>;
|
|
|
|
|
nvidia,xcvr-lsfslew = <1>;
|
|
|
|
|
nvidia,xcvr-lsrslew = <1>;
|
2014-07-04 08:09:37 +07:00
|
|
|
nvidia,has-utmi-pad-registers;
|
2013-05-16 21:12:57 +07:00
|
|
|
status = "disabled";
|
2013-03-07 01:28:33 +07:00
|
|
|
};
|
|
|
|
|
|
2011-11-04 16:12:39 +07:00
|
|
|
usb@c5004000 {
|
|
|
|
|
compatible = "nvidia,tegra20-ehci", "usb-ehci";
|
|
|
|
|
reg = <0xc5004000 0x4000>;
|
2013-02-14 02:51:51 +07:00
|
|
|
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
|
2011-11-04 16:12:39 +07:00
|
|
|
phy_type = "ulpi";
|
2013-05-22 23:45:32 +07:00
|
|
|
clocks = <&tegra_car TEGRA20_CLK_USB2>;
|
2013-11-07 04:01:16 +07:00
|
|
|
resets = <&tegra_car 58>;
|
|
|
|
|
reset-names = "usb";
|
2013-01-16 10:30:19 +07:00
|
|
|
nvidia,phy = <&phy2>;
|
2012-06-12 02:09:45 +07:00
|
|
|
status = "disabled";
|
2011-11-04 16:12:39 +07:00
|
|
|
};
|
|
|
|
|
|
2013-05-16 21:12:57 +07:00
|
|
|
phy2: usb-phy@c5004000 {
|
2013-03-07 01:28:33 +07:00
|
|
|
compatible = "nvidia,tegra20-usb-phy";
|
2013-05-16 21:12:57 +07:00
|
|
|
reg = <0xc5004000 0x4000>;
|
2013-03-07 01:28:33 +07:00
|
|
|
phy_type = "ulpi";
|
2013-05-22 23:45:32 +07:00
|
|
|
clocks = <&tegra_car TEGRA20_CLK_USB2>,
|
|
|
|
|
<&tegra_car TEGRA20_CLK_PLL_U>,
|
|
|
|
|
<&tegra_car TEGRA20_CLK_CDEV2>;
|
2013-05-16 21:12:57 +07:00
|
|
|
clock-names = "reg", "pll_u", "ulpi-link";
|
2014-07-04 08:09:37 +07:00
|
|
|
resets = <&tegra_car 58>, <&tegra_car 22>;
|
|
|
|
|
reset-names = "usb", "utmi-pads";
|
2013-05-16 21:12:57 +07:00
|
|
|
status = "disabled";
|
2013-03-07 01:28:33 +07:00
|
|
|
};
|
|
|
|
|
|
2011-11-04 16:12:39 +07:00
|
|
|
usb@c5008000 {
|
|
|
|
|
compatible = "nvidia,tegra20-ehci", "usb-ehci";
|
|
|
|
|
reg = <0xc5008000 0x4000>;
|
2013-02-14 02:51:51 +07:00
|
|
|
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
|
2011-11-04 16:12:39 +07:00
|
|
|
phy_type = "utmi";
|
2013-05-22 23:45:32 +07:00
|
|
|
clocks = <&tegra_car TEGRA20_CLK_USB3>;
|
2013-11-07 04:01:16 +07:00
|
|
|
resets = <&tegra_car 59>;
|
|
|
|
|
reset-names = "usb";
|
2013-01-16 10:30:19 +07:00
|
|
|
nvidia,phy = <&phy3>;
|
2012-06-12 02:09:45 +07:00
|
|
|
status = "disabled";
|
2011-11-04 16:12:39 +07:00
|
|
|
};
|
2012-05-07 13:43:47 +07:00
|
|
|
|
2013-05-16 21:12:57 +07:00
|
|
|
phy3: usb-phy@c5008000 {
|
2013-03-07 01:28:33 +07:00
|
|
|
compatible = "nvidia,tegra20-usb-phy";
|
2013-05-16 21:12:57 +07:00
|
|
|
reg = <0xc5008000 0x4000 0xc5000000 0x4000>;
|
2013-03-07 01:28:33 +07:00
|
|
|
phy_type = "utmi";
|
2013-05-22 23:45:32 +07:00
|
|
|
clocks = <&tegra_car TEGRA20_CLK_USB3>,
|
|
|
|
|
<&tegra_car TEGRA20_CLK_PLL_U>,
|
|
|
|
|
<&tegra_car TEGRA20_CLK_CLK_M>,
|
|
|
|
|
<&tegra_car TEGRA20_CLK_USBD>;
|
2013-05-16 21:12:57 +07:00
|
|
|
clock-names = "reg", "pll_u", "timer", "utmi-pads";
|
2014-07-04 08:09:37 +07:00
|
|
|
resets = <&tegra_car 59>, <&tegra_car 22>;
|
|
|
|
|
reset-names = "usb", "utmi-pads";
|
2013-07-17 13:31:00 +07:00
|
|
|
nvidia,hssync-start-delay = <9>;
|
|
|
|
|
nvidia,idle-wait-delay = <17>;
|
|
|
|
|
nvidia,elastic-limit = <16>;
|
|
|
|
|
nvidia,term-range-adj = <6>;
|
|
|
|
|
nvidia,xcvr-setup = <9>;
|
|
|
|
|
nvidia,xcvr-lsfslew = <2>;
|
|
|
|
|
nvidia,xcvr-lsrslew = <2>;
|
2013-05-16 21:12:57 +07:00
|
|
|
status = "disabled";
|
2013-03-07 01:28:33 +07:00
|
|
|
};
|
|
|
|
|
|
2012-05-12 06:03:26 +07:00
|
|
|
sdhci@c8000000 {
|
|
|
|
|
compatible = "nvidia,tegra20-sdhci";
|
|
|
|
|
reg = <0xc8000000 0x200>;
|
2013-02-14 02:51:51 +07:00
|
|
|
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
|
2013-05-22 23:45:32 +07:00
|
|
|
clocks = <&tegra_car TEGRA20_CLK_SDMMC1>;
|
2013-11-07 04:01:16 +07:00
|
|
|
resets = <&tegra_car 14>;
|
|
|
|
|
reset-names = "sdhci";
|
2012-06-12 02:09:45 +07:00
|
|
|
status = "disabled";
|
2012-05-07 13:43:47 +07:00
|
|
|
};
|
2012-05-10 04:42:31 +07:00
|
|
|
|
2012-05-12 06:03:26 +07:00
|
|
|
sdhci@c8000200 {
|
|
|
|
|
compatible = "nvidia,tegra20-sdhci";
|
|
|
|
|
reg = <0xc8000200 0x200>;
|
2013-02-14 02:51:51 +07:00
|
|
|
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
|
2013-05-22 23:45:32 +07:00
|
|
|
clocks = <&tegra_car TEGRA20_CLK_SDMMC2>;
|
2013-11-07 04:01:16 +07:00
|
|
|
resets = <&tegra_car 9>;
|
|
|
|
|
reset-names = "sdhci";
|
2012-06-12 02:09:45 +07:00
|
|
|
status = "disabled";
|
2012-05-10 04:42:31 +07:00
|
|
|
};
|
2012-05-10 04:45:33 +07:00
|
|
|
|
2012-05-12 06:03:26 +07:00
|
|
|
sdhci@c8000400 {
|
|
|
|
|
compatible = "nvidia,tegra20-sdhci";
|
|
|
|
|
reg = <0xc8000400 0x200>;
|
2013-02-14 02:51:51 +07:00
|
|
|
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
|
2013-05-22 23:45:32 +07:00
|
|
|
clocks = <&tegra_car TEGRA20_CLK_SDMMC3>;
|
2013-11-07 04:01:16 +07:00
|
|
|
resets = <&tegra_car 69>;
|
|
|
|
|
reset-names = "sdhci";
|
2012-06-12 02:09:45 +07:00
|
|
|
status = "disabled";
|
2012-05-12 06:03:26 +07:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
sdhci@c8000600 {
|
|
|
|
|
compatible = "nvidia,tegra20-sdhci";
|
|
|
|
|
reg = <0xc8000600 0x200>;
|
2013-02-14 02:51:51 +07:00
|
|
|
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
|
2013-05-22 23:45:32 +07:00
|
|
|
clocks = <&tegra_car TEGRA20_CLK_SDMMC4>;
|
2013-11-07 04:01:16 +07:00
|
|
|
resets = <&tegra_car 15>;
|
|
|
|
|
reset-names = "sdhci";
|
2012-06-12 02:09:45 +07:00
|
|
|
status = "disabled";
|
2012-05-12 06:03:26 +07:00
|
|
|
};
|
|
|
|
|
|
2013-01-11 20:26:55 +07:00
|
|
|
cpus {
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
|
|
|
|
|
cpu@0 {
|
|
|
|
|
device_type = "cpu";
|
|
|
|
|
compatible = "arm,cortex-a9";
|
|
|
|
|
reg = <0>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
cpu@1 {
|
|
|
|
|
device_type = "cpu";
|
|
|
|
|
compatible = "arm,cortex-a9";
|
|
|
|
|
reg = <1>;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
2012-05-12 06:03:26 +07:00
|
|
|
pmu {
|
|
|
|
|
compatible = "arm,cortex-a9-pmu";
|
2013-02-14 02:51:51 +07:00
|
|
|
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
|
2012-05-10 04:45:33 +07:00
|
|
|
};
|
2011-07-20 06:26:54 +07:00
|
|
|
};
|