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ARM: dts: tegra: fix PCI bus dtc warnings

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dtc recently added PCI bus checks. Fix these warnings.

Signed-off-by: Rob Herring <robh@kernel.org>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Thierry Reding <thierry.reding@gmail.com>
Cc: Alexandre Courbot <gnurou@gmail.com>
Cc: linux-tegra@vger.kernel.org
Signed-off-by: Thierry Reding <treding@nvidia.com>
This commit is contained in:
Rob Herring 2017-03-21 21:03:06 -05:00 committed by Thierry Reding
parent b5db9dedc5
commit 508d690e94
14 changed files with 21 additions and 14 deletions
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2
arch/arm/boot/dts/tegra124-apalis-eval.dts
View File

@ -63,7 +63,7 @@ chosen {
stdout-path = "serial0:115200n8";
};
pcie-controller@01003000 {
pcie@1003000 {
pci@1,0 {
status = "okay";
};

2
arch/arm/boot/dts/tegra124-apalis.dtsi
View File

@ -54,7 +54,7 @@ memory {
reg = <0x0 0x80000000 0x0 0x80000000>;
};
pcie-controller@01003000 {
pcie@1003000 {
status = "okay";
avddio-pex-supply = <&vdd_1v05>;

2
arch/arm/boot/dts/tegra124-jetson-tk1.dts
View File

@ -27,7 +27,7 @@ memory {
reg = <0x0 0x80000000 0x0 0x80000000>;
};
pcie-controller@01003000 {
pcie@1003000 {
status = "okay";
avddio-pex-supply = <&vdd_1v05_run>;

4
arch/arm/boot/dts/tegra124.dtsi
View File

@ -14,7 +14,7 @@ / {
#address-cells = <2>;
#size-cells = <2>;
pcie-controller@01003000 {
pcie@1003000 {
compatible = "nvidia,tegra124-pcie";
device_type = "pci";
reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */
@ -54,6 +54,7 @@ pci@1,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
reg = <0x000800 0 0 0 0>;
bus-range = <0x00 0xff>;
status = "disabled";
#address-cells = <3>;
@ -67,6 +68,7 @@ pci@2,0 {
device_type = "pci";
assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
reg = <0x001000 0 0 0 0>;
bus-range = <0x00 0xff>;
status = "disabled";
#address-cells = <3>;

2
arch/arm/boot/dts/tegra20-harmony.dts
View File

@ -566,7 +566,7 @@ pmc@7000e400 {
nvidia,sys-clock-req-active-high;
};
pcie-controller@80003000 {
pcie@80003000 {
status = "okay";
avdd-pex-supply = <&pci_vdd_reg>;

2
arch/arm/boot/dts/tegra20-tamonten.dtsi
View File

@ -478,7 +478,7 @@ pmc@7000e400 {
nvidia,sys-clock-req-active-high;
};
pcie-controller@80003000 {
pcie@80003000 {
avdd-pex-supply = <&pci_vdd_reg>;
vdd-pex-supply = <&pci_vdd_reg>;
avdd-pex-pll-supply = <&pci_vdd_reg>;

2
arch/arm/boot/dts/tegra20-tec.dts
View File

@ -32,7 +32,7 @@ wm8903: wm8903@1a {
};
};
pcie-controller@80003000 {
pcie@80003000 {
status = "okay";
pci@1,0 {

2
arch/arm/boot/dts/tegra20-trimslice.dts
View File

@ -321,7 +321,7 @@ pmc@7000e400 {
nvidia,sys-clock-req-active-high;
};
pcie-controller@80003000 {
pcie@80003000 {
status = "okay";
avdd-pex-supply = <&pci_vdd_reg>;

4
arch/arm/boot/dts/tegra20.dtsi
View File

@ -586,7 +586,7 @@ fuse@7000f800 {
reset-names = "fuse";
};
pcie-controller@80003000 {
pcie@80003000 {
compatible = "nvidia,tegra20-pcie";
device_type = "pci";
reg = <0x80003000 0x00000800 /* PADS registers */
@ -625,6 +625,7 @@ pci@1,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x80000000 0 0x1000>;
reg = <0x000800 0 0 0 0>;
bus-range = <0x00 0xff>;
status = "disabled";
#address-cells = <3>;
@ -638,6 +639,7 @@ pci@2,0 {
device_type = "pci";
assigned-addresses = <0x82001000 0 0x80001000 0 0x1000>;
reg = <0x001000 0 0 0 0>;
bus-range = <0x00 0xff>;
status = "disabled";
#address-cells = <3>;

2
arch/arm/boot/dts/tegra30-apalis-eval.dts
View File

@ -21,7 +21,7 @@ chosen {
stdout-path = "serial0:115200n8";
};
pcie-controller@00003000 {
pcie@3000 {
status = "okay";
pci@1,0 {

2
arch/arm/boot/dts/tegra30-apalis.dtsi
View File

@ -9,7 +9,7 @@ / {
model = "Toradex Apalis T30";
compatible = "toradex,apalis_t30", "nvidia,tegra30";
pcie-controller@00003000 {
pcie@3000 {
avdd-pexa-supply = <&vdd2_reg>;
vdd-pexa-supply = <&vdd2_reg>;
avdd-pexb-supply = <&vdd2_reg>;

2
arch/arm/boot/dts/tegra30-beaver.dts
View File

@ -20,7 +20,7 @@ memory {
reg = <0x80000000 0x7ff00000>;
};
pcie-controller@00003000 {
pcie@3000 {
status = "okay";
avdd-pexa-supply = <&ldo1_reg>;

2
arch/arm/boot/dts/tegra30-cardhu.dtsi
View File

@ -43,7 +43,7 @@ memory {
reg = <0x80000000 0x40000000>;
};
pcie-controller@00003000 {
pcie@3000 {
status = "okay";
/* AVDD_PEXA and VDD_PEXA inputs are grounded on Cardhu. */

5
arch/arm/boot/dts/tegra30.dtsi
View File

@ -10,7 +10,7 @@ / {
compatible = "nvidia,tegra30";
interrupt-parent = <&lic>;
pcie-controller@00003000 {
pcie@3000 {
compatible = "nvidia,tegra30-pcie";
device_type = "pci";
reg = <0x00003000 0x00000800 /* PADS registers */
@ -51,6 +51,7 @@ pci@1,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x00000000 0 0x1000>;
reg = <0x000800 0 0 0 0>;
bus-range = <0x00 0xff>;
status = "disabled";
#address-cells = <3>;
@ -64,6 +65,7 @@ pci@2,0 {
device_type = "pci";
assigned-addresses = <0x82001000 0 0x00001000 0 0x1000>;
reg = <0x001000 0 0 0 0>;
bus-range = <0x00 0xff>;
status = "disabled";
#address-cells = <3>;
@ -77,6 +79,7 @@ pci@3,0 {
device_type = "pci";
assigned-addresses = <0x82001800 0 0x00004000 0 0x1000>;
reg = <0x001800 0 0 0 0>;
bus-range = <0x00 0xff>;
status = "disabled";
#address-cells = <3>;