Christoph Hellwig fcdc653751 riscv: provide native clint access for M-mode ... RISC-V has the concept of a cpu level interrupt controller. The interface for it is split between a standardized part that is exposed as bits in the mstatus/sstatus register and the mie/mip/sie/sip CRS. But the bit to actually trigger IPIs is not standardized and just mentioned as implementable using MMIO. Add support for IPIs using MMIO using the SiFive clint layout (which is also shared by Ariane, Kendryte and the Qemu virt platform). Additionally the MMIO block also supports the time value and timer compare registers, so they are also set up using the same OF node. Support for other layouts should also be relatively easy to add in the future. Signed-off-by: Christoph Hellwig <hch@lst.de> Reviewed-by: Anup Patel <anup@brainfault.org> [paul.walmsley@sifive.com: update include guard format; fix checkpatch issues; minor commit message cleanup] Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>		2019-11-17 15:17:39 -08:00
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asm	riscv: provide native clint access for M-mode	2019-11-17 15:17:39 -08:00
uapi/asm	riscv: Add support for perf registers sampling	2019-09-05 00:48:58 -07:00