Leo (Hanghong) Ma fa11d3c942 drm/amd/display: Change the delay time before enabling FEC ... [why] DP spec requires 1000 symbols delay between the end of link training and enabling FEC in the stream. Currently we are using 1 miliseconds delay which is not accurate. [how] One lane RBR should have the maximum time for transmitting 1000 LL codes which is 6.173 us. So using 7 microseconds delay instead of 1 miliseconds. Signed-off-by: Leo (Hanghong) Ma <hanghong.ma@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Reviewed-by: Nikola Cornij <Nikola.Cornij@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2019-12-05 16:29:11 -05:00
..
amdgpu_dm	drm/amd/display: Null check aconnector in event_property_validate	2019-11-26 14:50:38 -05:00
dc	drm/amd/display: Change the delay time before enabling FEC	2019-12-05 16:29:11 -05:00
dmub	drm/amd/display: Program CW5 for tracebuffer for dcn20	2019-12-05 16:28:23 -05:00
include	drm/amd/display: Fix Dali clk mgr construct	2019-12-05 16:26:54 -05:00
modules	drm/amd/display: remove redundant assignment to variable v_total	2019-12-02 17:55:08 -05:00
Kconfig	drm/amd/display: rename DCN1_0 kconfig to DCN	2019-11-13 15:29:44 -05:00
Makefile	drm/amd/display: Drop CONFIG_DRM_AMD_DC_DMUB guards	2019-11-13 15:29:42 -05:00
TODO