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41193869f2
Convert sun4i-a10.dtsi to new CCU driver. Tested on Gemei G9 tablet. Signed-off-by: Priit Laes <plaes@plaes.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
840 lines
20 KiB
Plaintext
840 lines
20 KiB
Plaintext
/*
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* Copyright 2012 Stefan Roese
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* Stefan Roese <sr@denx.de>
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively,
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include "skeleton.dtsi"
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#include <dt-bindings/thermal/thermal.h>
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#include <dt-bindings/dma/sun4i-a10.h>
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#include <dt-bindings/clock/sun4i-a10-ccu.h>
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#include <dt-bindings/reset/sun4i-a10-ccu.h>
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/ {
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interrupt-parent = <&intc>;
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aliases {
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ethernet0 = &emac;
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};
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chosen {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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framebuffer@0 {
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compatible = "allwinner,simple-framebuffer",
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"simple-framebuffer";
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allwinner,pipeline = "de_be0-lcd0-hdmi";
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clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_HDMI0>,
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<&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>,
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<&ccu CLK_TCON0_CH1>, <&ccu CLK_DRAM_DE_BE0>;
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status = "disabled";
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};
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framebuffer@1 {
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compatible = "allwinner,simple-framebuffer",
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"simple-framebuffer";
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allwinner,pipeline = "de_fe0-de_be0-lcd0-hdmi";
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clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_HDMI0>,
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<&ccu CLK_AHB_DE_BE0>, <&ccu CLK_AHB_DE_FE0>,
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<&ccu CLK_DE_BE0>, <&ccu CLK_AHB_DE_FE0>,
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<&ccu CLK_TCON0_CH1>, <&ccu CLK_HDMI>,
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<&ccu CLK_DRAM_DE_FE0>, <&ccu CLK_DRAM_DE_BE0>;
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status = "disabled";
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};
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framebuffer@2 {
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compatible = "allwinner,simple-framebuffer",
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"simple-framebuffer";
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allwinner,pipeline = "de_fe0-de_be0-lcd0";
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clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_DE_BE0>,
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<&ccu CLK_AHB_DE_FE0>, <&ccu CLK_DE_BE0>,
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<&ccu CLK_AHB_DE_FE0>, <&ccu CLK_TCON0_CH0>,
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<&ccu CLK_DRAM_DE_FE0>, <&ccu CLK_DRAM_DE_BE0>;
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status = "disabled";
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};
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framebuffer@3 {
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compatible = "allwinner,simple-framebuffer",
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"simple-framebuffer";
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allwinner,pipeline = "de_fe0-de_be0-lcd0-tve0";
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clocks = <&ccu CLK_AHB_TVE0>, <&ccu CLK_AHB_LCD0>,
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<&ccu CLK_AHB_DE_BE0>, <&ccu CLK_AHB_DE_FE0>,
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<&ccu CLK_DE_BE0>, <&ccu CLK_AHB_DE_FE0>,
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<&ccu CLK_TCON0_CH1>, <&ccu CLK_DRAM_TVE0>,
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<&ccu CLK_DRAM_DE_FE0>, <&ccu CLK_DRAM_DE_BE0>;
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status = "disabled";
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};
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a8";
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reg = <0x0>;
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clocks = <&ccu CLK_CPU>;
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clock-latency = <244144>; /* 8 32k periods */
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operating-points = <
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/* kHz uV */
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1008000 1400000
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912000 1350000
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864000 1300000
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624000 1250000
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>;
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#cooling-cells = <2>;
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cooling-min-level = <0>;
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cooling-max-level = <3>;
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};
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};
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thermal-zones {
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cpu_thermal {
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/* milliseconds */
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polling-delay-passive = <250>;
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polling-delay = <1000>;
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thermal-sensors = <&rtp>;
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cooling-maps {
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map0 {
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trip = <&cpu_alert0>;
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cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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};
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};
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trips {
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cpu_alert0: cpu_alert0 {
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/* milliCelsius */
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temperature = <850000>;
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hysteresis = <2000>;
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type = "passive";
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};
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cpu_crit: cpu_crit {
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/* milliCelsius */
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temperature = <100000>;
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hysteresis = <2000>;
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type = "critical";
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};
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};
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};
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};
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memory {
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reg = <0x40000000 0x80000000>;
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};
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clocks {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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osc24M: clk@01c20050 {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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clock-output-names = "osc24M";
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};
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osc32k: clk@0 {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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clock-output-names = "osc32k";
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};
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};
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soc@01c00000 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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sram-controller@01c00000 {
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compatible = "allwinner,sun4i-a10-sram-controller";
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reg = <0x01c00000 0x30>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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sram_a: sram@00000000 {
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compatible = "mmio-sram";
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reg = <0x00000000 0xc000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x00000000 0xc000>;
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emac_sram: sram-section@8000 {
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compatible = "allwinner,sun4i-a10-sram-a3-a4";
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reg = <0x8000 0x4000>;
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status = "disabled";
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};
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};
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sram_d: sram@00010000 {
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compatible = "mmio-sram";
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reg = <0x00010000 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x00010000 0x1000>;
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otg_sram: sram-section@0000 {
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compatible = "allwinner,sun4i-a10-sram-d";
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reg = <0x0000 0x1000>;
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status = "disabled";
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};
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};
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};
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dma: dma-controller@01c02000 {
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compatible = "allwinner,sun4i-a10-dma";
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reg = <0x01c02000 0x1000>;
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interrupts = <27>;
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clocks = <&ccu CLK_AHB_DMA>;
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#dma-cells = <2>;
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};
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nfc: nand@01c03000 {
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compatible = "allwinner,sun4i-a10-nand";
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reg = <0x01c03000 0x1000>;
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interrupts = <37>;
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clocks = <&ccu CLK_AHB_NAND>, <&ccu CLK_NAND>;
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clock-names = "ahb", "mod";
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dmas = <&dma SUN4I_DMA_DEDICATED 3>;
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dma-names = "rxtx";
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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spi0: spi@01c05000 {
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compatible = "allwinner,sun4i-a10-spi";
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reg = <0x01c05000 0x1000>;
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interrupts = <10>;
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clocks = <&ccu CLK_AHB_SPI0>, <&ccu CLK_SPI0>;
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clock-names = "ahb", "mod";
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dmas = <&dma SUN4I_DMA_DEDICATED 27>,
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<&dma SUN4I_DMA_DEDICATED 26>;
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dma-names = "rx", "tx";
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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spi1: spi@01c06000 {
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compatible = "allwinner,sun4i-a10-spi";
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reg = <0x01c06000 0x1000>;
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interrupts = <11>;
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clocks = <&ccu CLK_AHB_SPI1>, <&ccu CLK_SPI1>;
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clock-names = "ahb", "mod";
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dmas = <&dma SUN4I_DMA_DEDICATED 9>,
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<&dma SUN4I_DMA_DEDICATED 8>;
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dma-names = "rx", "tx";
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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emac: ethernet@01c0b000 {
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compatible = "allwinner,sun4i-a10-emac";
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reg = <0x01c0b000 0x1000>;
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interrupts = <55>;
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clocks = <&ccu CLK_AHB_EMAC>;
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allwinner,sram = <&emac_sram 1>;
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status = "disabled";
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};
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mdio: mdio@01c0b080 {
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compatible = "allwinner,sun4i-a10-mdio";
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reg = <0x01c0b080 0x14>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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mmc0: mmc@01c0f000 {
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compatible = "allwinner,sun4i-a10-mmc";
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reg = <0x01c0f000 0x1000>;
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clocks = <&ccu CLK_AHB_MMC0>, <&ccu CLK_MMC0>;
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clock-names = "ahb", "mmc";
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interrupts = <32>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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mmc1: mmc@01c10000 {
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compatible = "allwinner,sun4i-a10-mmc";
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reg = <0x01c10000 0x1000>;
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clocks = <&ccu CLK_AHB_MMC1>, <&ccu CLK_MMC1>;
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clock-names = "ahb", "mmc";
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interrupts = <33>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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mmc2: mmc@01c11000 {
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compatible = "allwinner,sun4i-a10-mmc";
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reg = <0x01c11000 0x1000>;
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clocks = <&ccu CLK_AHB_MMC2>, <&ccu CLK_MMC2>;
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clock-names = "ahb", "mmc";
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interrupts = <34>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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mmc3: mmc@01c12000 {
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compatible = "allwinner,sun4i-a10-mmc";
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reg = <0x01c12000 0x1000>;
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clocks = <&ccu CLK_AHB_MMC3>, <&ccu CLK_MMC3>;
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clock-names = "ahb", "mmc";
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interrupts = <35>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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usb_otg: usb@01c13000 {
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compatible = "allwinner,sun4i-a10-musb";
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reg = <0x01c13000 0x0400>;
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clocks = <&ccu CLK_AHB_OTG>;
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interrupts = <38>;
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interrupt-names = "mc";
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phys = <&usbphy 0>;
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phy-names = "usb";
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extcon = <&usbphy 0>;
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allwinner,sram = <&otg_sram 1>;
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status = "disabled";
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};
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usbphy: phy@01c13400 {
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#phy-cells = <1>;
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compatible = "allwinner,sun4i-a10-usb-phy";
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reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
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reg-names = "phy_ctrl", "pmu1", "pmu2";
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clocks = <&ccu CLK_USB_PHY>;
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clock-names = "usb_phy";
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resets = <&ccu RST_USB_PHY0>,
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<&ccu RST_USB_PHY1>,
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<&ccu RST_USB_PHY2>;
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reset-names = "usb0_reset", "usb1_reset", "usb2_reset";
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status = "disabled";
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};
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ehci0: usb@01c14000 {
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compatible = "allwinner,sun4i-a10-ehci", "generic-ehci";
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reg = <0x01c14000 0x100>;
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interrupts = <39>;
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clocks = <&ccu CLK_AHB_EHCI0>;
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phys = <&usbphy 1>;
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phy-names = "usb";
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status = "disabled";
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};
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ohci0: usb@01c14400 {
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compatible = "allwinner,sun4i-a10-ohci", "generic-ohci";
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reg = <0x01c14400 0x100>;
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interrupts = <64>;
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clocks = <&ccu CLK_USB_OHCI0>, <&ccu CLK_AHB_OHCI0>;
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phys = <&usbphy 1>;
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phy-names = "usb";
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status = "disabled";
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};
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crypto: crypto-engine@01c15000 {
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compatible = "allwinner,sun4i-a10-crypto";
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reg = <0x01c15000 0x1000>;
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interrupts = <86>;
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clocks = <&ccu CLK_AHB_SS>, <&ccu CLK_SS>;
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clock-names = "ahb", "mod";
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};
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spi2: spi@01c17000 {
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compatible = "allwinner,sun4i-a10-spi";
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reg = <0x01c17000 0x1000>;
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interrupts = <12>;
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clocks = <&ccu CLK_AHB_SPI2>, <&ccu CLK_SPI2>;
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clock-names = "ahb", "mod";
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dmas = <&dma SUN4I_DMA_DEDICATED 29>,
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<&dma SUN4I_DMA_DEDICATED 28>;
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dma-names = "rx", "tx";
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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ahci: sata@01c18000 {
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compatible = "allwinner,sun4i-a10-ahci";
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reg = <0x01c18000 0x1000>;
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interrupts = <56>;
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clocks = <&ccu CLK_AHB_SATA>, <&ccu CLK_SATA>;
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status = "disabled";
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};
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ehci1: usb@01c1c000 {
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compatible = "allwinner,sun4i-a10-ehci", "generic-ehci";
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reg = <0x01c1c000 0x100>;
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interrupts = <40>;
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clocks = <&ccu CLK_AHB_EHCI1>;
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phys = <&usbphy 2>;
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phy-names = "usb";
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status = "disabled";
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};
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ohci1: usb@01c1c400 {
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compatible = "allwinner,sun4i-a10-ohci", "generic-ohci";
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reg = <0x01c1c400 0x100>;
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interrupts = <65>;
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clocks = <&ccu CLK_USB_OHCI1>, <&ccu CLK_AHB_OHCI1>;
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phys = <&usbphy 2>;
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phy-names = "usb";
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status = "disabled";
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};
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spi3: spi@01c1f000 {
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compatible = "allwinner,sun4i-a10-spi";
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reg = <0x01c1f000 0x1000>;
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interrupts = <50>;
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clocks = <&ccu CLK_AHB_SPI3>, <&ccu CLK_SPI3>;
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clock-names = "ahb", "mod";
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dmas = <&dma SUN4I_DMA_DEDICATED 31>,
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<&dma SUN4I_DMA_DEDICATED 30>;
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dma-names = "rx", "tx";
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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ccu: clock@01c20000 {
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compatible = "allwinner,sun4i-a10-ccu";
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reg = <0x01c20000 0x400>;
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clocks = <&osc24M>, <&osc32k>;
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clock-names = "hosc", "losc";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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intc: interrupt-controller@01c20400 {
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compatible = "allwinner,sun4i-a10-ic";
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reg = <0x01c20400 0x400>;
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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pio: pinctrl@01c20800 {
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compatible = "allwinner,sun4i-a10-pinctrl";
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|
reg = <0x01c20800 0x400>;
|
|
interrupts = <28>;
|
|
clocks = <&ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
|
|
clock-names = "apb", "hosc", "losc";
|
|
gpio-controller;
|
|
interrupt-controller;
|
|
#interrupt-cells = <3>;
|
|
#gpio-cells = <3>;
|
|
|
|
can0_pins_a: can0@0 {
|
|
pins = "PH20", "PH21";
|
|
function = "can";
|
|
};
|
|
|
|
emac_pins_a: emac0@0 {
|
|
pins = "PA0", "PA1", "PA2",
|
|
"PA3", "PA4", "PA5", "PA6",
|
|
"PA7", "PA8", "PA9", "PA10",
|
|
"PA11", "PA12", "PA13", "PA14",
|
|
"PA15", "PA16";
|
|
function = "emac";
|
|
};
|
|
|
|
i2c0_pins_a: i2c0@0 {
|
|
pins = "PB0", "PB1";
|
|
function = "i2c0";
|
|
};
|
|
|
|
i2c1_pins_a: i2c1@0 {
|
|
pins = "PB18", "PB19";
|
|
function = "i2c1";
|
|
};
|
|
|
|
i2c2_pins_a: i2c2@0 {
|
|
pins = "PB20", "PB21";
|
|
function = "i2c2";
|
|
};
|
|
|
|
ir0_rx_pins_a: ir0@0 {
|
|
pins = "PB4";
|
|
function = "ir0";
|
|
};
|
|
|
|
ir0_tx_pins_a: ir0@1 {
|
|
pins = "PB3";
|
|
function = "ir0";
|
|
};
|
|
|
|
ir1_rx_pins_a: ir1@0 {
|
|
pins = "PB23";
|
|
function = "ir1";
|
|
};
|
|
|
|
ir1_tx_pins_a: ir1@1 {
|
|
pins = "PB22";
|
|
function = "ir1";
|
|
};
|
|
|
|
mmc0_pins_a: mmc0@0 {
|
|
pins = "PF0", "PF1", "PF2",
|
|
"PF3", "PF4", "PF5";
|
|
function = "mmc0";
|
|
drive-strength = <30>;
|
|
bias-pull-up;
|
|
};
|
|
|
|
ps20_pins_a: ps20@0 {
|
|
pins = "PI20", "PI21";
|
|
function = "ps2";
|
|
};
|
|
|
|
ps21_pins_a: ps21@0 {
|
|
pins = "PH12", "PH13";
|
|
function = "ps2";
|
|
};
|
|
|
|
pwm0_pins_a: pwm0@0 {
|
|
pins = "PB2";
|
|
function = "pwm";
|
|
};
|
|
|
|
pwm1_pins_a: pwm1@0 {
|
|
pins = "PI3";
|
|
function = "pwm";
|
|
};
|
|
|
|
spdif_tx_pins_a: spdif@0 {
|
|
pins = "PB13";
|
|
function = "spdif";
|
|
bias-pull-up;
|
|
};
|
|
|
|
spi0_pins_a: spi0@0 {
|
|
pins = "PI11", "PI12", "PI13";
|
|
function = "spi0";
|
|
};
|
|
|
|
spi0_cs0_pins_a: spi0_cs0@0 {
|
|
pins = "PI10";
|
|
function = "spi0";
|
|
};
|
|
|
|
spi1_pins_a: spi1@0 {
|
|
pins = "PI17", "PI18", "PI19";
|
|
function = "spi1";
|
|
};
|
|
|
|
spi1_cs0_pins_a: spi1_cs0@0 {
|
|
pins = "PI16";
|
|
function = "spi1";
|
|
};
|
|
|
|
spi2_pins_a: spi2@0 {
|
|
pins = "PC20", "PC21", "PC22";
|
|
function = "spi2";
|
|
};
|
|
|
|
spi2_pins_b: spi2@1 {
|
|
pins = "PB15", "PB16", "PB17";
|
|
function = "spi2";
|
|
};
|
|
|
|
spi2_cs0_pins_a: spi2_cs0@0 {
|
|
pins = "PC19";
|
|
function = "spi2";
|
|
};
|
|
|
|
spi2_cs0_pins_b: spi2_cs0@1 {
|
|
pins = "PB14";
|
|
function = "spi2";
|
|
};
|
|
|
|
uart0_pins_a: uart0@0 {
|
|
pins = "PB22", "PB23";
|
|
function = "uart0";
|
|
};
|
|
|
|
uart0_pins_b: uart0@1 {
|
|
pins = "PF2", "PF4";
|
|
function = "uart0";
|
|
};
|
|
|
|
uart1_pins_a: uart1@0 {
|
|
pins = "PA10", "PA11";
|
|
function = "uart1";
|
|
};
|
|
};
|
|
|
|
timer@01c20c00 {
|
|
compatible = "allwinner,sun4i-a10-timer";
|
|
reg = <0x01c20c00 0x90>;
|
|
interrupts = <22>;
|
|
clocks = <&osc24M>;
|
|
};
|
|
|
|
wdt: watchdog@01c20c90 {
|
|
compatible = "allwinner,sun4i-a10-wdt";
|
|
reg = <0x01c20c90 0x10>;
|
|
};
|
|
|
|
rtc: rtc@01c20d00 {
|
|
compatible = "allwinner,sun4i-a10-rtc";
|
|
reg = <0x01c20d00 0x20>;
|
|
interrupts = <24>;
|
|
};
|
|
|
|
pwm: pwm@01c20e00 {
|
|
compatible = "allwinner,sun4i-a10-pwm";
|
|
reg = <0x01c20e00 0xc>;
|
|
clocks = <&osc24M>;
|
|
#pwm-cells = <3>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spdif: spdif@01c21000 {
|
|
#sound-dai-cells = <0>;
|
|
compatible = "allwinner,sun4i-a10-spdif";
|
|
reg = <0x01c21000 0x400>;
|
|
interrupts = <13>;
|
|
clocks = <&ccu CLK_APB0_SPDIF>, <&ccu CLK_SPDIF>;
|
|
clock-names = "apb", "spdif";
|
|
dmas = <&dma SUN4I_DMA_NORMAL 2>,
|
|
<&dma SUN4I_DMA_NORMAL 2>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
ir0: ir@01c21800 {
|
|
compatible = "allwinner,sun4i-a10-ir";
|
|
clocks = <&ccu CLK_APB0_IR0>, <&ccu CLK_IR0>;
|
|
clock-names = "apb", "ir";
|
|
interrupts = <5>;
|
|
reg = <0x01c21800 0x40>;
|
|
status = "disabled";
|
|
};
|
|
|
|
ir1: ir@01c21c00 {
|
|
compatible = "allwinner,sun4i-a10-ir";
|
|
clocks = <&ccu CLK_APB0_IR1>, <&ccu CLK_IR1>;
|
|
clock-names = "apb", "ir";
|
|
interrupts = <6>;
|
|
reg = <0x01c21c00 0x40>;
|
|
status = "disabled";
|
|
};
|
|
|
|
lradc: lradc@01c22800 {
|
|
compatible = "allwinner,sun4i-a10-lradc-keys";
|
|
reg = <0x01c22800 0x100>;
|
|
interrupts = <31>;
|
|
status = "disabled";
|
|
};
|
|
|
|
codec: codec@01c22c00 {
|
|
#sound-dai-cells = <0>;
|
|
compatible = "allwinner,sun4i-a10-codec";
|
|
reg = <0x01c22c00 0x40>;
|
|
interrupts = <30>;
|
|
clocks = <&ccu CLK_APB0_CODEC>, <&ccu CLK_CODEC>;
|
|
clock-names = "apb", "codec";
|
|
dmas = <&dma SUN4I_DMA_NORMAL 19>,
|
|
<&dma SUN4I_DMA_NORMAL 19>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
sid: eeprom@01c23800 {
|
|
compatible = "allwinner,sun4i-a10-sid";
|
|
reg = <0x01c23800 0x10>;
|
|
};
|
|
|
|
rtp: rtp@01c25000 {
|
|
compatible = "allwinner,sun4i-a10-ts";
|
|
reg = <0x01c25000 0x100>;
|
|
interrupts = <29>;
|
|
#thermal-sensor-cells = <0>;
|
|
};
|
|
|
|
uart0: serial@01c28000 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x01c28000 0x400>;
|
|
interrupts = <1>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
clocks = <&ccu CLK_APB1_UART0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart1: serial@01c28400 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x01c28400 0x400>;
|
|
interrupts = <2>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
clocks = <&ccu CLK_APB1_UART1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart2: serial@01c28800 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x01c28800 0x400>;
|
|
interrupts = <3>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
clocks = <&ccu CLK_APB1_UART2>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart3: serial@01c28c00 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x01c28c00 0x400>;
|
|
interrupts = <4>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
clocks = <&ccu CLK_APB1_UART3>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart4: serial@01c29000 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x01c29000 0x400>;
|
|
interrupts = <17>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
clocks = <&ccu CLK_APB1_UART4>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart5: serial@01c29400 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x01c29400 0x400>;
|
|
interrupts = <18>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
clocks = <&ccu CLK_APB1_UART5>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart6: serial@01c29800 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x01c29800 0x400>;
|
|
interrupts = <19>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
clocks = <&ccu CLK_APB1_UART6>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart7: serial@01c29c00 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x01c29c00 0x400>;
|
|
interrupts = <20>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
clocks = <&ccu CLK_APB1_UART7>;
|
|
status = "disabled";
|
|
};
|
|
|
|
ps20: ps2@01c2a000 {
|
|
compatible = "allwinner,sun4i-a10-ps2";
|
|
reg = <0x01c2a000 0x400>;
|
|
interrupts = <62>;
|
|
clocks = <&ccu CLK_APB1_PS20>;
|
|
status = "disabled";
|
|
};
|
|
|
|
ps21: ps2@01c2a400 {
|
|
compatible = "allwinner,sun4i-a10-ps2";
|
|
reg = <0x01c2a400 0x400>;
|
|
interrupts = <63>;
|
|
clocks = <&ccu CLK_APB1_PS21>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c0: i2c@01c2ac00 {
|
|
compatible = "allwinner,sun4i-a10-i2c";
|
|
reg = <0x01c2ac00 0x400>;
|
|
interrupts = <7>;
|
|
clocks = <&ccu CLK_APB1_I2C0>;
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
i2c1: i2c@01c2b000 {
|
|
compatible = "allwinner,sun4i-a10-i2c";
|
|
reg = <0x01c2b000 0x400>;
|
|
interrupts = <8>;
|
|
clocks = <&ccu CLK_APB1_I2C1>;
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
i2c2: i2c@01c2b400 {
|
|
compatible = "allwinner,sun4i-a10-i2c";
|
|
reg = <0x01c2b400 0x400>;
|
|
interrupts = <9>;
|
|
clocks = <&ccu CLK_APB1_I2C2>;
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
can0: can@01c2bc00 {
|
|
compatible = "allwinner,sun4i-a10-can";
|
|
reg = <0x01c2bc00 0x400>;
|
|
interrupts = <26>;
|
|
clocks = <&ccu CLK_APB1_CAN>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
};
|