2012-11-26 21:46:12 +07:00
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/*
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* Copyright 2012 Stefan Roese
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* Stefan Roese <sr@denx.de>
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*
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2014-09-03 00:25:26 +07:00
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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2012-11-26 21:46:12 +07:00
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*
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2014-09-03 00:25:26 +07:00
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* a) This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively,
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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2012-11-26 21:46:12 +07:00
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*/
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2014-12-17 04:59:54 +07:00
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#include "skeleton.dtsi"
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2012-11-26 21:46:12 +07:00
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2015-01-12 11:34:08 +07:00
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#include <dt-bindings/thermal/thermal.h>
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2014-12-17 04:59:56 +07:00
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#include <dt-bindings/dma/sun4i-a10.h>
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2017-08-24 00:23:33 +07:00
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#include <dt-bindings/clock/sun4i-a10-ccu.h>
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#include <dt-bindings/reset/sun4i-a10-ccu.h>
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2012-11-26 21:46:12 +07:00
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/ {
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2013-03-14 02:07:37 +07:00
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interrupt-parent = <&intc>;
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2013-11-17 01:17:29 +07:00
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aliases {
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ethernet0 = &emac;
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};
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2014-11-14 22:34:34 +07:00
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chosen {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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2014-11-18 18:07:13 +07:00
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framebuffer@0 {
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2015-05-03 16:53:07 +07:00
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compatible = "allwinner,simple-framebuffer",
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"simple-framebuffer";
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2014-11-18 18:07:13 +07:00
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allwinner,pipeline = "de_be0-lcd0-hdmi";
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2017-08-24 00:23:33 +07:00
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clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_HDMI0>,
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<&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>,
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<&ccu CLK_TCON0_CH1>, <&ccu CLK_DRAM_DE_BE0>;
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2014-11-14 22:34:34 +07:00
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status = "disabled";
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};
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2015-01-19 20:01:17 +07:00
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framebuffer@1 {
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2015-05-03 16:53:07 +07:00
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compatible = "allwinner,simple-framebuffer",
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"simple-framebuffer";
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2015-01-19 20:01:17 +07:00
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allwinner,pipeline = "de_fe0-de_be0-lcd0-hdmi";
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2017-08-24 00:23:33 +07:00
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clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_HDMI0>,
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<&ccu CLK_AHB_DE_BE0>, <&ccu CLK_AHB_DE_FE0>,
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<&ccu CLK_DE_BE0>, <&ccu CLK_AHB_DE_FE0>,
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<&ccu CLK_TCON0_CH1>, <&ccu CLK_HDMI>,
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<&ccu CLK_DRAM_DE_FE0>, <&ccu CLK_DRAM_DE_BE0>;
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2015-01-19 20:01:17 +07:00
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status = "disabled";
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};
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2015-01-19 20:05:12 +07:00
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framebuffer@2 {
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compatible = "allwinner,simple-framebuffer",
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"simple-framebuffer";
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allwinner,pipeline = "de_fe0-de_be0-lcd0";
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2017-08-24 00:23:33 +07:00
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clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_DE_BE0>,
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<&ccu CLK_AHB_DE_FE0>, <&ccu CLK_DE_BE0>,
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<&ccu CLK_AHB_DE_FE0>, <&ccu CLK_TCON0_CH0>,
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<&ccu CLK_DRAM_DE_FE0>, <&ccu CLK_DRAM_DE_BE0>;
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2015-01-19 20:05:12 +07:00
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status = "disabled";
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};
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framebuffer@3 {
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compatible = "allwinner,simple-framebuffer",
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"simple-framebuffer";
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allwinner,pipeline = "de_fe0-de_be0-lcd0-tve0";
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2017-08-24 00:23:33 +07:00
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clocks = <&ccu CLK_AHB_TVE0>, <&ccu CLK_AHB_LCD0>,
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<&ccu CLK_AHB_DE_BE0>, <&ccu CLK_AHB_DE_FE0>,
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<&ccu CLK_DE_BE0>, <&ccu CLK_AHB_DE_FE0>,
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<&ccu CLK_TCON0_CH1>, <&ccu CLK_DRAM_TVE0>,
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<&ccu CLK_DRAM_DE_FE0>, <&ccu CLK_DRAM_DE_BE0>;
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2015-01-19 20:05:12 +07:00
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status = "disabled";
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};
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2014-11-14 22:34:34 +07:00
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};
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2013-03-14 02:07:37 +07:00
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cpus {
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2013-06-10 21:48:36 +07:00
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#address-cells = <1>;
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#size-cells = <0>;
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2015-01-06 09:35:23 +07:00
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cpu0: cpu@0 {
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2013-04-19 00:41:57 +07:00
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device_type = "cpu";
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2013-03-14 02:07:37 +07:00
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compatible = "arm,cortex-a8";
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2013-04-19 00:41:57 +07:00
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reg = <0x0>;
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2017-08-24 00:23:33 +07:00
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clocks = <&ccu CLK_CPU>;
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2015-01-06 09:35:23 +07:00
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clock-latency = <244144>; /* 8 32k periods */
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operating-points = <
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2015-05-03 16:54:35 +07:00
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/* kHz uV */
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2015-01-06 09:35:23 +07:00
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1008000 1400000
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2015-05-03 16:54:35 +07:00
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912000 1350000
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864000 1300000
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624000 1250000
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2015-01-06 09:35:23 +07:00
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>;
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#cooling-cells = <2>;
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cooling-min-level = <0>;
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2015-03-24 23:53:27 +07:00
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cooling-max-level = <3>;
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2013-03-14 02:07:37 +07:00
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};
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};
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2015-01-12 11:34:08 +07:00
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thermal-zones {
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cpu_thermal {
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/* milliseconds */
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polling-delay-passive = <250>;
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polling-delay = <1000>;
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thermal-sensors = <&rtp>;
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cooling-maps {
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map0 {
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trip = <&cpu_alert0>;
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cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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};
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};
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trips {
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cpu_alert0: cpu_alert0 {
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/* milliCelsius */
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temperature = <850000>;
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hysteresis = <2000>;
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type = "passive";
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};
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cpu_crit: cpu_crit {
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/* milliCelsius */
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temperature = <100000>;
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hysteresis = <2000>;
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type = "critical";
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};
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};
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2013-03-14 02:07:37 +07:00
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};
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};
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2012-11-26 21:46:12 +07:00
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memory {
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reg = <0x40000000 0x80000000>;
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};
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2013-01-26 21:36:54 +07:00
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2013-03-14 02:07:37 +07:00
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clocks {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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2014-02-03 08:51:41 +07:00
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osc24M: clk@01c20050 {
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2013-03-14 02:07:37 +07:00
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#clock-cells = <0>;
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2017-08-24 00:23:33 +07:00
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compatible = "fixed-clock";
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2013-04-09 20:48:04 +07:00
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clock-frequency = <24000000>;
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2014-02-03 08:51:41 +07:00
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clock-output-names = "osc24M";
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2013-03-14 02:07:37 +07:00
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};
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2014-02-03 08:51:41 +07:00
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osc32k: clk@0 {
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2013-03-14 02:07:37 +07:00
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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2014-02-03 08:51:41 +07:00
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clock-output-names = "osc32k";
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2013-03-14 02:07:37 +07:00
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};
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};
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2013-08-03 21:07:36 +07:00
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soc@01c00000 {
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2013-03-14 02:07:37 +07:00
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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2015-03-26 21:53:44 +07:00
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sram-controller@01c00000 {
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compatible = "allwinner,sun4i-a10-sram-controller";
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reg = <0x01c00000 0x30>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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sram_a: sram@00000000 {
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compatible = "mmio-sram";
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reg = <0x00000000 0xc000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x00000000 0xc000>;
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emac_sram: sram-section@8000 {
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compatible = "allwinner,sun4i-a10-sram-a3-a4";
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reg = <0x8000 0x4000>;
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status = "disabled";
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};
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};
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sram_d: sram@00010000 {
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compatible = "mmio-sram";
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reg = <0x00010000 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x00010000 0x1000>;
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otg_sram: sram-section@0000 {
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compatible = "allwinner,sun4i-a10-sram-d";
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reg = <0x0000 0x1000>;
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status = "disabled";
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};
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};
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};
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2014-08-05 03:09:57 +07:00
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dma: dma-controller@01c02000 {
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compatible = "allwinner,sun4i-a10-dma";
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reg = <0x01c02000 0x1000>;
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interrupts = <27>;
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2017-08-24 00:23:33 +07:00
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clocks = <&ccu CLK_AHB_DMA>;
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2014-08-05 03:09:57 +07:00
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#dma-cells = <2>;
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};
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2016-06-14 18:17:36 +07:00
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nfc: nand@01c03000 {
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compatible = "allwinner,sun4i-a10-nand";
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reg = <0x01c03000 0x1000>;
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interrupts = <37>;
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2017-08-24 00:23:33 +07:00
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clocks = <&ccu CLK_AHB_NAND>, <&ccu CLK_NAND>;
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2016-06-14 18:17:36 +07:00
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clock-names = "ahb", "mod";
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dmas = <&dma SUN4I_DMA_DEDICATED 3>;
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dma-names = "rxtx";
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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2014-02-23 04:35:55 +07:00
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spi0: spi@01c05000 {
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compatible = "allwinner,sun4i-a10-spi";
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reg = <0x01c05000 0x1000>;
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interrupts = <10>;
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2017-08-24 00:23:33 +07:00
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clocks = <&ccu CLK_AHB_SPI0>, <&ccu CLK_SPI0>;
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2014-02-23 04:35:55 +07:00
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clock-names = "ahb", "mod";
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2014-12-17 04:59:56 +07:00
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dmas = <&dma SUN4I_DMA_DEDICATED 27>,
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<&dma SUN4I_DMA_DEDICATED 26>;
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2014-08-05 03:10:00 +07:00
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dma-names = "rx", "tx";
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2014-02-23 04:35:55 +07:00
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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spi1: spi@01c06000 {
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compatible = "allwinner,sun4i-a10-spi";
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reg = <0x01c06000 0x1000>;
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interrupts = <11>;
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2017-08-24 00:23:33 +07:00
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clocks = <&ccu CLK_AHB_SPI1>, <&ccu CLK_SPI1>;
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2014-02-23 04:35:55 +07:00
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clock-names = "ahb", "mod";
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2014-12-17 04:59:56 +07:00
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dmas = <&dma SUN4I_DMA_DEDICATED 9>,
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<&dma SUN4I_DMA_DEDICATED 8>;
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2014-08-05 03:10:00 +07:00
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dma-names = "rx", "tx";
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2014-02-23 04:35:55 +07:00
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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2013-05-30 10:49:23 +07:00
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|
|
emac: ethernet@01c0b000 {
|
2014-02-02 20:49:13 +07:00
|
|
|
compatible = "allwinner,sun4i-a10-emac";
|
2013-05-30 10:49:23 +07:00
|
|
|
reg = <0x01c0b000 0x1000>;
|
|
|
|
|
interrupts = <55>;
|
2017-08-24 00:23:33 +07:00
|
|
|
clocks = <&ccu CLK_AHB_EMAC>;
|
2015-03-26 21:53:44 +07:00
|
|
|
allwinner,sram = <&emac_sram 1>;
|
2013-05-30 10:49:23 +07:00
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
2015-01-20 02:35:22 +07:00
|
|
|
mdio: mdio@01c0b080 {
|
2014-02-02 20:49:13 +07:00
|
|
|
compatible = "allwinner,sun4i-a10-mdio";
|
2013-05-30 10:49:23 +07:00
|
|
|
reg = <0x01c0b080 0x14>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
};
|
|
|
|
|
|
2014-05-02 22:57:18 +07:00
|
|
|
mmc0: mmc@01c0f000 {
|
|
|
|
|
compatible = "allwinner,sun4i-a10-mmc";
|
|
|
|
|
reg = <0x01c0f000 0x1000>;
|
2017-08-24 00:23:33 +07:00
|
|
|
clocks = <&ccu CLK_AHB_MMC0>, <&ccu CLK_MMC0>;
|
|
|
|
|
clock-names = "ahb", "mmc";
|
2014-05-02 22:57:18 +07:00
|
|
|
interrupts = <32>;
|
|
|
|
|
status = "disabled";
|
2015-03-10 22:27:09 +07:00
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
2014-05-02 22:57:18 +07:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
mmc1: mmc@01c10000 {
|
|
|
|
|
compatible = "allwinner,sun4i-a10-mmc";
|
|
|
|
|
reg = <0x01c10000 0x1000>;
|
2017-08-24 00:23:33 +07:00
|
|
|
clocks = <&ccu CLK_AHB_MMC1>, <&ccu CLK_MMC1>;
|
|
|
|
|
clock-names = "ahb", "mmc";
|
2014-05-02 22:57:18 +07:00
|
|
|
interrupts = <33>;
|
|
|
|
|
status = "disabled";
|
2015-03-10 22:27:09 +07:00
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
2014-05-02 22:57:18 +07:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
mmc2: mmc@01c11000 {
|
|
|
|
|
compatible = "allwinner,sun4i-a10-mmc";
|
|
|
|
|
reg = <0x01c11000 0x1000>;
|
2017-08-24 00:23:33 +07:00
|
|
|
clocks = <&ccu CLK_AHB_MMC2>, <&ccu CLK_MMC2>;
|
|
|
|
|
clock-names = "ahb", "mmc";
|
2014-05-02 22:57:18 +07:00
|
|
|
interrupts = <34>;
|
|
|
|
|
status = "disabled";
|
2015-03-10 22:27:09 +07:00
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
2014-05-02 22:57:18 +07:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
mmc3: mmc@01c12000 {
|
|
|
|
|
compatible = "allwinner,sun4i-a10-mmc";
|
|
|
|
|
reg = <0x01c12000 0x1000>;
|
2017-08-24 00:23:33 +07:00
|
|
|
clocks = <&ccu CLK_AHB_MMC3>, <&ccu CLK_MMC3>;
|
|
|
|
|
clock-names = "ahb", "mmc";
|
2014-05-02 22:57:18 +07:00
|
|
|
interrupts = <35>;
|
|
|
|
|
status = "disabled";
|
2015-03-10 22:27:09 +07:00
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
2014-05-02 22:57:18 +07:00
|
|
|
};
|
|
|
|
|
|
2015-02-04 01:17:35 +07:00
|
|
|
usb_otg: usb@01c13000 {
|
|
|
|
|
compatible = "allwinner,sun4i-a10-musb";
|
|
|
|
|
reg = <0x01c13000 0x0400>;
|
2017-08-24 00:23:33 +07:00
|
|
|
clocks = <&ccu CLK_AHB_OTG>;
|
2015-02-04 01:17:35 +07:00
|
|
|
interrupts = <38>;
|
|
|
|
|
interrupt-names = "mc";
|
|
|
|
|
phys = <&usbphy 0>;
|
|
|
|
|
phy-names = "usb";
|
|
|
|
|
extcon = <&usbphy 0>;
|
|
|
|
|
allwinner,sram = <&otg_sram 1>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
2014-03-02 02:26:23 +07:00
|
|
|
usbphy: phy@01c13400 {
|
|
|
|
|
#phy-cells = <1>;
|
|
|
|
|
compatible = "allwinner,sun4i-a10-usb-phy";
|
|
|
|
|
reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
|
|
|
|
|
reg-names = "phy_ctrl", "pmu1", "pmu2";
|
2017-08-24 00:23:33 +07:00
|
|
|
clocks = <&ccu CLK_USB_PHY>;
|
2014-03-02 02:26:23 +07:00
|
|
|
clock-names = "usb_phy";
|
2017-08-24 00:23:33 +07:00
|
|
|
resets = <&ccu RST_USB_PHY0>,
|
|
|
|
|
<&ccu RST_USB_PHY1>,
|
|
|
|
|
<&ccu RST_USB_PHY2>;
|
2014-12-18 18:10:35 +07:00
|
|
|
reset-names = "usb0_reset", "usb1_reset", "usb2_reset";
|
2014-03-02 02:26:23 +07:00
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
ehci0: usb@01c14000 {
|
|
|
|
|
compatible = "allwinner,sun4i-a10-ehci", "generic-ehci";
|
|
|
|
|
reg = <0x01c14000 0x100>;
|
|
|
|
|
interrupts = <39>;
|
2017-08-24 00:23:33 +07:00
|
|
|
clocks = <&ccu CLK_AHB_EHCI0>;
|
2014-03-02 02:26:23 +07:00
|
|
|
phys = <&usbphy 1>;
|
|
|
|
|
phy-names = "usb";
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
ohci0: usb@01c14400 {
|
|
|
|
|
compatible = "allwinner,sun4i-a10-ohci", "generic-ohci";
|
|
|
|
|
reg = <0x01c14400 0x100>;
|
|
|
|
|
interrupts = <64>;
|
2017-08-24 00:23:33 +07:00
|
|
|
clocks = <&ccu CLK_USB_OHCI0>, <&ccu CLK_AHB_OHCI0>;
|
2014-03-02 02:26:23 +07:00
|
|
|
phys = <&usbphy 1>;
|
|
|
|
|
phy-names = "usb";
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
2015-07-17 21:39:38 +07:00
|
|
|
crypto: crypto-engine@01c15000 {
|
|
|
|
|
compatible = "allwinner,sun4i-a10-crypto";
|
|
|
|
|
reg = <0x01c15000 0x1000>;
|
|
|
|
|
interrupts = <86>;
|
2017-08-24 00:23:33 +07:00
|
|
|
clocks = <&ccu CLK_AHB_SS>, <&ccu CLK_SS>;
|
2015-07-17 21:39:38 +07:00
|
|
|
clock-names = "ahb", "mod";
|
|
|
|
|
};
|
|
|
|
|
|
2014-02-23 04:35:55 +07:00
|
|
|
spi2: spi@01c17000 {
|
|
|
|
|
compatible = "allwinner,sun4i-a10-spi";
|
|
|
|
|
reg = <0x01c17000 0x1000>;
|
|
|
|
|
interrupts = <12>;
|
2017-08-24 00:23:33 +07:00
|
|
|
clocks = <&ccu CLK_AHB_SPI2>, <&ccu CLK_SPI2>;
|
2014-02-23 04:35:55 +07:00
|
|
|
clock-names = "ahb", "mod";
|
2014-12-17 04:59:56 +07:00
|
|
|
dmas = <&dma SUN4I_DMA_DEDICATED 29>,
|
|
|
|
|
<&dma SUN4I_DMA_DEDICATED 28>;
|
2014-08-05 03:10:00 +07:00
|
|
|
dma-names = "rx", "tx";
|
2014-02-23 04:35:55 +07:00
|
|
|
status = "disabled";
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
};
|
|
|
|
|
|
2014-03-02 02:26:21 +07:00
|
|
|
ahci: sata@01c18000 {
|
|
|
|
|
compatible = "allwinner,sun4i-a10-ahci";
|
|
|
|
|
reg = <0x01c18000 0x1000>;
|
|
|
|
|
interrupts = <56>;
|
2017-08-24 00:23:33 +07:00
|
|
|
clocks = <&ccu CLK_AHB_SATA>, <&ccu CLK_SATA>;
|
2014-03-02 02:26:21 +07:00
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
2014-03-02 02:26:23 +07:00
|
|
|
ehci1: usb@01c1c000 {
|
|
|
|
|
compatible = "allwinner,sun4i-a10-ehci", "generic-ehci";
|
|
|
|
|
reg = <0x01c1c000 0x100>;
|
|
|
|
|
interrupts = <40>;
|
2017-08-24 00:23:33 +07:00
|
|
|
clocks = <&ccu CLK_AHB_EHCI1>;
|
2014-03-02 02:26:23 +07:00
|
|
|
phys = <&usbphy 2>;
|
|
|
|
|
phy-names = "usb";
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
ohci1: usb@01c1c400 {
|
|
|
|
|
compatible = "allwinner,sun4i-a10-ohci", "generic-ohci";
|
|
|
|
|
reg = <0x01c1c400 0x100>;
|
|
|
|
|
interrupts = <65>;
|
2017-08-24 00:23:33 +07:00
|
|
|
clocks = <&ccu CLK_USB_OHCI1>, <&ccu CLK_AHB_OHCI1>;
|
2014-03-02 02:26:23 +07:00
|
|
|
phys = <&usbphy 2>;
|
|
|
|
|
phy-names = "usb";
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
2014-02-23 04:35:55 +07:00
|
|
|
spi3: spi@01c1f000 {
|
|
|
|
|
compatible = "allwinner,sun4i-a10-spi";
|
|
|
|
|
reg = <0x01c1f000 0x1000>;
|
|
|
|
|
interrupts = <50>;
|
2017-08-24 00:23:33 +07:00
|
|
|
clocks = <&ccu CLK_AHB_SPI3>, <&ccu CLK_SPI3>;
|
2014-02-23 04:35:55 +07:00
|
|
|
clock-names = "ahb", "mod";
|
2014-12-17 04:59:56 +07:00
|
|
|
dmas = <&dma SUN4I_DMA_DEDICATED 31>,
|
|
|
|
|
<&dma SUN4I_DMA_DEDICATED 30>;
|
2014-08-05 03:10:00 +07:00
|
|
|
dma-names = "rx", "tx";
|
2014-02-23 04:35:55 +07:00
|
|
|
status = "disabled";
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
};
|
|
|
|
|
|
2017-08-24 00:23:33 +07:00
|
|
|
ccu: clock@01c20000 {
|
|
|
|
|
compatible = "allwinner,sun4i-a10-ccu";
|
|
|
|
|
reg = <0x01c20000 0x400>;
|
|
|
|
|
clocks = <&osc24M>, <&osc32k>;
|
|
|
|
|
clock-names = "hosc", "losc";
|
|
|
|
|
#clock-cells = <1>;
|
|
|
|
|
#reset-cells = <1>;
|
|
|
|
|
};
|
|
|
|
|
|
2013-03-14 02:07:37 +07:00
|
|
|
intc: interrupt-controller@01c20400 {
|
2014-02-08 03:50:26 +07:00
|
|
|
compatible = "allwinner,sun4i-a10-ic";
|
2013-03-14 02:07:37 +07:00
|
|
|
reg = <0x01c20400 0x400>;
|
|
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <1>;
|
|
|
|
|
};
|
|
|
|
|
|
2013-01-28 01:26:05 +07:00
|
|
|
pio: pinctrl@01c20800 {
|
2013-01-26 21:36:54 +07:00
|
|
|
compatible = "allwinner,sun4i-a10-pinctrl";
|
|
|
|
|
reg = <0x01c20800 0x400>;
|
2013-04-06 20:00:48 +07:00
|
|
|
interrupts = <28>;
|
2017-08-24 00:23:33 +07:00
|
|
|
clocks = <&ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
|
2016-10-19 16:15:27 +07:00
|
|
|
clock-names = "apb", "hosc", "losc";
|
2013-01-28 01:26:05 +07:00
|
|
|
gpio-controller;
|
2013-04-06 20:00:48 +07:00
|
|
|
interrupt-controller;
|
2015-06-17 16:44:24 +07:00
|
|
|
#interrupt-cells = <3>;
|
2013-01-28 01:26:05 +07:00
|
|
|
#gpio-cells = <3>;
|
2013-01-26 21:36:55 +07:00
|
|
|
|
2017-04-04 00:00:12 +07:00
|
|
|
can0_pins_a: can0@0 {
|
|
|
|
|
pins = "PH20", "PH21";
|
|
|
|
|
function = "can";
|
|
|
|
|
};
|
|
|
|
|
|
2016-06-10 15:05:18 +07:00
|
|
|
emac_pins_a: emac0@0 {
|
2016-09-23 18:28:10 +07:00
|
|
|
pins = "PA0", "PA1", "PA2",
|
|
|
|
|
"PA3", "PA4", "PA5", "PA6",
|
|
|
|
|
"PA7", "PA8", "PA9", "PA10",
|
|
|
|
|
"PA11", "PA12", "PA13", "PA14",
|
|
|
|
|
"PA15", "PA16";
|
|
|
|
|
function = "emac";
|
2014-04-28 23:17:10 +07:00
|
|
|
};
|
|
|
|
|
|
2016-06-10 15:05:18 +07:00
|
|
|
i2c0_pins_a: i2c0@0 {
|
2016-09-23 18:28:10 +07:00
|
|
|
pins = "PB0", "PB1";
|
|
|
|
|
function = "i2c0";
|
2013-01-26 21:36:55 +07:00
|
|
|
};
|
|
|
|
|
|
2016-06-10 15:05:18 +07:00
|
|
|
i2c1_pins_a: i2c1@0 {
|
2016-09-23 18:28:10 +07:00
|
|
|
pins = "PB18", "PB19";
|
|
|
|
|
function = "i2c1";
|
2013-01-26 21:36:55 +07:00
|
|
|
};
|
|
|
|
|
|
2016-06-10 15:05:18 +07:00
|
|
|
i2c2_pins_a: i2c2@0 {
|
2016-09-23 18:28:10 +07:00
|
|
|
pins = "PB20", "PB21";
|
|
|
|
|
function = "i2c2";
|
2013-01-26 21:36:55 +07:00
|
|
|
};
|
2013-03-10 19:44:38 +07:00
|
|
|
|
2016-06-10 15:05:18 +07:00
|
|
|
ir0_rx_pins_a: ir0@0 {
|
2016-09-23 18:28:10 +07:00
|
|
|
pins = "PB4";
|
|
|
|
|
function = "ir0";
|
2013-03-10 19:44:38 +07:00
|
|
|
};
|
|
|
|
|
|
2016-06-10 15:05:18 +07:00
|
|
|
ir0_tx_pins_a: ir0@1 {
|
2016-09-23 18:28:10 +07:00
|
|
|
pins = "PB3";
|
|
|
|
|
function = "ir0";
|
2013-03-10 19:44:38 +07:00
|
|
|
};
|
|
|
|
|
|
2016-06-10 15:05:18 +07:00
|
|
|
ir1_rx_pins_a: ir1@0 {
|
2016-09-23 18:28:10 +07:00
|
|
|
pins = "PB23";
|
|
|
|
|
function = "ir1";
|
2013-03-10 19:44:38 +07:00
|
|
|
};
|
Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next
Pull networking updates from David Miller:
"This is a re-do of the net-next pull request for the current merge
window. The only difference from the one I made the other day is that
this has Eliezer's interface renames and the timeout handling changes
made based upon your feedback, as well as a few bug fixes that have
trickeled in.
Highlights:
1) Low latency device polling, eliminating the cost of interrupt
handling and context switches. Allows direct polling of a network
device from socket operations, such as recvmsg() and poll().
Currently ixgbe, mlx4, and bnx2x support this feature.
Full high level description, performance numbers, and design in
commit 0a4db187a999 ("Merge branch 'll_poll'")
From Eliezer Tamir.
2) With the routing cache removed, ip_check_mc_rcu() gets exercised
more than ever before in the case where we have lots of multicast
addresses. Use a hash table instead of a simple linked list, from
Eric Dumazet.
3) Add driver for Atheros CQA98xx 802.11ac wireless devices, from
Bartosz Markowski, Janusz Dziedzic, Kalle Valo, Marek Kwaczynski,
Marek Puzyniak, Michal Kazior, and Sujith Manoharan.
4) Support reporting the TUN device persist flag to userspace, from
Pavel Emelyanov.
5) Allow controlling network device VF link state using netlink, from
Rony Efraim.
6) Support GRE tunneling in openvswitch, from Pravin B Shelar.
7) Adjust SOCK_MIN_RCVBUF and SOCK_MIN_SNDBUF for modern times, from
Daniel Borkmann and Eric Dumazet.
8) Allow controlling of TCP quickack behavior on a per-route basis,
from Cong Wang.
9) Several bug fixes and improvements to vxlan from Stephen
Hemminger, Pravin B Shelar, and Mike Rapoport. In particular,
support receiving on multiple UDP ports.
10) Major cleanups, particular in the area of debugging and cookie
lifetime handline, to the SCTP protocol code. From Daniel
Borkmann.
11) Allow packets to cross network namespaces when traversing tunnel
devices. From Nicolas Dichtel.
12) Allow monitoring netlink traffic via AF_PACKET sockets, in a
manner akin to how we monitor real network traffic via ptype_all.
From Daniel Borkmann.
13) Several bug fixes and improvements for the new alx device driver,
from Johannes Berg.
14) Fix scalability issues in the netem packet scheduler's time queue,
by using an rbtree. From Eric Dumazet.
15) Several bug fixes in TCP loss recovery handling, from Yuchung
Cheng.
16) Add support for GSO segmentation of MPLS packets, from Simon
Horman.
17) Make network notifiers have a real data type for the opaque
pointer that's passed into them. Use this to properly handle
network device flag changes in arp_netdev_event(). From Jiri
Pirko and Timo Teräs.
18) Convert several drivers over to module_pci_driver(), from Peter
Huewe.
19) tcp_fixup_rcvbuf() can loop 500 times over loopback, just use a
O(1) calculation instead. From Eric Dumazet.
20) Support setting of explicit tunnel peer addresses in ipv6, just
like ipv4. From Nicolas Dichtel.
21) Protect x86 BPF JIT against spraying attacks, from Eric Dumazet.
22) Prevent a single high rate flow from overruning an individual cpu
during RX packet processing via selective flow shedding. From
Willem de Bruijn.
23) Don't use spinlocks in TCP md5 signing fast paths, from Eric
Dumazet.
24) Don't just drop GSO packets which are above the TBF scheduler's
burst limit, chop them up so they are in-bounds instead. Also
from Eric Dumazet.
25) VLAN offloads are missed when configured on top of a bridge, fix
from Vlad Yasevich.
26) Support IPV6 in ping sockets. From Lorenzo Colitti.
27) Receive flow steering targets should be updated at poll() time
too, from David Majnemer.
28) Fix several corner case regressions in PMTU/redirect handling due
to the routing cache removal, from Timo Teräs.
29) We have to be mindful of ipv4 mapped ipv6 sockets in
upd_v6_push_pending_frames(). From Hannes Frederic Sowa.
30) Fix L2TP sequence number handling bugs, from James Chapman."
* git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next: (1214 commits)
drivers/net: caif: fix wrong rtnl_is_locked() usage
drivers/net: enic: release rtnl_lock on error-path
vhost-net: fix use-after-free in vhost_net_flush
net: mv643xx_eth: do not use port number as platform device id
net: sctp: confirm route during forward progress
virtio_net: fix race in RX VQ processing
virtio: support unlocked queue poll
net/cadence/macb: fix bug/typo in extracting gem_irq_read_clear bit
Documentation: Fix references to defunct linux-net@vger.kernel.org
net/fs: change busy poll time accounting
net: rename low latency sockets functions to busy poll
bridge: fix some kernel warning in multicast timer
sfc: Fix memory leak when discarding scattered packets
sit: fix tunnel update via netlink
dt:net:stmmac: Add dt specific phy reset callback support.
dt:net:stmmac: Add support to dwmac version 3.610 and 3.710
dt:net:stmmac: Allocate platform data only if its NULL.
net:stmmac: fix memleak in the open method
ipv6: rt6_check_neigh should successfully verify neigh if no NUD information are available
net: ipv6: fix wrong ping_v6_sendmsg return value
...
2013-07-10 08:24:39 +07:00
|
|
|
|
2016-06-10 15:05:18 +07:00
|
|
|
ir1_tx_pins_a: ir1@1 {
|
2016-09-23 18:28:10 +07:00
|
|
|
pins = "PB22";
|
|
|
|
|
function = "ir1";
|
2013-05-30 10:49:22 +07:00
|
|
|
};
|
2014-05-02 22:57:19 +07:00
|
|
|
|
|
|
|
|
mmc0_pins_a: mmc0@0 {
|
2016-09-23 18:28:10 +07:00
|
|
|
pins = "PF0", "PF1", "PF2",
|
|
|
|
|
"PF3", "PF4", "PF5";
|
|
|
|
|
function = "mmc0";
|
|
|
|
|
drive-strength = <30>;
|
2016-11-17 16:34:38 +07:00
|
|
|
bias-pull-up;
|
2014-05-02 22:57:19 +07:00
|
|
|
};
|
|
|
|
|
|
2016-06-10 15:05:18 +07:00
|
|
|
ps20_pins_a: ps20@0 {
|
2016-09-23 18:28:10 +07:00
|
|
|
pins = "PI20", "PI21";
|
|
|
|
|
function = "ps2";
|
2014-07-01 04:57:58 +07:00
|
|
|
};
|
|
|
|
|
|
2016-06-10 15:05:18 +07:00
|
|
|
ps21_pins_a: ps21@0 {
|
2016-09-23 18:28:10 +07:00
|
|
|
pins = "PH12", "PH13";
|
|
|
|
|
function = "ps2";
|
2015-05-02 18:36:20 +07:00
|
|
|
};
|
|
|
|
|
|
2016-06-10 15:05:18 +07:00
|
|
|
pwm0_pins_a: pwm0@0 {
|
2016-09-23 18:28:10 +07:00
|
|
|
pins = "PB2";
|
|
|
|
|
function = "pwm";
|
2015-05-02 18:36:20 +07:00
|
|
|
};
|
|
|
|
|
|
2016-06-10 15:05:18 +07:00
|
|
|
pwm1_pins_a: pwm1@0 {
|
2016-09-23 18:28:10 +07:00
|
|
|
pins = "PI3";
|
|
|
|
|
function = "pwm";
|
2014-07-01 04:57:58 +07:00
|
|
|
};
|
2014-12-08 17:14:01 +07:00
|
|
|
|
2016-06-10 15:05:18 +07:00
|
|
|
spdif_tx_pins_a: spdif@0 {
|
2016-09-23 18:28:10 +07:00
|
|
|
pins = "PB13";
|
|
|
|
|
function = "spdif";
|
|
|
|
|
bias-pull-up;
|
2016-06-10 15:05:18 +07:00
|
|
|
};
|
|
|
|
|
|
2014-12-08 17:14:01 +07:00
|
|
|
spi0_pins_a: spi0@0 {
|
2016-09-23 18:28:10 +07:00
|
|
|
pins = "PI11", "PI12", "PI13";
|
|
|
|
|
function = "spi0";
|
2015-05-03 14:25:41 +07:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
spi0_cs0_pins_a: spi0_cs0@0 {
|
2016-09-23 18:28:10 +07:00
|
|
|
pins = "PI10";
|
|
|
|
|
function = "spi0";
|
2014-12-08 17:14:01 +07:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
spi1_pins_a: spi1@0 {
|
2016-09-23 18:28:10 +07:00
|
|
|
pins = "PI17", "PI18", "PI19";
|
|
|
|
|
function = "spi1";
|
2015-05-03 14:25:41 +07:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
spi1_cs0_pins_a: spi1_cs0@0 {
|
2016-09-23 18:28:10 +07:00
|
|
|
pins = "PI16";
|
|
|
|
|
function = "spi1";
|
2014-12-08 17:14:01 +07:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
spi2_pins_a: spi2@0 {
|
2016-09-23 18:28:10 +07:00
|
|
|
pins = "PC20", "PC21", "PC22";
|
|
|
|
|
function = "spi2";
|
2014-12-08 17:14:01 +07:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
spi2_pins_b: spi2@1 {
|
2016-09-23 18:28:10 +07:00
|
|
|
pins = "PB15", "PB16", "PB17";
|
|
|
|
|
function = "spi2";
|
2015-05-03 14:25:41 +07:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
spi2_cs0_pins_a: spi2_cs0@0 {
|
2016-09-23 18:28:10 +07:00
|
|
|
pins = "PC19";
|
|
|
|
|
function = "spi2";
|
2015-05-03 14:25:41 +07:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
spi2_cs0_pins_b: spi2_cs0@1 {
|
2016-09-23 18:28:10 +07:00
|
|
|
pins = "PB14";
|
|
|
|
|
function = "spi2";
|
2014-12-08 17:14:01 +07:00
|
|
|
};
|
2015-01-25 20:40:09 +07:00
|
|
|
|
2016-06-10 15:05:18 +07:00
|
|
|
uart0_pins_a: uart0@0 {
|
2016-09-23 18:28:10 +07:00
|
|
|
pins = "PB22", "PB23";
|
|
|
|
|
function = "uart0";
|
2015-01-25 20:40:09 +07:00
|
|
|
};
|
|
|
|
|
|
2016-06-10 15:05:18 +07:00
|
|
|
uart0_pins_b: uart0@1 {
|
2016-09-23 18:28:10 +07:00
|
|
|
pins = "PF2", "PF4";
|
|
|
|
|
function = "uart0";
|
2014-07-01 04:57:58 +07:00
|
|
|
};
|
2016-03-22 03:00:59 +07:00
|
|
|
|
2016-06-10 15:05:18 +07:00
|
|
|
uart1_pins_a: uart1@0 {
|
2016-09-23 18:28:10 +07:00
|
|
|
pins = "PA10", "PA11";
|
|
|
|
|
function = "uart1";
|
2016-03-22 03:00:59 +07:00
|
|
|
};
|
2013-01-26 21:36:54 +07:00
|
|
|
};
|
2013-02-21 08:25:03 +07:00
|
|
|
|
2013-03-14 02:07:37 +07:00
|
|
|
timer@01c20c00 {
|
2014-02-06 16:40:32 +07:00
|
|
|
compatible = "allwinner,sun4i-a10-timer";
|
2013-03-14 02:07:37 +07:00
|
|
|
reg = <0x01c20c00 0x90>;
|
|
|
|
|
interrupts = <22>;
|
|
|
|
|
clocks = <&osc24M>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
wdt: watchdog@01c20c90 {
|
2014-02-08 04:29:26 +07:00
|
|
|
compatible = "allwinner,sun4i-a10-wdt";
|
2013-03-14 02:07:37 +07:00
|
|
|
reg = <0x01c20c90 0x10>;
|
|
|
|
|
};
|
|
|
|
|
|
2013-10-17 01:30:26 +07:00
|
|
|
rtc: rtc@01c20d00 {
|
2014-04-04 04:50:03 +07:00
|
|
|
compatible = "allwinner,sun4i-a10-rtc";
|
2013-10-17 01:30:26 +07:00
|
|
|
reg = <0x01c20d00 0x20>;
|
|
|
|
|
interrupts = <24>;
|
|
|
|
|
};
|
|
|
|
|
|
2014-04-28 23:17:11 +07:00
|
|
|
pwm: pwm@01c20e00 {
|
|
|
|
|
compatible = "allwinner,sun4i-a10-pwm";
|
|
|
|
|
reg = <0x01c20e00 0xc>;
|
|
|
|
|
clocks = <&osc24M>;
|
|
|
|
|
#pwm-cells = <3>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
2016-03-22 03:01:03 +07:00
|
|
|
spdif: spdif@01c21000 {
|
|
|
|
|
#sound-dai-cells = <0>;
|
|
|
|
|
compatible = "allwinner,sun4i-a10-spdif";
|
|
|
|
|
reg = <0x01c21000 0x400>;
|
|
|
|
|
interrupts = <13>;
|
2017-08-24 00:23:33 +07:00
|
|
|
clocks = <&ccu CLK_APB0_SPDIF>, <&ccu CLK_SPDIF>;
|
2016-03-22 03:01:03 +07:00
|
|
|
clock-names = "apb", "spdif";
|
|
|
|
|
dmas = <&dma SUN4I_DMA_NORMAL 2>,
|
|
|
|
|
<&dma SUN4I_DMA_NORMAL 2>;
|
|
|
|
|
dma-names = "rx", "tx";
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
2014-07-01 04:57:58 +07:00
|
|
|
ir0: ir@01c21800 {
|
|
|
|
|
compatible = "allwinner,sun4i-a10-ir";
|
2017-08-24 00:23:33 +07:00
|
|
|
clocks = <&ccu CLK_APB0_IR0>, <&ccu CLK_IR0>;
|
2014-07-01 04:57:58 +07:00
|
|
|
clock-names = "apb", "ir";
|
|
|
|
|
interrupts = <5>;
|
|
|
|
|
reg = <0x01c21800 0x40>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
ir1: ir@01c21c00 {
|
|
|
|
|
compatible = "allwinner,sun4i-a10-ir";
|
2017-08-24 00:23:33 +07:00
|
|
|
clocks = <&ccu CLK_APB0_IR1>, <&ccu CLK_IR1>;
|
2014-07-01 04:57:58 +07:00
|
|
|
clock-names = "apb", "ir";
|
|
|
|
|
interrupts = <6>;
|
|
|
|
|
reg = <0x01c21c00 0x40>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
2014-12-23 17:13:20 +07:00
|
|
|
lradc: lradc@01c22800 {
|
|
|
|
|
compatible = "allwinner,sun4i-a10-lradc-keys";
|
|
|
|
|
reg = <0x01c22800 0x100>;
|
|
|
|
|
interrupts = <31>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
2014-07-22 18:06:48 +07:00
|
|
|
codec: codec@01c22c00 {
|
|
|
|
|
#sound-dai-cells = <0>;
|
|
|
|
|
compatible = "allwinner,sun4i-a10-codec";
|
|
|
|
|
reg = <0x01c22c00 0x40>;
|
|
|
|
|
interrupts = <30>;
|
2017-08-24 00:23:33 +07:00
|
|
|
clocks = <&ccu CLK_APB0_CODEC>, <&ccu CLK_CODEC>;
|
2014-07-22 18:06:48 +07:00
|
|
|
clock-names = "apb", "codec";
|
|
|
|
|
dmas = <&dma SUN4I_DMA_NORMAL 19>,
|
|
|
|
|
<&dma SUN4I_DMA_NORMAL 19>;
|
|
|
|
|
dma-names = "rx", "tx";
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
2013-09-03 17:33:28 +07:00
|
|
|
sid: eeprom@01c23800 {
|
2014-02-08 04:20:40 +07:00
|
|
|
compatible = "allwinner,sun4i-a10-sid";
|
2013-09-03 17:33:28 +07:00
|
|
|
reg = <0x01c23800 0x10>;
|
|
|
|
|
};
|
|
|
|
|
|
2013-12-31 23:20:50 +07:00
|
|
|
rtp: rtp@01c25000 {
|
2014-02-02 20:52:40 +07:00
|
|
|
compatible = "allwinner,sun4i-a10-ts";
|
2013-12-31 23:20:50 +07:00
|
|
|
reg = <0x01c25000 0x100>;
|
|
|
|
|
interrupts = <29>;
|
2015-01-06 09:35:15 +07:00
|
|
|
#thermal-sensor-cells = <0>;
|
2013-12-31 23:20:50 +07:00
|
|
|
};
|
|
|
|
|
|
2013-02-21 08:25:03 +07:00
|
|
|
uart0: serial@01c28000 {
|
|
|
|
|
compatible = "snps,dw-apb-uart";
|
|
|
|
|
reg = <0x01c28000 0x400>;
|
|
|
|
|
interrupts = <1>;
|
|
|
|
|
reg-shift = <2>;
|
|
|
|
|
reg-io-width = <4>;
|
2017-08-24 00:23:33 +07:00
|
|
|
clocks = <&ccu CLK_APB1_UART0>;
|
2013-02-21 08:25:03 +07:00
|
|
|
status = "disabled";
|
|
|
|
|
};
|
2013-02-21 08:38:27 +07:00
|
|
|
|
2013-03-14 02:07:37 +07:00
|
|
|
uart1: serial@01c28400 {
|
|
|
|
|
compatible = "snps,dw-apb-uart";
|
|
|
|
|
reg = <0x01c28400 0x400>;
|
|
|
|
|
interrupts = <2>;
|
|
|
|
|
reg-shift = <2>;
|
|
|
|
|
reg-io-width = <4>;
|
2017-08-24 00:23:33 +07:00
|
|
|
clocks = <&ccu CLK_APB1_UART1>;
|
2013-03-14 02:07:37 +07:00
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
2013-02-21 08:38:27 +07:00
|
|
|
uart2: serial@01c28800 {
|
|
|
|
|
compatible = "snps,dw-apb-uart";
|
|
|
|
|
reg = <0x01c28800 0x400>;
|
|
|
|
|
interrupts = <3>;
|
|
|
|
|
reg-shift = <2>;
|
|
|
|
|
reg-io-width = <4>;
|
2017-08-24 00:23:33 +07:00
|
|
|
clocks = <&ccu CLK_APB1_UART2>;
|
2013-02-21 08:38:27 +07:00
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
2013-03-14 02:07:37 +07:00
|
|
|
uart3: serial@01c28c00 {
|
|
|
|
|
compatible = "snps,dw-apb-uart";
|
|
|
|
|
reg = <0x01c28c00 0x400>;
|
|
|
|
|
interrupts = <4>;
|
|
|
|
|
reg-shift = <2>;
|
|
|
|
|
reg-io-width = <4>;
|
2017-08-24 00:23:33 +07:00
|
|
|
clocks = <&ccu CLK_APB1_UART3>;
|
2013-03-14 02:07:37 +07:00
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
2013-02-21 08:38:27 +07:00
|
|
|
uart4: serial@01c29000 {
|
|
|
|
|
compatible = "snps,dw-apb-uart";
|
|
|
|
|
reg = <0x01c29000 0x400>;
|
|
|
|
|
interrupts = <17>;
|
|
|
|
|
reg-shift = <2>;
|
|
|
|
|
reg-io-width = <4>;
|
2017-08-24 00:23:33 +07:00
|
|
|
clocks = <&ccu CLK_APB1_UART4>;
|
2013-02-21 08:38:27 +07:00
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
uart5: serial@01c29400 {
|
|
|
|
|
compatible = "snps,dw-apb-uart";
|
|
|
|
|
reg = <0x01c29400 0x400>;
|
|
|
|
|
interrupts = <18>;
|
|
|
|
|
reg-shift = <2>;
|
|
|
|
|
reg-io-width = <4>;
|
2017-08-24 00:23:33 +07:00
|
|
|
clocks = <&ccu CLK_APB1_UART5>;
|
2013-02-21 08:38:27 +07:00
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
uart6: serial@01c29800 {
|
|
|
|
|
compatible = "snps,dw-apb-uart";
|
|
|
|
|
reg = <0x01c29800 0x400>;
|
|
|
|
|
interrupts = <19>;
|
|
|
|
|
reg-shift = <2>;
|
|
|
|
|
reg-io-width = <4>;
|
2017-08-24 00:23:33 +07:00
|
|
|
clocks = <&ccu CLK_APB1_UART6>;
|
2013-02-21 08:38:27 +07:00
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
uart7: serial@01c29c00 {
|
|
|
|
|
compatible = "snps,dw-apb-uart";
|
|
|
|
|
reg = <0x01c29c00 0x400>;
|
|
|
|
|
interrupts = <20>;
|
|
|
|
|
reg-shift = <2>;
|
|
|
|
|
reg-io-width = <4>;
|
2017-08-24 00:23:33 +07:00
|
|
|
clocks = <&ccu CLK_APB1_UART7>;
|
2013-02-21 08:38:27 +07:00
|
|
|
status = "disabled";
|
|
|
|
|
};
|
2013-03-10 19:34:36 +07:00
|
|
|
|
2017-04-05 01:36:27 +07:00
|
|
|
ps20: ps2@01c2a000 {
|
|
|
|
|
compatible = "allwinner,sun4i-a10-ps2";
|
|
|
|
|
reg = <0x01c2a000 0x400>;
|
|
|
|
|
interrupts = <62>;
|
2017-08-24 00:23:33 +07:00
|
|
|
clocks = <&ccu CLK_APB1_PS20>;
|
2017-04-05 01:36:27 +07:00
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
ps21: ps2@01c2a400 {
|
|
|
|
|
compatible = "allwinner,sun4i-a10-ps2";
|
|
|
|
|
reg = <0x01c2a400 0x400>;
|
|
|
|
|
interrupts = <63>;
|
2017-08-24 00:23:33 +07:00
|
|
|
clocks = <&ccu CLK_APB1_PS21>;
|
2017-04-05 01:36:27 +07:00
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
2013-03-10 19:34:36 +07:00
|
|
|
i2c0: i2c@01c2ac00 {
|
2014-03-31 19:54:58 +07:00
|
|
|
compatible = "allwinner,sun4i-a10-i2c";
|
2013-03-10 19:34:36 +07:00
|
|
|
reg = <0x01c2ac00 0x400>;
|
|
|
|
|
interrupts = <7>;
|
2017-08-24 00:23:33 +07:00
|
|
|
clocks = <&ccu CLK_APB1_I2C0>;
|
2013-03-10 19:34:36 +07:00
|
|
|
status = "disabled";
|
2014-04-13 18:41:03 +07:00
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
2013-03-10 19:34:36 +07:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
i2c1: i2c@01c2b000 {
|
2014-03-31 19:54:58 +07:00
|
|
|
compatible = "allwinner,sun4i-a10-i2c";
|
2013-03-10 19:34:36 +07:00
|
|
|
reg = <0x01c2b000 0x400>;
|
|
|
|
|
interrupts = <8>;
|
2017-08-24 00:23:33 +07:00
|
|
|
clocks = <&ccu CLK_APB1_I2C1>;
|
2013-03-10 19:34:36 +07:00
|
|
|
status = "disabled";
|
2014-04-13 18:41:03 +07:00
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
2013-03-10 19:34:36 +07:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
i2c2: i2c@01c2b400 {
|
2014-03-31 19:54:58 +07:00
|
|
|
compatible = "allwinner,sun4i-a10-i2c";
|
2013-03-10 19:34:36 +07:00
|
|
|
reg = <0x01c2b400 0x400>;
|
|
|
|
|
interrupts = <9>;
|
2017-08-24 00:23:33 +07:00
|
|
|
clocks = <&ccu CLK_APB1_I2C2>;
|
2013-03-10 19:34:36 +07:00
|
|
|
status = "disabled";
|
2014-04-13 18:41:03 +07:00
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
2013-03-10 19:34:36 +07:00
|
|
|
};
|
2015-01-25 20:40:08 +07:00
|
|
|
|
2017-04-04 00:00:11 +07:00
|
|
|
can0: can@01c2bc00 {
|
|
|
|
|
compatible = "allwinner,sun4i-a10-can";
|
|
|
|
|
reg = <0x01c2bc00 0x400>;
|
|
|
|
|
interrupts = <26>;
|
2017-08-24 00:23:33 +07:00
|
|
|
clocks = <&ccu CLK_APB1_CAN>;
|
2017-04-04 00:00:11 +07:00
|
|
|
status = "disabled";
|
|
|
|
|
};
|
2013-01-26 21:36:54 +07:00
|
|
|
};
|
2012-11-26 21:46:12 +07:00
|
|
|
};
|