mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-27 02:35:23 +07:00
28fbb9c539
dtc recently added PCI bus checks. Fix these warnings. Signed-off-by: Rob Herring <robh@kernel.org> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Andrew Lunn <andrew@lunn.ch> Cc: Gregory Clement <gregory.clement@free-electrons.com> Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
141 lines
3.6 KiB
Plaintext
141 lines
3.6 KiB
Plaintext
/ {
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mbus@f1000000 {
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pciec: pcie@82000000 {
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compatible = "marvell,kirkwood-pcie";
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status = "disabled";
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device_type = "pci";
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#address-cells = <3>;
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#size-cells = <2>;
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bus-range = <0x00 0xff>;
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ranges =
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<0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
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0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
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0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
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0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
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0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
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0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 1.0 MEM */
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0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 1.0 IO */>;
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pcie0: pcie@1,0 {
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device_type = "pci";
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assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>;
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reg = <0x0800 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
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0x81000000 0 0 0x81000000 0x1 0 1 0>;
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bus-range = <0x00 0xff>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &intc 9>;
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marvell,pcie-port = <0>;
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marvell,pcie-lane = <0>;
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clocks = <&gate_clk 2>;
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status = "disabled";
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};
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pcie1: pcie@2,0 {
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device_type = "pci";
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assigned-addresses = <0x82001000 0 0x00044000 0 0x2000>;
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reg = <0x1000 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
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0x81000000 0 0 0x81000000 0x2 0 1 0>;
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bus-range = <0x00 0xff>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &intc 10>;
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marvell,pcie-port = <1>;
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marvell,pcie-lane = <0>;
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clocks = <&gate_clk 18>;
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status = "disabled";
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};
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};
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};
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ocp@f1000000 {
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pinctrl: pin-controller@10000 {
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compatible = "marvell,88f6282-pinctrl";
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pmx_sata0: pmx-sata0 {
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marvell,pins = "mpp5", "mpp21", "mpp23";
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marvell,function = "sata0";
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};
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pmx_sata1: pmx-sata1 {
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marvell,pins = "mpp4", "mpp20", "mpp22";
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marvell,function = "sata1";
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};
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/*
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* Default I2C1 pinctrl setting on mpp36/mpp37,
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* overwrite marvell,pins on board level if required.
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*/
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pmx_twsi1: pmx-twsi1 {
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marvell,pins = "mpp36", "mpp37";
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marvell,function = "twsi1";
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};
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pmx_sdio: pmx-sdio {
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marvell,pins = "mpp12", "mpp13", "mpp14",
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"mpp15", "mpp16", "mpp17";
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marvell,function = "sdio";
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};
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};
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thermal: thermal@10078 {
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compatible = "marvell,kirkwood-thermal";
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reg = <0x10078 0x4>;
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status = "okay";
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};
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rtc: rtc@10300 {
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compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc";
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reg = <0x10300 0x20>;
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interrupts = <53>;
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clocks = <&gate_clk 7>;
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};
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i2c1: i2c@11100 {
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compatible = "marvell,mv64xxx-i2c";
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reg = <0x11100 0x20>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <32>;
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clock-frequency = <100000>;
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clocks = <&gate_clk 7>;
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pinctrl-0 = <&pmx_twsi1>;
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pinctrl-names = "default";
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status = "disabled";
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};
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sata: sata@80000 {
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compatible = "marvell,orion-sata";
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reg = <0x80000 0x5000>;
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interrupts = <21>;
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clocks = <&gate_clk 14>, <&gate_clk 15>;
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clock-names = "0", "1";
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phys = <&sata_phy0>, <&sata_phy1>;
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phy-names = "port0", "port1";
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status = "disabled";
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};
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sdio: mvsdio@90000 {
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compatible = "marvell,orion-sdio";
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reg = <0x90000 0x200>;
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interrupts = <28>;
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clocks = <&gate_clk 4>;
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pinctrl-0 = <&pmx_sdio>;
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pinctrl-names = "default";
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bus-width = <4>;
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cap-sdio-irq;
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cap-sd-highspeed;
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cap-mmc-highspeed;
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status = "disabled";
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};
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};
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};
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