mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-28 11:18:45 +07:00
3bba4e2fdc
Add devicetree support for Sophon Edge board from Bitmain based on BM1880 SoC. This board is one of the 96Boards Consumer and AI platform. More information about this board can be found in 96Boards product page: https://www.96boards.org/documentation/consumer/sophon-edge/ Only UART peripheral support is enabled for now. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Acked-by: Arnd Bergmann <arnd@arndb.de>
51 lines
769 B
Plaintext
51 lines
769 B
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
|
/*
|
|
* Copyright (c) 2019 Linaro Ltd.
|
|
* Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
|
|
*/
|
|
|
|
/dts-v1/;
|
|
|
|
#include "bm1880.dtsi"
|
|
|
|
/ {
|
|
compatible = "bitmain,sophon-edge", "bitmain,bm1880";
|
|
model = "Sophon Edge";
|
|
|
|
aliases {
|
|
serial0 = &uart0;
|
|
serial1 = &uart2;
|
|
serial2 = &uart1;
|
|
};
|
|
|
|
chosen {
|
|
stdout-path = "serial0:115200n8";
|
|
};
|
|
|
|
memory@0 {
|
|
device_type = "memory";
|
|
reg = <0x1 0x00000000 0x0 0x40000000>; // 1GB
|
|
};
|
|
|
|
uart_clk: uart-clk {
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <500000000>;
|
|
#clock-cells = <0>;
|
|
};
|
|
};
|
|
|
|
&uart0 {
|
|
status = "okay";
|
|
clocks = <&uart_clk>;
|
|
};
|
|
|
|
&uart1 {
|
|
status = "okay";
|
|
clocks = <&uart_clk>;
|
|
};
|
|
|
|
&uart2 {
|
|
status = "okay";
|
|
clocks = <&uart_clk>;
|
|
};
|