mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-23 03:23:47 +07:00
84badc5ec5
With l4 interconnect hierarchy and ti-sysc interconnect target module data in place, we can simply move all the related child devices to their proper location and enable probing using ti-sysc. In general the first child device address range starts at range 0 from the ti-sysc interconnect target so the move involves adjusting the child device reg properties for that. And we cannot yet move mmu_dsp until we have a proper reset controller driver for rstctrl registers. In case of any regressions, problem devices can be reverted to probe with legacy platform data as needed by moving them back and removing the related interconnect target module node. Signed-off-by: Tony Lindgren <tony@atomide.com>
633 lines
16 KiB
Plaintext
633 lines
16 KiB
Plaintext
/*
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* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <dt-bindings/bus/ti-sysc.h>
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#include <dt-bindings/clock/omap4.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/pinctrl/omap.h>
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#include <dt-bindings/clock/omap4.h>
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/ {
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compatible = "ti,omap4430", "ti,omap4";
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interrupt-parent = <&wakeupgen>;
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#address-cells = <1>;
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#size-cells = <1>;
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chosen { };
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aliases {
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i2c0 = &i2c1;
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i2c1 = &i2c2;
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i2c2 = &i2c3;
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i2c3 = &i2c4;
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serial0 = &uart1;
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serial1 = &uart2;
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serial2 = &uart3;
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serial3 = &uart4;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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compatible = "arm,cortex-a9";
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device_type = "cpu";
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next-level-cache = <&L2>;
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reg = <0x0>;
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clocks = <&dpll_mpu_ck>;
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clock-names = "cpu";
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clock-latency = <300000>; /* From omap-cpufreq driver */
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};
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cpu@1 {
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compatible = "arm,cortex-a9";
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device_type = "cpu";
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next-level-cache = <&L2>;
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reg = <0x1>;
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};
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};
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/*
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* Note that 4430 needs cross trigger interface (CTI) supported
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* before we can configure the interrupts. This means sampling
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* events are not supported for pmu. Note that 4460 does not use
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* CTI, see also 4460.dtsi.
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*/
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pmu {
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compatible = "arm,cortex-a9-pmu";
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ti,hwmods = "debugss";
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};
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gic: interrupt-controller@48241000 {
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compatible = "arm,cortex-a9-gic";
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interrupt-controller;
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#interrupt-cells = <3>;
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reg = <0x48241000 0x1000>,
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<0x48240100 0x0100>;
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interrupt-parent = <&gic>;
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};
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L2: l2-cache-controller@48242000 {
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compatible = "arm,pl310-cache";
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reg = <0x48242000 0x1000>;
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cache-unified;
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cache-level = <2>;
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};
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local-timer@48240600 {
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compatible = "arm,cortex-a9-twd-timer";
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clocks = <&mpu_periphclk>;
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reg = <0x48240600 0x20>;
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_EDGE_RISING)>;
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interrupt-parent = <&gic>;
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};
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wakeupgen: interrupt-controller@48281000 {
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compatible = "ti,omap4-wugen-mpu";
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interrupt-controller;
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#interrupt-cells = <3>;
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reg = <0x48281000 0x1000>;
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interrupt-parent = <&gic>;
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};
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/*
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* The soc node represents the soc top level view. It is used for IPs
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* that are not memory mapped in the MPU view or for the MPU itself.
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*/
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soc {
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compatible = "ti,omap-infra";
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mpu {
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compatible = "ti,omap4-mpu";
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ti,hwmods = "mpu";
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sram = <&ocmcram>;
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};
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dsp {
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compatible = "ti,omap3-c64";
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ti,hwmods = "dsp";
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};
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iva {
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compatible = "ti,ivahd";
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ti,hwmods = "iva";
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};
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};
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/*
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* XXX: Use a flat representation of the OMAP4 interconnect.
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* The real OMAP interconnect network is quite complex.
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* Since it will not bring real advantage to represent that in DT for
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* the moment, just use a fake OCP bus entry to represent the whole bus
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* hierarchy.
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*/
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ocp {
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compatible = "ti,omap4-l3-noc", "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
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reg = <0x44000000 0x1000>,
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<0x44800000 0x2000>,
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<0x45000000 0x1000>;
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interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
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l4_wkup: interconnect@4a300000 {
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};
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l4_cfg: interconnect@4a000000 {
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};
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l4_per: interconnect@48000000 {
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};
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ocmcram: ocmcram@40304000 {
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compatible = "mmio-sram";
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reg = <0x40304000 0xa000>; /* 40k */
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};
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gpmc: gpmc@50000000 {
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compatible = "ti,omap4430-gpmc";
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reg = <0x50000000 0x1000>;
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#address-cells = <2>;
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#size-cells = <1>;
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interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
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dmas = <&sdma 4>;
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dma-names = "rxtx";
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gpmc,num-cs = <8>;
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gpmc,num-waitpins = <4>;
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ti,hwmods = "gpmc";
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ti,no-idle-on-init;
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clocks = <&l3_div_ck>;
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clock-names = "fck";
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interrupt-controller;
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#interrupt-cells = <2>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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mmu_dsp: mmu@4a066000 {
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compatible = "ti,omap4-iommu";
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reg = <0x4a066000 0x100>;
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interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
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ti,hwmods = "mmu_dsp";
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#iommu-cells = <0>;
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};
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target-module@52000000 {
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compatible = "ti,sysc-omap4", "ti,sysc";
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ti,hwmods = "iss";
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reg = <0x52000000 0x4>,
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<0x52000010 0x4>;
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reg-names = "rev", "sysc";
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ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
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ti,sysc-midle = <SYSC_IDLE_FORCE>,
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<SYSC_IDLE_NO>,
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<SYSC_IDLE_SMART>,
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<SYSC_IDLE_SMART_WKUP>;
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ti,sysc-sidle = <SYSC_IDLE_FORCE>,
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<SYSC_IDLE_NO>,
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<SYSC_IDLE_SMART>,
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<SYSC_IDLE_SMART_WKUP>;
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ti,sysc-delay-us = <2>;
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clocks = <&iss_clkctrl OMAP4_ISS_CLKCTRL 0>;
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clock-names = "fck";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x52000000 0x1000000>;
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/* No child device binding, driver in staging */
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};
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mmu_ipu: mmu@55082000 {
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compatible = "ti,omap4-iommu";
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reg = <0x55082000 0x100>;
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interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
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ti,hwmods = "mmu_ipu";
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#iommu-cells = <0>;
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ti,iommu-bus-err-back;
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};
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target-module@40130000 {
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compatible = "ti,sysc-omap2", "ti,sysc";
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ti,hwmods = "wd_timer3";
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reg = <0x40130000 0x4>,
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<0x40130010 0x4>,
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<0x40130014 0x4>;
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reg-names = "rev", "sysc", "syss";
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ti,sysc-mask = <(SYSC_OMAP2_EMUFREE |
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SYSC_OMAP2_SOFTRESET)>;
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ti,sysc-sidle = <SYSC_IDLE_FORCE>,
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<SYSC_IDLE_NO>,
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<SYSC_IDLE_SMART>,
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<SYSC_IDLE_SMART_WKUP>;
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ti,syss-mask = <1>;
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/* Domains (V, P, C): abe, abe_pwrdm, abe_clkdm */
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clocks = <&abe_clkctrl OMAP4_WD_TIMER3_CLKCTRL 0>;
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clock-names = "fck";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x00000000 0x40130000 0x1000>, /* MPU private access */
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<0x49030000 0x49030000 0x0080>; /* L3 Interconnect */
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wdt3: wdt@0 {
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compatible = "ti,omap4-wdt", "ti,omap3-wdt";
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reg = <0x0 0x80>;
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interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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mcpdm: mcpdm@40132000 {
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compatible = "ti,omap4-mcpdm";
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reg = <0x40132000 0x7f>, /* MPU private access */
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<0x49032000 0x7f>; /* L3 Interconnect */
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reg-names = "mpu", "dma";
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interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
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ti,hwmods = "mcpdm";
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dmas = <&sdma 65>,
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<&sdma 66>;
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dma-names = "up_link", "dn_link";
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status = "disabled";
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};
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dmic: dmic@4012e000 {
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compatible = "ti,omap4-dmic";
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reg = <0x4012e000 0x7f>, /* MPU private access */
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<0x4902e000 0x7f>; /* L3 Interconnect */
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reg-names = "mpu", "dma";
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interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
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ti,hwmods = "dmic";
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dmas = <&sdma 67>;
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dma-names = "up_link";
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status = "disabled";
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};
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mcbsp1: mcbsp@40122000 {
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compatible = "ti,omap4-mcbsp";
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reg = <0x40122000 0xff>, /* MPU private access */
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<0x49022000 0xff>; /* L3 Interconnect */
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reg-names = "mpu", "dma";
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interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "common";
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ti,buffer-size = <128>;
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ti,hwmods = "mcbsp1";
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dmas = <&sdma 33>,
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<&sdma 34>;
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dma-names = "tx", "rx";
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status = "disabled";
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};
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mcbsp2: mcbsp@40124000 {
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compatible = "ti,omap4-mcbsp";
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reg = <0x40124000 0xff>, /* MPU private access */
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<0x49024000 0xff>; /* L3 Interconnect */
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reg-names = "mpu", "dma";
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interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "common";
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ti,buffer-size = <128>;
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ti,hwmods = "mcbsp2";
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dmas = <&sdma 17>,
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<&sdma 18>;
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dma-names = "tx", "rx";
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status = "disabled";
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};
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mcbsp3: mcbsp@40126000 {
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compatible = "ti,omap4-mcbsp";
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reg = <0x40126000 0xff>, /* MPU private access */
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<0x49026000 0xff>; /* L3 Interconnect */
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reg-names = "mpu", "dma";
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interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "common";
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ti,buffer-size = <128>;
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ti,hwmods = "mcbsp3";
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dmas = <&sdma 19>,
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<&sdma 20>;
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dma-names = "tx", "rx";
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status = "disabled";
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};
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target-module@40128000 {
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compatible = "ti,sysc-mcasp", "ti,sysc";
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ti,hwmods = "mcasp";
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reg = <0x40128000 0x4>,
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<0x40128004 0x4>;
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reg-names = "rev", "sysc";
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ti,sysc-sidle = <SYSC_IDLE_FORCE>,
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<SYSC_IDLE_NO>,
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<SYSC_IDLE_SMART>,
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<SYSC_IDLE_SMART_WKUP>;
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clocks = <&abe_clkctrl OMAP4_MCASP_CLKCTRL 0>;
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clock-names = "fck";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x00000000 0x40128000 0x1000>, /* MPU */
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<0x49028000 0x49028000 0x1000>; /* L3 */
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/*
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* Child device unsupported by davinci-mcasp. At least
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* RX path is disabled for omap4, and only DIT mode
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* works with no I2S. See also old Android kernel
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* omap-mcasp driver for more information.
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*/
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};
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target-module@4012c000 {
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compatible = "ti,sysc-omap4", "ti,sysc";
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ti,hwmods = "slimbus1";
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reg = <0x4012c000 0x4>,
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<0x4012c010 0x4>;
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reg-names = "rev", "sysc";
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ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
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ti,sysc-sidle = <SYSC_IDLE_FORCE>,
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<SYSC_IDLE_NO>,
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<SYSC_IDLE_SMART>,
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<SYSC_IDLE_SMART_WKUP>;
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clocks = <&abe_clkctrl OMAP4_SLIMBUS1_CLKCTRL 0>;
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clock-names = "fck";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x00000000 0x4012c000 0x1000>, /* MPU */
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<0x4902c000 0x4902c000 0x1000>; /* L3 */
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/* No child device binding or driver in mainline */
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};
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target-module@401f1000 {
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compatible = "ti,sysc-omap4", "ti,sysc";
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ti,hwmods = "aess";
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reg = <0x401f1000 0x4>,
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<0x401f1010 0x4>;
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reg-names = "rev", "sysc";
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ti,sysc-midle = <SYSC_IDLE_FORCE>,
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<SYSC_IDLE_NO>,
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<SYSC_IDLE_SMART>,
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<SYSC_IDLE_SMART_WKUP>;
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ti,sysc-sidle = <SYSC_IDLE_FORCE>,
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<SYSC_IDLE_NO>,
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<SYSC_IDLE_SMART>;
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clocks = <&abe_clkctrl OMAP4_AESS_CLKCTRL 0>;
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clock-names = "fck";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x00000000 0x401f1000 0x1000>, /* MPU */
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<0x490f1000 0x490f1000 0x1000>; /* L3 */
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/*
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* No child device binding or driver in mainline.
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* See Android tree and related upstreaming efforts
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* for the old driver.
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*/
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};
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dmm@4e000000 {
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compatible = "ti,omap4-dmm";
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reg = <0x4e000000 0x800>;
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interrupts = <0 113 0x4>;
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ti,hwmods = "dmm";
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};
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emif1: emif@4c000000 {
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compatible = "ti,emif-4d";
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reg = <0x4c000000 0x100>;
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interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
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ti,hwmods = "emif1";
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ti,no-idle-on-init;
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phy-type = <1>;
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hw-caps-read-idle-ctrl;
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hw-caps-ll-interface;
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hw-caps-temp-alert;
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};
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emif2: emif@4d000000 {
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compatible = "ti,emif-4d";
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reg = <0x4d000000 0x100>;
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interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
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ti,hwmods = "emif2";
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ti,no-idle-on-init;
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phy-type = <1>;
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hw-caps-read-idle-ctrl;
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hw-caps-ll-interface;
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hw-caps-temp-alert;
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};
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timer5: timer@40138000 {
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compatible = "ti,omap4430-timer";
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reg = <0x40138000 0x80>,
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<0x49038000 0x80>;
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interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
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ti,hwmods = "timer5";
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ti,timer-dsp;
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};
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timer6: timer@4013a000 {
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compatible = "ti,omap4430-timer";
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reg = <0x4013a000 0x80>,
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<0x4903a000 0x80>;
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interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
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ti,hwmods = "timer6";
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ti,timer-dsp;
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};
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timer7: timer@4013c000 {
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compatible = "ti,omap4430-timer";
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reg = <0x4013c000 0x80>,
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<0x4903c000 0x80>;
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interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
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ti,hwmods = "timer7";
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ti,timer-dsp;
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};
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timer8: timer@4013e000 {
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compatible = "ti,omap4430-timer";
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reg = <0x4013e000 0x80>,
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<0x4903e000 0x80>;
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interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
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ti,hwmods = "timer8";
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ti,timer-pwm;
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ti,timer-dsp;
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};
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aes1: aes@4b501000 {
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compatible = "ti,omap4-aes";
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ti,hwmods = "aes1";
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reg = <0x4b501000 0xa0>;
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interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
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dmas = <&sdma 111>, <&sdma 110>;
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dma-names = "tx", "rx";
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};
|
|
|
|
aes2: aes@4b701000 {
|
|
compatible = "ti,omap4-aes";
|
|
ti,hwmods = "aes2";
|
|
reg = <0x4b701000 0xa0>;
|
|
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&sdma 114>, <&sdma 113>;
|
|
dma-names = "tx", "rx";
|
|
};
|
|
|
|
des: des@480a5000 {
|
|
compatible = "ti,omap4-des";
|
|
ti,hwmods = "des";
|
|
reg = <0x480a5000 0xa0>;
|
|
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&sdma 117>, <&sdma 116>;
|
|
dma-names = "tx", "rx";
|
|
};
|
|
|
|
sham: sham@4b100000 {
|
|
compatible = "ti,omap4-sham";
|
|
ti,hwmods = "sham";
|
|
reg = <0x4b100000 0x300>;
|
|
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&sdma 119>;
|
|
dma-names = "rx";
|
|
};
|
|
|
|
abb_mpu: regulator-abb-mpu {
|
|
compatible = "ti,abb-v2";
|
|
regulator-name = "abb_mpu";
|
|
#address-cells = <0>;
|
|
#size-cells = <0>;
|
|
ti,tranxdone-status-mask = <0x80>;
|
|
clocks = <&sys_clkin_ck>;
|
|
ti,settling-time = <50>;
|
|
ti,clock-cycles = <16>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
abb_iva: regulator-abb-iva {
|
|
compatible = "ti,abb-v2";
|
|
regulator-name = "abb_iva";
|
|
#address-cells = <0>;
|
|
#size-cells = <0>;
|
|
ti,tranxdone-status-mask = <0x80000000>;
|
|
clocks = <&sys_clkin_ck>;
|
|
ti,settling-time = <50>;
|
|
ti,clock-cycles = <16>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
target-module@56000000 {
|
|
compatible = "ti,sysc-omap4", "ti,sysc";
|
|
ti,hwmods = "gpu";
|
|
reg = <0x5601fc00 0x4>,
|
|
<0x5601fc10 0x4>;
|
|
reg-names = "rev", "sysc";
|
|
ti,sysc-midle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>,
|
|
<SYSC_IDLE_SMART>,
|
|
<SYSC_IDLE_SMART_WKUP>;
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>,
|
|
<SYSC_IDLE_SMART>,
|
|
<SYSC_IDLE_SMART_WKUP>;
|
|
clocks = <&l3_gfx_clkctrl OMAP4_GPU_CLKCTRL 0>;
|
|
clock-names = "fck";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0 0x56000000 0x2000000>;
|
|
|
|
/*
|
|
* Closed source PowerVR driver, no child device
|
|
* binding or driver in mainline
|
|
*/
|
|
};
|
|
|
|
dss: dss@58000000 {
|
|
compatible = "ti,omap4-dss";
|
|
reg = <0x58000000 0x80>;
|
|
status = "disabled";
|
|
ti,hwmods = "dss_core";
|
|
clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>;
|
|
clock-names = "fck";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
|
|
dispc@58001000 {
|
|
compatible = "ti,omap4-dispc";
|
|
reg = <0x58001000 0x1000>;
|
|
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
|
|
ti,hwmods = "dss_dispc";
|
|
clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>;
|
|
clock-names = "fck";
|
|
};
|
|
|
|
rfbi: encoder@58002000 {
|
|
compatible = "ti,omap4-rfbi";
|
|
reg = <0x58002000 0x1000>;
|
|
status = "disabled";
|
|
ti,hwmods = "dss_rfbi";
|
|
clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>, <&l3_div_ck>;
|
|
clock-names = "fck", "ick";
|
|
};
|
|
|
|
venc: encoder@58003000 {
|
|
compatible = "ti,omap4-venc";
|
|
reg = <0x58003000 0x1000>;
|
|
status = "disabled";
|
|
ti,hwmods = "dss_venc";
|
|
clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 11>;
|
|
clock-names = "fck";
|
|
};
|
|
|
|
dsi1: encoder@58004000 {
|
|
compatible = "ti,omap4-dsi";
|
|
reg = <0x58004000 0x200>,
|
|
<0x58004200 0x40>,
|
|
<0x58004300 0x20>;
|
|
reg-names = "proto", "phy", "pll";
|
|
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
|
|
status = "disabled";
|
|
ti,hwmods = "dss_dsi1";
|
|
clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>,
|
|
<&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
|
|
clock-names = "fck", "sys_clk";
|
|
};
|
|
|
|
dsi2: encoder@58005000 {
|
|
compatible = "ti,omap4-dsi";
|
|
reg = <0x58005000 0x200>,
|
|
<0x58005200 0x40>,
|
|
<0x58005300 0x20>;
|
|
reg-names = "proto", "phy", "pll";
|
|
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
|
|
status = "disabled";
|
|
ti,hwmods = "dss_dsi2";
|
|
clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>,
|
|
<&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
|
|
clock-names = "fck", "sys_clk";
|
|
};
|
|
|
|
hdmi: encoder@58006000 {
|
|
compatible = "ti,omap4-hdmi";
|
|
reg = <0x58006000 0x200>,
|
|
<0x58006200 0x100>,
|
|
<0x58006300 0x100>,
|
|
<0x58006400 0x1000>;
|
|
reg-names = "wp", "pll", "phy", "core";
|
|
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
|
|
status = "disabled";
|
|
ti,hwmods = "dss_hdmi";
|
|
clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 9>,
|
|
<&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
|
|
clock-names = "fck", "sys_clk";
|
|
dmas = <&sdma 76>;
|
|
dma-names = "audio_tx";
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
#include "omap4-l4.dtsi"
|
|
#include "omap44xx-clocks.dtsi"
|