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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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156ad0d7ea
The condition passed to read*_poll_timeout() is the break condition,
i.e. wait for this condition to happen and return success.
The original code assumed the opposite, resulting in a warning when
the PLL clock rate was changed but never lost it's lock as far as
the readout indicated. This was verified by checking the read out
register value.
Fixes: 1d80c14248 ("clk: sunxi-ng: Add common infrastructure")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
91 lines
2.0 KiB
C
91 lines
2.0 KiB
C
/*
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* Copyright 2016 Maxime Ripard
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*
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* Maxime Ripard <maxime.ripard@free-electrons.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/clk-provider.h>
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#include <linux/iopoll.h>
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#include <linux/slab.h>
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#include "ccu_common.h"
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#include "ccu_reset.h"
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static DEFINE_SPINLOCK(ccu_lock);
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void ccu_helper_wait_for_lock(struct ccu_common *common, u32 lock)
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{
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u32 reg;
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if (!lock)
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return;
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WARN_ON(readl_relaxed_poll_timeout(common->base + common->reg, reg,
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reg & lock, 100, 70000));
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}
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int sunxi_ccu_probe(struct device_node *node, void __iomem *reg,
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const struct sunxi_ccu_desc *desc)
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{
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struct ccu_reset *reset;
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int i, ret;
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for (i = 0; i < desc->num_ccu_clks; i++) {
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struct ccu_common *cclk = desc->ccu_clks[i];
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if (!cclk)
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continue;
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cclk->base = reg;
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cclk->lock = &ccu_lock;
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}
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for (i = 0; i < desc->hw_clks->num ; i++) {
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struct clk_hw *hw = desc->hw_clks->hws[i];
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if (!hw)
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continue;
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ret = clk_hw_register(NULL, hw);
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if (ret) {
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pr_err("Couldn't register clock %s\n",
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clk_hw_get_name(hw));
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goto err_clk_unreg;
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}
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}
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ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get,
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desc->hw_clks);
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if (ret)
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goto err_clk_unreg;
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reset = kzalloc(sizeof(*reset), GFP_KERNEL);
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reset->rcdev.of_node = node;
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reset->rcdev.ops = &ccu_reset_ops;
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reset->rcdev.owner = THIS_MODULE;
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reset->rcdev.nr_resets = desc->num_resets;
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reset->base = reg;
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reset->lock = &ccu_lock;
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reset->reset_map = desc->resets;
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ret = reset_controller_register(&reset->rcdev);
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if (ret)
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goto err_of_clk_unreg;
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return 0;
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err_of_clk_unreg:
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err_clk_unreg:
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return ret;
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}
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