Maxime Ripard e66f81bbd7 clk: sunxi-ng: Implement factors offsets ... The factors we've seen so far all had an offset of one. However, on the earlier Allwinner SoCs, some factors could have no offset at all, meaning that the value computed to reach the rate we want to use was the one we had to program in the registers. Implement an additional field for the factors that can have such an offset (linears, not based on a power of two) to specify that offset. This offset is not linked to the extremums that can be specified in those structures too. The minimum and maximum are representing the range of values we can use to try to compute the best rate. The offset comes later on when we want to set the best value in the registers. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>		2017-01-23 11:44:27 +01:00
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ccu_common.c	clk: sunxi-ng: Fix inverted test condition in ccu_helper_wait_for_lock	2016-08-08 19:27:33 +02:00
ccu_common.h	clk: sunxi-ng: Add common infrastructure	2016-07-08 18:04:32 -07:00
ccu_div.c	clk: sunxi-ng: Add divider	2016-07-08 18:04:48 -07:00
ccu_div.h	clk: sunxi-ng: Implement factors offsets	2017-01-23 11:44:27 +01:00
ccu_frac.c	clk: sunxi-ng: Rename the internal structures	2016-10-20 19:24:20 +02:00
ccu_frac.h	clk: sunxi-ng: Rename the internal structures	2016-10-20 19:24:20 +02:00
ccu_gate.c	clk: sunxi-ng: Add gate clock support	2016-07-08 18:04:38 -07:00
ccu_gate.h	clk: sunxi-ng: Add gate clock support	2016-07-08 18:04:38 -07:00
ccu_mp.c	clk: sunxi-ng: Implement factors offsets	2017-01-23 11:44:27 +01:00
ccu_mp.h	clk: sunxi-ng: Rename the internal structures	2016-10-20 19:24:20 +02:00
ccu_mult.c	clk: sunxi-ng: Implement factors offsets	2017-01-23 11:44:27 +01:00
ccu_mult.h	clk: sunxi-ng: Implement factors offsets	2017-01-23 11:44:27 +01:00
ccu_mux.c	clk: sunxi-ng: mux: Add clk notifier functions	2016-08-25 22:30:36 +02:00
ccu_mux.h	clk: sunxi-ng: mux: Add mux table macro	2016-09-10 11:41:18 +02:00
ccu_nk.c	clk: sunxi-ng: Implement factors offsets	2017-01-23 11:44:27 +01:00
ccu_nk.h	clk: sunxi-ng: Rename the internal structures	2016-10-20 19:24:20 +02:00
ccu_nkm.c	clk: sunxi-ng: Implement factors offsets	2017-01-23 11:44:27 +01:00
ccu_nkm.h	clk: sunxi-ng: Rename the internal structures	2016-10-20 19:24:20 +02:00
ccu_nkmp.c	clk: sunxi-ng: Implement factors offsets	2017-01-23 11:44:27 +01:00
ccu_nkmp.h	clk: sunxi-ng: Rename the internal structures	2016-10-20 19:24:20 +02:00
ccu_nm.c	clk: sunxi-ng: Implement factors offsets	2017-01-23 11:44:27 +01:00
ccu_nm.h	clk: sunxi-ng: Rename the internal structures	2016-10-20 19:24:20 +02:00
ccu_phase.c	clk: sunxi-ng: Add phase clock support	2016-07-08 18:04:45 -07:00
ccu_phase.h	clk: sunxi-ng: Add phase clock support	2016-07-08 18:04:45 -07:00
ccu_reset.c	clk: sunxi-ng: Add common infrastructure	2016-07-08 18:04:32 -07:00
ccu_reset.h	clk: sunxi-ng: Add common infrastructure	2016-07-08 18:04:32 -07:00
ccu-sun6i-a31.c	clk: sunxi-ng: A31: Fix spdif clock register	2017-01-02 22:24:55 +01:00
ccu-sun6i-a31.h	clk: sunxi-ng: Add A31/A31s clocks	2016-08-25 22:31:43 +02:00
ccu-sun8i-a23-a33.h	clk: sunxi-ng: Add A33 CCU support	2016-09-10 11:41:19 +02:00
ccu-sun8i-a23.c	clk: sunxi-ng: sun8i-a23: Set CLK_SET_RATE_PARENT for audio module clocks	2016-11-11 21:47:36 +01:00
ccu-sun8i-a33.c	clk: sunxi-ng: a33: Add CLK_SET_RATE_PARENT to ac-dig	2017-01-17 17:42:46 +01:00
ccu-sun8i-h3.c	clk: sunxi-ng: fix PLL_CPUX adjusting on H3	2017-01-02 22:24:55 +01:00
ccu-sun8i-h3.h	clk: sunxi-ng: Add H3 clocks	2016-07-08 18:05:12 -07:00
ccu-sun8i-v3s.c	clk: sunxi-ng: add support for V3s CCU	2017-01-20 21:39:03 +01:00
ccu-sun8i-v3s.h	clk: sunxi-ng: add support for V3s CCU	2017-01-20 21:39:03 +01:00
ccu-sun50i-a64.c	clk: sunxi-ng: Mark structs static and cleanup spaces	2016-11-16 11:27:28 -08:00
ccu-sun50i-a64.h	clk: sunxi-ng: Add A64 clocks	2016-11-03 09:06:18 +01:00
Kconfig	clk: sunxi-ng: add support for V3s CCU	2017-01-20 21:39:03 +01:00
Makefile	clk: sunxi-ng: add support for V3s CCU	2017-01-20 21:39:03 +01:00