James Hogan aff565aab9 MIPS: Clean up RDHWR handling ... No preprocessor definitions are used in the handling of the registers accessible with the RDHWR instruction, nor the corresponding bits in the CP0 HWREna register. Add definitions for both the register numbers (MIPS_HWR_*) and HWREna bits (MIPS_HWRENA_*) in asm/mipsregs.h and make use of them in the initialisation of HWREna and emulation of the RDHWR instruction. Signed-off-by: James Hogan <james.hogan@imgtec.com> Acked-by: Ralf Baechle <ralf@linux-mips.org> Cc: David Daney <david.daney@cavium.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Radim Krčmář <rkrcmar@redhat.com> Cc: linux-mips@linux-mips.org Cc: kvm@vger.kernel.org Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>		2016-06-15 23:58:25 +02:00
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cpu-feature-overrides.h	MIPS: Clean up RDHWR handling	2016-06-15 23:58:25 +02:00
dma-coherence.h	MIPS: DMA: Implement platform hook to perform post-DMA cache flushes.	2015-04-01 17:22:01 +02:00
irq.h	MIPS: Octeon: Add twsi interrupt initialization for OCTEON 3XXX, 5XXX, 63XX	2014-06-04 22:50:42 +02:00
kernel-entry-init.h	MIPS: Fix misspellings in comments.	2016-04-03 12:32:09 +02:00
mangle-port.h	MIPS: OCTEON: Add mach-cavium-octeon/mangle-port.h	2015-04-01 17:21:24 +02:00
spaces.h	MIPS/OCTEON: Override default address space layout.	2013-06-21 18:07:02 +02:00
war.h	MIPS: OCTEON: Implement DCache errata workaround for all CN6XXX	2015-02-20 15:31:27 +01:00