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DIV6 clocks are divider gate clocks controlled through a single register. The divider is expressed on 6 bits, hence the name, and can take values from 1/1 to 1/64. Those clocks are found on Renesas ARM SoCs. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
29 lines
897 B
Plaintext
29 lines
897 B
Plaintext
* Renesas CPG DIV6 Clock
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The CPG DIV6 clocks are variable factor clocks provided by the Clock Pulse
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Generator (CPG). They clock input is divided by a configurable factor from 1
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to 64.
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Required Properties:
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- compatible: Must be one of the following
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- "renesas,r8a7790-div6-clock" for R8A7790 (R-Car H2) DIV6 clocks
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- "renesas,r8a7791-div6-clock" for R8A7791 (R-Car M2) DIV6 clocks
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- "renesas,cpg-div6-clock" for generic DIV6 clocks
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- reg: Base address and length of the memory resource used by the DIV6 clock
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- clocks: Reference to the parent clock
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- #clock-cells: Must be 0
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- clock-output-names: The name of the clock as a free-form string
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Example
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-------
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sd2_clk: sd2_clk@e6150078 {
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compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
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reg = <0 0xe6150078 0 4>;
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clocks = <&pll1_div2_clk>;
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#clock-cells = <0>;
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clock-output-names = "sd2";
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};
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