Emilio López d838ff33ec clk: sunxi: add gating support to PLL1 ... This commit adds gating support to PLL1 on the clock driver. This makes the PLL1 implementation fully compatible with PLL4 as well. Signed-off-by: Emilio López <emilio@elopez.com.ar> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Mike Turquette <mturquette@linaro.org>		2013-12-28 17:08:06 -03:00
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bindings	clk: sunxi: add gating support to PLL1	2013-12-28 17:08:06 -03:00
00-INDEX	Documentation: add devicetree docs index file	2011-03-16 10:47:03 -07:00
booting-without-of.txt	sun.com documentation fixes	2013-02-21 17:22:20 -08:00
usage-model.txt	doc: device tree: clarify stuff in usage-model.txt.	2013-06-18 13:46:27 +02:00