Will Deacon d5efd9cc9c arm64: pmu: add support for interrupt-affinity property ... Historically, the PMU devicetree bindings have expected SPIs to be listed in order of *logical* CPU number. This is problematic for bootloaders, especially when the boot CPU (logical ID 0) isn't listed first in the devicetree. This patch adds a new optional property, interrupt-affinity, to the PMU node which allows the interrupt affinity to be described using a list of phandled to CPU nodes, with each entry in the list corresponding to the SPI at the same index in the interrupts property. Cc: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>		2015-03-24 15:09:47 +00:00
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boot	dtb: change binding name to match with newer firmware DT	2015-03-04 15:54:14 -05:00
configs	ARM: SoC 64-bit changes and additions	2015-02-17 09:47:46 -08:00
crypto	arm64/crypto: issue aese/aesmc instructions in pairs	2015-03-19 10:43:57 +00:00
include	arm64: pmu: add support for interrupt-affinity property	2015-03-24 15:09:47 +00:00
kernel	arm64: pmu: add support for interrupt-affinity property	2015-03-24 15:09:47 +00:00
kvm	arm64: KVM: use ID map with increased VA range if required	2015-03-23 11:35:29 +00:00
lib	arm64: __clear_user: handle exceptions on strb	2014-11-13 15:21:26 +00:00
mm	arm64: mm: increase VA range of identity map	2015-03-23 11:35:29 +00:00
net	arm64: bpf: lift restriction on last instruction	2014-12-03 18:04:09 +00:00
xen
Kconfig	arm64: kconfig: increase NR_CPUS range to 2-4096.	2015-03-19 19:46:00 +00:00
Kconfig.debug	arm64: add better page protections to arm64	2015-01-22 14:54:29 +00:00
Makefile	arm64: Adjust EFI libstub object include logic	2015-03-17 16:59:47 +00:00