Will Deacon d5efd9cc9c arm64: pmu: add support for interrupt-affinity property ... Historically, the PMU devicetree bindings have expected SPIs to be listed in order of *logical* CPU number. This is problematic for bootloaders, especially when the boot CPU (logical ID 0) isn't listed first in the devicetree. This patch adds a new optional property, interrupt-affinity, to the PMU node which allows the interrupt affinity to be described using a list of phandled to CPU nodes, with each entry in the list corresponding to the SPI at the same index in the interrupts property. Cc: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>		2015-03-24 15:09:47 +00:00
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asm	arm64: pmu: add support for interrupt-affinity property	2015-03-24 15:09:47 +00:00
uapi/asm	Fairly small update, but there are some interesting new features.	2015-02-13 09:55:09 -08:00