hersen wu 65d38262b3 drm/amd/display: fbc state could not reach while enable fbc ... [WHY] fbc is within the data path from memory to dce. while re-configure mc dmif, fbc should be enabled. otherwise, fbc may not be enabled properly. [HOW] before re-configure mc dmif, disable fbc, only after dmif re-configuration fully done, enable fbc again. Signed-off-by: hersen wu <hersenxs.wu@amd.com> Reviewed-by: Roman Li <Roman.Li@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2018-11-30 12:02:35 -05:00
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hw	drm/amd/display: Load DMCU IRAM	2018-11-26 15:47:53 -05:00
bw_fixed.h	drm/amd/display: explicit uint64_t casting	2018-11-05 14:20:50 -05:00
clock_source.h	drm/amd/display: remove unused clk_src code	2018-09-10 22:42:55 -05:00
compressor.h	drm/amd/display: fbc state could not reach while enable fbc	2018-11-30 12:02:35 -05:00
core_status.h	drm/amd/display: Add timing validation against dongle cap	2017-11-28 17:54:16 -05:00
core_types.h	drm/amd/display: Start documentation of DC	2018-11-30 12:01:56 -05:00
custom_float.h	drm/amd/display: Enable regamma 25 segments and use double buffer.	2017-09-26 17:14:18 -04:00
dc_link_ddc.h	drm/amd/display: Return aux replies directly to DRM	2018-07-13 14:48:36 -05:00
dc_link_dp.h	drm/amd/display: Retry link training again	2018-07-27 09:07:42 -05:00
dce_calcs.h	drm/amdgpu/display: remove VEGAM config option	2018-05-18 16:08:18 -05:00
dcn_calcs.h	drm/amd/display: rename dccg to clk_mgr	2018-11-05 14:20:48 -05:00
hw_sequencer.h	drm/amd/display: make underflow status clear explicit	2018-11-19 15:27:36 -05:00
link_hwss.h	drm/amd/display: add eDP 1.2+ polling for T7	2018-02-19 14:19:34 -05:00
reg_helper.h	drm/amd/display: generic indirect register access	2018-07-13 14:47:33 -05:00
resource.h	drm/amd/display: move pplib/smu notification to dccg block	2018-11-05 14:20:40 -05:00