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drm/amd/display: add eDP 1.2+ polling for T7

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Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Charlene Liu 2018-01-18 19:09:06 -05:00 committed by Alex Deucher
parent 60eb6d98ec
commit 5180d4a476
4 changed files with 33 additions and 5 deletions
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22
drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
View File

@ -123,6 +123,28 @@ bool edp_receiver_ready_T9(struct dc_link *link)
} while (++tries < 50);
return result;
}
bool edp_receiver_ready_T7(struct dc_link *link)
{
unsigned int tries = 0;
unsigned char sinkstatus = 0;
unsigned char edpRev = 0;
enum dc_status result = DC_OK;
result = core_link_read_dpcd(link, DP_EDP_DPCD_REV, &edpRev, sizeof(edpRev));
if (result == DC_OK && edpRev < DP_EDP_12)
return true;
/* start from eDP version 1.2, SINK_STAUS indicate the sink is ready.*/
do {
sinkstatus = 0;
result = core_link_read_dpcd(link, DP_SINK_STATUS, &sinkstatus, sizeof(sinkstatus));
if (sinkstatus == 1)
break;
if (result != DC_OK)
break;
udelay(25); //MAx T7 is 50ms
} while (++tries < 300);
return result;
}
void dp_disable_link_phy(struct dc_link *link, enum signal_type signal)
{

6
drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
View File

@ -920,6 +920,7 @@ static void dce110_stream_encoder_dp_blank(
{
struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
uint32_t retries = 0;
uint32_t reg1 = 0;
uint32_t max_retries = DP_BLANK_MAX_RETRY * 10;
/* Note: For CZ, we are changing driver default to disable
@ -928,7 +929,10 @@ static void dce110_stream_encoder_dp_blank(
* handful of panels that cannot handle disable stream at
* HBLANK and will result in a white line flash across the
* screen on stream disable. */
REG_GET(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, &reg1);
if ((reg1 & 0x1) == 0)
/*stream not enabled*/
return;
/* Specify the video stream disable point
* (2 = start of the next vertical blank) */
REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_DIS_DEFER, 2);

9
drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
View File

@ -927,9 +927,13 @@ void hwss_edp_backlight_control(
* Enable it in the future if necessary.
*/
/* dc_service_sleep_in_milliseconds(50); */
/*edp 1.2*/
if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_ON)
edp_receiver_ready_T7(link);
link_transmitter_control(ctx->dc_bios, &cntl);
/*edp 1.2*/
edp_receiver_ready_T9(link);
if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_OFF)
edp_receiver_ready_T9(link);
}
void dce110_disable_stream(struct pipe_ctx *pipe_ctx, int option)
@ -976,9 +980,6 @@ void dce110_disable_stream(struct pipe_ctx *pipe_ctx, int option)
*/
}
/* blank at encoder level */
if (dc_is_dp_signal(pipe_ctx->stream->signal))
pipe_ctx->stream_res.stream_enc->funcs->dp_blank(pipe_ctx->stream_res.stream_enc);
link->link_enc->funcs->connect_dig_be_to_fe(
link->link_enc,

1
drivers/gpu/drm/amd/display/dc/inc/link_hwss.h
View File

@ -52,6 +52,7 @@ void dp_enable_link_phy(
void dp_receiver_power_ctrl(struct dc_link *link, bool on);
bool edp_receiver_ready_T9(struct dc_link *link);
bool edp_receiver_ready_T7(struct dc_link *link);
void dp_disable_link_phy(struct dc_link *link, enum signal_type signal);