Vineet Gupta d1f317d825 ARCv2: MMUv4: cache programming model changes ... Caveats about cache flush on ARCv2 based cores - dcache is PIPT so paddr is sufficient for cache maintenance ops (no need to setup PTAG reg - icache is still VIPT but only aliasing configs need PTAG setup So basically this is departure from MMU-v3 which always need vaddr in line ops registers (DC_IVDL, DC_FLDL, IC_IVIL) but paddr in DC_PTAG, IC_PTAG respectively. Signed-off-by: Vineet Gupta <vgupta@synopsys.com>		2015-06-22 14:06:55 +05:30
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boot	ARC: [axs101] STAR 9000799830: Fix SD cards support	2015-06-19 18:09:31 +05:30
configs	ARC: [axs101] Add support for AXS101 SDP (software development platform)	2015-06-19 18:09:30 +05:30
include	ARCv2: MMUv4: cache programming model changes	2015-06-22 14:06:55 +05:30
kernel	ARCv2: STAR 9000808988: signals involving Delay Slot	2015-06-22 14:06:55 +05:30
lib	ARC: switch to generic ENTRY/END assembler annotations	2014-03-26 14:31:28 +05:30
mm	ARCv2: MMUv4: cache programming model changes	2015-06-22 14:06:55 +05:30
oprofile	ARC: OProfile support	2013-02-15 23:16:00 +05:30
plat-axs10x	ARC: [axs101] Add missing __init annotations	2015-06-19 18:09:32 +05:30
plat-sim	ARC: [plat_arcfpga]->[plat_sim]	2015-06-19 18:09:26 +05:30
plat-tb10x	ARC: [plat*] move code out of .init_machine into common	2014-10-13 14:46:13 +05:30
Kbuild
Kconfig	ARCv2: MMUv4: cache programming model changes	2015-06-22 14:06:55 +05:30
Kconfig.debug	ARC: With earlycon in use, retire EARLY_PRINTK	2015-05-11 11:20:21 +05:30
Makefile	ARCv2: Support for ARCv2 ISA and HS38x cores	2015-06-22 14:06:55 +05:30