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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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4b31bad51f
Add an appropriate "#power-domain-cells" property to the cpg_clocks device node, to create the CPG/MSTP Clock Domain. Add "power-domains" properties to all device nodes for devices that are part of the CPG/MSTP Clock Domain and can be power-managed through an MSTP clock. This applies to most on-SoC devices, which have a one-to-one mapping from SoC device to DT device node. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
375 lines
11 KiB
Plaintext
375 lines
11 KiB
Plaintext
/*
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* Device Tree Source for the r8a7793 SoC
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*
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* Copyright (C) 2014-2015 Renesas Electronics Corporation
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*/
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#include <dt-bindings/clock/r8a7793-clock.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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/ {
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compatible = "renesas,r8a7793";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0>;
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clock-frequency = <1500000000>;
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voltage-tolerance = <1>; /* 1% */
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clocks = <&cpg_clocks R8A7793_CLK_Z>;
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clock-latency = <300000>; /* 300 us */
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/* kHz - uV - OPPs unknown yet */
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operating-points = <1500000 1000000>,
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<1312500 1000000>,
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<1125000 1000000>,
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< 937500 1000000>,
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< 750000 1000000>,
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< 375000 1000000>;
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};
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};
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gic: interrupt-controller@f1001000 {
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compatible = "arm,gic-400";
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#interrupt-cells = <3>;
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#address-cells = <0>;
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interrupt-controller;
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reg = <0 0xf1001000 0 0x1000>,
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<0 0xf1002000 0 0x1000>,
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<0 0xf1004000 0 0x2000>,
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<0 0xf1006000 0 0x2000>;
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interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
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};
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timer {
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compatible = "arm,armv7-timer";
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interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
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<1 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
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<1 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
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<1 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
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};
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cmt0: timer@ffca0000 {
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compatible = "renesas,cmt-48-r8a7793", "renesas,cmt-48-gen2";
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reg = <0 0xffca0000 0 0x1004>;
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interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>,
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<0 143 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp1_clks R8A7793_CLK_CMT0>;
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clock-names = "fck";
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power-domains = <&cpg_clocks>;
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renesas,channels-mask = <0x60>;
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status = "disabled";
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};
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cmt1: timer@e6130000 {
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compatible = "renesas,cmt-48-r8a7793", "renesas,cmt-48-gen2";
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reg = <0 0xe6130000 0 0x1004>;
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interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>,
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<0 121 IRQ_TYPE_LEVEL_HIGH>,
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<0 122 IRQ_TYPE_LEVEL_HIGH>,
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<0 123 IRQ_TYPE_LEVEL_HIGH>,
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<0 124 IRQ_TYPE_LEVEL_HIGH>,
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<0 125 IRQ_TYPE_LEVEL_HIGH>,
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<0 126 IRQ_TYPE_LEVEL_HIGH>,
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<0 127 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp3_clks R8A7793_CLK_CMT1>;
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clock-names = "fck";
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power-domains = <&cpg_clocks>;
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renesas,channels-mask = <0xff>;
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status = "disabled";
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};
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irqc0: interrupt-controller@e61c0000 {
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compatible = "renesas,irqc-r8a7793", "renesas,irqc";
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#interrupt-cells = <2>;
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interrupt-controller;
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reg = <0 0xe61c0000 0 0x200>;
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interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
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<0 1 IRQ_TYPE_LEVEL_HIGH>,
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<0 2 IRQ_TYPE_LEVEL_HIGH>,
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<0 3 IRQ_TYPE_LEVEL_HIGH>,
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<0 12 IRQ_TYPE_LEVEL_HIGH>,
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<0 13 IRQ_TYPE_LEVEL_HIGH>,
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<0 14 IRQ_TYPE_LEVEL_HIGH>,
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<0 15 IRQ_TYPE_LEVEL_HIGH>,
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<0 16 IRQ_TYPE_LEVEL_HIGH>,
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<0 17 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp4_clks R8A7793_CLK_IRQC>;
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power-domains = <&cpg_clocks>;
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};
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scif0: serial@e6e60000 {
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compatible = "renesas,scif-r8a7793", "renesas,scif";
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reg = <0 0xe6e60000 0 64>;
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interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp7_clks R8A7793_CLK_SCIF0>;
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clock-names = "sci_ick";
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power-domains = <&cpg_clocks>;
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status = "disabled";
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};
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scif1: serial@e6e68000 {
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compatible = "renesas,scif-r8a7793", "renesas,scif";
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reg = <0 0xe6e68000 0 64>;
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interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp7_clks R8A7793_CLK_SCIF1>;
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clock-names = "sci_ick";
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power-domains = <&cpg_clocks>;
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status = "disabled";
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};
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ether: ethernet@ee700000 {
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compatible = "renesas,ether-r8a7793";
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reg = <0 0xee700000 0 0x400>;
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interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp8_clks R8A7793_CLK_ETHER>;
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power-domains = <&cpg_clocks>;
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phy-mode = "rmii";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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clocks {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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/* External root clock */
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extal_clk: extal_clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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/* This value must be overridden by the board. */
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clock-frequency = <0>;
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clock-output-names = "extal";
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};
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/* Special CPG clocks */
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cpg_clocks: cpg_clocks@e6150000 {
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compatible = "renesas,r8a7793-cpg-clocks",
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"renesas,rcar-gen2-cpg-clocks";
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reg = <0 0xe6150000 0 0x1000>;
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clocks = <&extal_clk>;
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#clock-cells = <1>;
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clock-output-names = "main", "pll0", "pll1", "pll3",
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"lb", "qspi", "sdh", "sd0", "z",
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"rcan", "adsp";
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#power-domain-cells = <0>;
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};
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/* Variable factor clocks */
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sd2_clk: sd2_clk@e6150078 {
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compatible = "renesas,r8a7793-div6-clock",
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"renesas,cpg-div6-clock";
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reg = <0 0xe6150078 0 4>;
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clocks = <&pll1_div2_clk>;
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#clock-cells = <0>;
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clock-output-names = "sd2";
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};
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sd3_clk: sd3_clk@e615026c {
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compatible = "renesas,r8a7793-div6-clock",
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"renesas,cpg-div6-clock";
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reg = <0 0xe615026c 0 4>;
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clocks = <&pll1_div2_clk>;
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#clock-cells = <0>;
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clock-output-names = "sd3";
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};
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mmc0_clk: mmc0_clk@e6150240 {
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compatible = "renesas,r8a7793-div6-clock",
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"renesas,cpg-div6-clock";
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reg = <0 0xe6150240 0 4>;
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clocks = <&pll1_div2_clk>;
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#clock-cells = <0>;
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clock-output-names = "mmc0";
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};
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/* Fixed factor clocks */
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pll1_div2_clk: pll1_div2_clk {
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compatible = "fixed-factor-clock";
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clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
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#clock-cells = <0>;
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clock-div = <2>;
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clock-mult = <1>;
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clock-output-names = "pll1_div2";
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};
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zg_clk: zg_clk {
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compatible = "fixed-factor-clock";
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clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
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#clock-cells = <0>;
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clock-div = <5>;
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clock-mult = <1>;
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clock-output-names = "zg";
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};
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zx_clk: zx_clk {
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compatible = "fixed-factor-clock";
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clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
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#clock-cells = <0>;
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clock-div = <3>;
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clock-mult = <1>;
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clock-output-names = "zx";
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};
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zs_clk: zs_clk {
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compatible = "fixed-factor-clock";
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clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
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#clock-cells = <0>;
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clock-div = <6>;
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clock-mult = <1>;
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clock-output-names = "zs";
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};
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hp_clk: hp_clk {
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compatible = "fixed-factor-clock";
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clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
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#clock-cells = <0>;
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clock-div = <12>;
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clock-mult = <1>;
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clock-output-names = "hp";
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};
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p_clk: p_clk {
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compatible = "fixed-factor-clock";
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clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
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#clock-cells = <0>;
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clock-div = <24>;
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clock-mult = <1>;
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clock-output-names = "p";
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};
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rclk_clk: rclk_clk {
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compatible = "fixed-factor-clock";
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clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
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#clock-cells = <0>;
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clock-div = <(48 * 1024)>;
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clock-mult = <1>;
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clock-output-names = "rclk";
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};
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mp_clk: mp_clk {
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compatible = "fixed-factor-clock";
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clocks = <&pll1_div2_clk>;
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#clock-cells = <0>;
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clock-div = <15>;
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clock-mult = <1>;
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clock-output-names = "mp";
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};
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cp_clk: cp_clk {
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compatible = "fixed-factor-clock";
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clocks = <&extal_clk>;
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#clock-cells = <0>;
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clock-div = <2>;
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clock-mult = <1>;
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clock-output-names = "cp";
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};
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/* Gate clocks */
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mstp1_clks: mstp1_clks@e6150134 {
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compatible = "renesas,r8a7793-mstp-clocks",
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"renesas,cpg-mstp-clocks";
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reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
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clocks = <&zs_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>,
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<&zg_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>,
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<&p_clk>, <&p_clk>, <&rclk_clk>, <&cp_clk>,
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<&zs_clk>, <&zs_clk>, <&zs_clk>;
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#clock-cells = <1>;
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clock-indices = <
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R8A7793_CLK_VCP0 R8A7793_CLK_VPC0
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R8A7793_CLK_SSP1 R8A7793_CLK_TMU1
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R8A7793_CLK_3DG R8A7793_CLK_2DDMAC
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R8A7793_CLK_FDP1_1 R8A7793_CLK_FDP1_0
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R8A7793_CLK_TMU3 R8A7793_CLK_TMU2
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R8A7793_CLK_CMT0 R8A7793_CLK_TMU0
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R8A7793_CLK_VSP1_DU1 R8A7793_CLK_VSP1_DU0
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R8A7793_CLK_VSP1_S
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>;
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clock-output-names =
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"vcp0", "vpc0", "ssp_dev", "tmu1",
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"pvrsrvkm", "tddmac", "fdp1", "fdp0",
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"tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1",
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"vsp1-du0", "vsps";
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};
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mstp3_clks: mstp3_clks@e615013c {
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compatible = "renesas,r8a7793-mstp-clocks",
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"renesas,cpg-mstp-clocks";
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reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
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clocks = <&cp_clk>, <&sd3_clk>, <&sd2_clk>,
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<&cpg_clocks R8A7793_CLK_SD0>, <&mmc0_clk>,
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<&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>,
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<&rclk_clk>, <&hp_clk>, <&hp_clk>;
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#clock-cells = <1>;
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clock-indices = <
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R8A7793_CLK_TPU0 R8A7793_CLK_SDHI2
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R8A7793_CLK_SDHI1 R8A7793_CLK_SDHI0
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R8A7793_CLK_MMCIF0 R8A7793_CLK_IIC0
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R8A7793_CLK_PCIEC R8A7793_CLK_IIC1
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R8A7793_CLK_SSUSB R8A7793_CLK_CMT1
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R8A7793_CLK_USBDMAC0 R8A7793_CLK_USBDMAC1
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>;
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clock-output-names =
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"tpu0", "sdhi2", "sdhi1", "sdhi0", "mmcif0",
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"i2c7", "pciec", "i2c8", "ssusb", "cmt1",
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"usbdmac0", "usbdmac1";
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};
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mstp4_clks: mstp4_clks@e6150140 {
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compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks";
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reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
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clocks = <&cp_clk>;
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#clock-cells = <1>;
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clock-indices = <R8A7793_CLK_IRQC>;
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clock-output-names = "irqc";
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};
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mstp7_clks: mstp7_clks@e615014c {
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compatible = "renesas,r8a7793-mstp-clocks",
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"renesas,cpg-mstp-clocks";
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reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
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clocks = <&mp_clk>, <&hp_clk>, <&zs_clk>, <&p_clk>,
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<&p_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>,
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<&p_clk>, <&p_clk>, <&p_clk>, <&zx_clk>,
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<&zx_clk>, <&zx_clk>;
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#clock-cells = <1>;
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clock-indices = <
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R8A7793_CLK_EHCI R8A7793_CLK_HSUSB
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R8A7793_CLK_HSCIF2 R8A7793_CLK_SCIF5
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R8A7793_CLK_SCIF4 R8A7793_CLK_HSCIF1
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R8A7793_CLK_HSCIF0 R8A7793_CLK_SCIF3
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R8A7793_CLK_SCIF2 R8A7793_CLK_SCIF1
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R8A7793_CLK_SCIF0 R8A7793_CLK_DU1
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R8A7793_CLK_DU0 R8A7793_CLK_LVDS0
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>;
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clock-output-names =
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"ehci", "hsusb", "hscif2", "scif5", "scif4",
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"hscif1", "hscif0", "scif3", "scif2",
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"scif1", "scif0", "du1", "du0", "lvds0";
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};
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mstp8_clks: mstp8_clks@e6150990 {
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compatible = "renesas,r8a7793-mstp-clocks",
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"renesas,cpg-mstp-clocks";
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reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
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clocks = <&zx_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>,
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<&p_clk>, <&zs_clk>, <&zs_clk>;
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#clock-cells = <1>;
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clock-indices = <
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R8A7793_CLK_IPMMU_SGX R8A7793_CLK_VIN2
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R8A7793_CLK_VIN1 R8A7793_CLK_VIN0
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R8A7793_CLK_ETHER R8A7793_CLK_SATA1
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R8A7793_CLK_SATA0
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>;
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clock-output-names =
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"ipmmu_sgx", "vin2", "vin1", "vin0", "ether",
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"sata1", "sata0";
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};
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};
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};
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