AuxXxilium/linux_dsm_epyc7002
1
0
Fork 0
mirror of https://github.com/AuxXxilium/linux_dsm_epyc7002.git synced 2025-01-24 00:29:27 +07:00
Code Issues Actions Packages Projects Releases Wiki Activity

ARM: shmobile: r8a7793 dtsi: Add CPG/MSTP Clock Domain

Browse Source 
Add an appropriate "#power-domain-cells" property to the cpg_clocks
device node, to create the CPG/MSTP Clock Domain.

Add "power-domains" properties to all device nodes for devices that are
part of the CPG/MSTP Clock Domain and can be power-managed through an
MSTP clock.  This applies to most on-SoC devices, which have a
one-to-one mapping from SoC device to DT device node.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This commit is contained in:
Geert Uytterhoeven 2015-08-04 14:28:12 +02:00 committed by Simon Horman
parent 797a0626e0
commit 4b31bad51f
1 changed files with 7 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
arch/arm/boot/dts/r8a7793.dtsi
View File

@ -68,6 +68,7 @@ cmt0: timer@ffca0000 {
<0 143 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp1_clks R8A7793_CLK_CMT0>;
clock-names = "fck";
power-domains = <&cpg_clocks>;
renesas,channels-mask = <0x60>;
@ -87,6 +88,7 @@ cmt1: timer@e6130000 {
<0 127 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7793_CLK_CMT1>;
clock-names = "fck";
power-domains = <&cpg_clocks>;
renesas,channels-mask = <0xff>;
@ -109,6 +111,7 @@ irqc0: interrupt-controller@e61c0000 {
<0 16 IRQ_TYPE_LEVEL_HIGH>,
<0 17 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp4_clks R8A7793_CLK_IRQC>;
power-domains = <&cpg_clocks>;
};
scif0: serial@e6e60000 {
@ -117,6 +120,7 @@ scif0: serial@e6e60000 {
interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp7_clks R8A7793_CLK_SCIF0>;
clock-names = "sci_ick";
power-domains = <&cpg_clocks>;
status = "disabled";
};
@ -126,6 +130,7 @@ scif1: serial@e6e68000 {
interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp7_clks R8A7793_CLK_SCIF1>;
clock-names = "sci_ick";
power-domains = <&cpg_clocks>;
status = "disabled";
};
@ -134,6 +139,7 @@ ether: ethernet@ee700000 {
reg = <0 0xee700000 0 0x400>;
interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp8_clks R8A7793_CLK_ETHER>;
power-domains = <&cpg_clocks>;
phy-mode = "rmii";
#address-cells = <1>;
#size-cells = <0>;
@ -164,6 +170,7 @@ cpg_clocks: cpg_clocks@e6150000 {
clock-output-names = "main", "pll0", "pll1", "pll3",
"lb", "qspi", "sdh", "sd0", "z",
"rcan", "adsp";
#power-domain-cells = <0>;
};
/* Variable factor clocks */