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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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cf8fb73c23
Set the Latency Tolerance Reporting (LTR) values for the "PCIe-like" GbE MAC in the Lynx Point PCH based on Rx buffer size and link speed when link is up (which must not exceed the maximum latency supported by the platform), otherwise specify there is no LTR requirement. Unlike true-PCIe devices which set the LTR maximum snoop/no-snoop latencies in the LTR Extended Capability Structure in the PCIe Extended Capability register set, on this device LTR is set by writing the equivalent snoop/no-snoop latencies in the LTRV register in the MAC and set the SEND bit to send an Intel On-chip System Fabric sideband (IOSF-SB) message to the PMC. Signed-off-by: Bruce Allan <bruce.w.allan@intel.com> Tested-by: Jeff Pieper <jeffrey.e.pieper@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> |
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| .. | ||
| 80003es2lan.c | ||
| 80003es2lan.h | ||
| 82571.c | ||
| 82571.h | ||
| defines.h | ||
| e1000.h | ||
| ethtool.c | ||
| hw.h | ||
| ich8lan.c | ||
| ich8lan.h | ||
| mac.c | ||
| mac.h | ||
| Makefile | ||
| manage.c | ||
| manage.h | ||
| netdev.c | ||
| nvm.c | ||
| nvm.h | ||
| param.c | ||
| phy.c | ||
| phy.h | ||
| ptp.c | ||
| regs.h | ||