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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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402bfb3c13
The A80 SoC has configuration registers for I/O bias voltage. Incorrect settings would make the affected peripherals inoperable in some cases, such as Ethernet RGMII signals biased at 2.5V with the settings still at 3.3V. However low speed signals such as MDIO on the same group of pins seem to be unaffected. Previously there was no way to know what the actual voltage used was, short of hard-coding a value in the device tree. With the new pin bank regulator supply support in place, the driver can now query the regulator for its voltage, and if it's valid (as opposed to being the dummy regulator), set the bias voltage setting accordingly. Add a quirk to denote the presence of the configuration registers, and a function to set the correct setting based on the voltage read back from the regulator. This is only done when the regulator is first acquired and enabled. While it would be nice to have a notifier on the regulator so that when the voltage changes, the driver can update the setting, in practice no board currently supports dynamic changing of the I/O voltages. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
179 lines
6.2 KiB
C
179 lines
6.2 KiB
C
/*
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* Allwinner A80 SoCs special pins pinctrl driver.
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*
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* Copyright (C) 2014 Maxime Ripard
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* Maxime Ripard <maxime.ripard@free-electrons.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/pinctrl/pinctrl.h>
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#include <linux/reset.h>
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#include "pinctrl-sunxi.h"
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static const struct sunxi_desc_pin sun9i_a80_r_pins[] = {
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SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 0),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x3, "s_uart"), /* TX */
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), /* PL_EINT0 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 1),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x3, "s_uart"), /* RX */
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)), /* PL_EINT1 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 2),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x3, "s_jtag"), /* TMS */
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)), /* PL_EINT2 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 3),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x3, "s_jtag"), /* TCK */
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)), /* PL_EINT3 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 4),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x3, "s_jtag"), /* TDO */
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)), /* PL_EINT4 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 5),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x3, "s_jtag"), /* TDI */
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)), /* PL_EINT5 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 6),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x3, "s_cir_rx"),
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)), /* PL_EINT6 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 7),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x3, "1wire"),
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)), /* PL_EINT7 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 8),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "s_ps2"), /* SCK1 */
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)), /* PL_EINT8 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 9),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "s_ps2"), /* SDA1 */
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)), /* PL_EINT9 */
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/* Hole */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 0),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)), /* PM_EINT0 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 1),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)), /* PM_EINT1 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 2),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2)), /* PM_EINT2 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 3),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)), /* PM_EINT3 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 4),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x3, "s_i2s1"), /* LRCKR */
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SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)), /* PM_EINT4 */
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/* Hole */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 8),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x3, "s_i2c1"), /* SCK */
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SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 8)), /* PM_EINT8 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 9),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x3, "s_i2c1"), /* SDA */
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SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 9)), /* PM_EINT9 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 10),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "s_i2s0"), /* MCLK */
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SUNXI_FUNCTION(0x3, "s_i2s1")), /* MCLK */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 11),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "s_i2s0"), /* BCLK */
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SUNXI_FUNCTION(0x3, "s_i2s1")), /* BCLK */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 12),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "s_i2s0"), /* LRCK */
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SUNXI_FUNCTION(0x3, "s_i2s1")), /* LRCK */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 13),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "s_i2s0"), /* DIN */
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SUNXI_FUNCTION(0x3, "s_i2s1")), /* DIN */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 14),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "s_i2s0"), /* DOUT */
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SUNXI_FUNCTION(0x3, "s_i2s1")), /* DOUT */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 15),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 15)), /* PM_EINT15 */
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/* Hole */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(N, 0),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "s_i2c0"), /* SCK */
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SUNXI_FUNCTION(0x3, "s_rsb")), /* SCK */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(N, 1),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "s_i2c0"), /* SDA */
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SUNXI_FUNCTION(0x3, "s_rsb")), /* SDA */
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};
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static const struct sunxi_pinctrl_desc sun9i_a80_r_pinctrl_data = {
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.pins = sun9i_a80_r_pins,
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.npins = ARRAY_SIZE(sun9i_a80_r_pins),
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.pin_base = PL_BASE,
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.irq_banks = 2,
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.disable_strict_mode = true,
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.has_io_bias_cfg = true,
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};
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static int sun9i_a80_r_pinctrl_probe(struct platform_device *pdev)
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{
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return sunxi_pinctrl_init(pdev,
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&sun9i_a80_r_pinctrl_data);
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}
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static const struct of_device_id sun9i_a80_r_pinctrl_match[] = {
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{ .compatible = "allwinner,sun9i-a80-r-pinctrl", },
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{}
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};
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static struct platform_driver sun9i_a80_r_pinctrl_driver = {
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.probe = sun9i_a80_r_pinctrl_probe,
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.driver = {
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.name = "sun9i-a80-r-pinctrl",
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.owner = THIS_MODULE,
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.of_match_table = sun9i_a80_r_pinctrl_match,
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},
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};
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builtin_platform_driver(sun9i_a80_r_pinctrl_driver);
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