Yu-ting Shen cab5dec425 drm/amd/display: limit display clock to 100MHz to avoid FIFO error ... [Why] when changing display clock, SMU need to use power up DFS and use DENTIST to ramp DFS DID to switch target frequency before switching back to bypass. [How] fixed the minimum display clock to 100MHz, it's W/A the same with PCO. Signed-off-by: Yu-ting Shen <Yu-ting.Shen@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2020-02-25 11:10:08 -05:00
..
acp	drm/amdgpu: fix license on Kconfig and Makefiles	2019-12-11 15:22:08 -05:00
amdgpu	drm/amdgpu: Improve Vega20 XGMI TLB flush workaround	2020-02-25 11:01:57 -05:00
amdkfd	drm/amdkfd: refactor runtime pm for baco	2020-02-12 16:00:54 -05:00
display	drm/amd/display: limit display clock to 100MHz to avoid FIFO error	2020-02-25 11:10:08 -05:00
include	amdgpu/gmc_v9: save/restore sdpif regs during S3	2020-02-25 11:01:26 -05:00
powerplay	drm/amdgpu: fix memory leak during TDR test(v2)	2020-02-25 11:01:25 -05:00