Yu-ting Shen cab5dec425 drm/amd/display: limit display clock to 100MHz to avoid FIFO error ... [Why] when changing display clock, SMU need to use power up DFS and use DENTIST to ramp DFS DID to switch target frequency before switching back to bypass. [How] fixed the minimum display clock to 100MHz, it's W/A the same with PCO. Signed-off-by: Yu-ting Shen <Yu-ting.Shen@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2020-02-25 11:10:08 -05:00
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drm	drm/amd/display: limit display clock to 100MHz to avoid FIFO error	2020-02-25 11:10:08 -05:00
host1x
ipu-v3
vga
Makefile