mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-26 19:15:25 +07:00
d1876a0bcf
Currently common clock and reset IDs were used, however, each clock and
reset ID should be used for each channel.
Pro5 and PXs2 are affected by this fix, but the SCSSI clock gate of Pro5 is
common to all channels.
Fixes: 92fa4f4cc2 ("ARM: dts: uniphier: add SPI node for UniPhier 32bit SoCs")
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
783 lines
18 KiB
Plaintext
783 lines
18 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+ OR MIT
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//
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// Device Tree Source for UniPhier PXs2 SoC
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//
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// Copyright (C) 2015-2016 Socionext Inc.
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// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
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#include <dt-bindings/gpio/uniphier-gpio.h>
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#include <dt-bindings/thermal/thermal.h>
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/ {
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compatible = "socionext,uniphier-pxs2";
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#address-cells = <1>;
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#size-cells = <1>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <0>;
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clocks = <&sys_clk 32>;
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enable-method = "psci";
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next-level-cache = <&l2>;
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operating-points-v2 = <&cpu_opp>;
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#cooling-cells = <2>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <1>;
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clocks = <&sys_clk 32>;
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enable-method = "psci";
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next-level-cache = <&l2>;
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operating-points-v2 = <&cpu_opp>;
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#cooling-cells = <2>;
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};
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cpu2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <2>;
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clocks = <&sys_clk 32>;
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enable-method = "psci";
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next-level-cache = <&l2>;
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operating-points-v2 = <&cpu_opp>;
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#cooling-cells = <2>;
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};
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cpu3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <3>;
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clocks = <&sys_clk 32>;
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enable-method = "psci";
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next-level-cache = <&l2>;
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operating-points-v2 = <&cpu_opp>;
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#cooling-cells = <2>;
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};
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};
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cpu_opp: opp-table {
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compatible = "operating-points-v2";
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opp-shared;
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opp-100000000 {
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opp-hz = /bits/ 64 <100000000>;
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clock-latency-ns = <300>;
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};
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opp-150000000 {
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opp-hz = /bits/ 64 <150000000>;
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clock-latency-ns = <300>;
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};
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opp-200000000 {
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opp-hz = /bits/ 64 <200000000>;
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clock-latency-ns = <300>;
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};
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opp-300000000 {
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opp-hz = /bits/ 64 <300000000>;
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clock-latency-ns = <300>;
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};
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opp-400000000 {
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opp-hz = /bits/ 64 <400000000>;
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clock-latency-ns = <300>;
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};
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opp-600000000 {
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opp-hz = /bits/ 64 <600000000>;
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clock-latency-ns = <300>;
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};
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opp-800000000 {
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opp-hz = /bits/ 64 <800000000>;
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clock-latency-ns = <300>;
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};
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opp-1200000000 {
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opp-hz = /bits/ 64 <1200000000>;
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clock-latency-ns = <300>;
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};
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};
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psci {
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compatible = "arm,psci-0.2";
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method = "smc";
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};
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clocks {
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refclk: ref {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <25000000>;
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};
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arm_timer_clk: arm-timer {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <50000000>;
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};
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};
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thermal-zones {
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cpu-thermal {
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polling-delay-passive = <250>; /* 250ms */
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polling-delay = <1000>; /* 1000ms */
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thermal-sensors = <&pvtctl>;
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trips {
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cpu_crit: cpu-crit {
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temperature = <95000>; /* 95C */
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hysteresis = <2000>;
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type = "critical";
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};
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cpu_alert: cpu-alert {
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temperature = <85000>; /* 85C */
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hysteresis = <2000>;
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type = "passive";
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};
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};
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cooling-maps {
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map {
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trip = <&cpu_alert>;
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cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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};
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};
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};
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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interrupt-parent = <&intc>;
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l2: cache-controller@500c0000 {
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compatible = "socionext,uniphier-system-cache";
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reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
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<0x506c0000 0x400>;
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interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>;
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cache-unified;
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cache-size = <(1280 * 1024)>;
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cache-sets = <512>;
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cache-line-size = <128>;
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cache-level = <2>;
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};
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spi0: spi@54006000 {
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compatible = "socionext,uniphier-scssi";
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status = "disabled";
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reg = <0x54006000 0x100>;
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interrupts = <0 39 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_spi0>;
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clocks = <&peri_clk 11>;
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resets = <&peri_rst 11>;
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};
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spi1: spi@54006100 {
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compatible = "socionext,uniphier-scssi";
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status = "disabled";
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reg = <0x54006100 0x100>;
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interrupts = <0 216 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_spi1>;
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clocks = <&peri_clk 12>;
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resets = <&peri_rst 12>;
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};
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serial0: serial@54006800 {
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compatible = "socionext,uniphier-uart";
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status = "disabled";
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reg = <0x54006800 0x40>;
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interrupts = <0 33 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart0>;
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clocks = <&peri_clk 0>;
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resets = <&peri_rst 0>;
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};
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serial1: serial@54006900 {
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compatible = "socionext,uniphier-uart";
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status = "disabled";
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reg = <0x54006900 0x40>;
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interrupts = <0 35 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1>;
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clocks = <&peri_clk 1>;
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resets = <&peri_rst 1>;
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};
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serial2: serial@54006a00 {
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compatible = "socionext,uniphier-uart";
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status = "disabled";
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reg = <0x54006a00 0x40>;
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interrupts = <0 37 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart2>;
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clocks = <&peri_clk 2>;
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resets = <&peri_rst 2>;
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};
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serial3: serial@54006b00 {
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compatible = "socionext,uniphier-uart";
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status = "disabled";
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reg = <0x54006b00 0x40>;
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interrupts = <0 177 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart3>;
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clocks = <&peri_clk 3>;
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resets = <&peri_rst 3>;
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};
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gpio: gpio@55000000 {
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compatible = "socionext,uniphier-gpio";
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reg = <0x55000000 0x200>;
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interrupt-parent = <&aidet>;
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interrupt-controller;
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#interrupt-cells = <2>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&pinctrl 0 0 0>,
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<&pinctrl 96 0 0>;
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gpio-ranges-group-names = "gpio_range0",
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"gpio_range1";
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ngpios = <232>;
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socionext,interrupt-ranges = <0 48 16>, <16 154 5>,
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<21 217 3>;
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};
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audio@56000000 {
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compatible = "socionext,uniphier-pxs2-aio";
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reg = <0x56000000 0x80000>;
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interrupts = <0 144 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_ain1>,
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<&pinctrl_ain2>,
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<&pinctrl_ainiec1>,
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<&pinctrl_aout2>,
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<&pinctrl_aout3>,
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<&pinctrl_aoutiec1>,
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<&pinctrl_aoutiec2>;
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clock-names = "aio";
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clocks = <&sys_clk 40>;
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reset-names = "aio";
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resets = <&sys_rst 40>;
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#sound-dai-cells = <1>;
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socionext,syscon = <&soc_glue>;
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i2s_port0: port@0 {
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i2s_hdmi: endpoint {
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};
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};
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i2s_port1: port@1 {
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i2s_line: endpoint {
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};
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};
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i2s_port2: port@2 {
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i2s_aux: endpoint {
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};
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};
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spdif_port0: port@3 {
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spdif_hiecout1: endpoint {
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};
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};
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spdif_port1: port@4 {
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spdif_iecout1: endpoint {
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};
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};
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comp_spdif_port0: port@5 {
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comp_spdif_hiecout1: endpoint {
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};
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};
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comp_spdif_port1: port@6 {
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comp_spdif_iecout1: endpoint {
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};
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};
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};
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i2c0: i2c@58780000 {
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compatible = "socionext,uniphier-fi2c";
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status = "disabled";
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reg = <0x58780000 0x80>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <0 41 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c0>;
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clocks = <&peri_clk 4>;
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resets = <&peri_rst 4>;
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clock-frequency = <100000>;
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};
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i2c1: i2c@58781000 {
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compatible = "socionext,uniphier-fi2c";
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status = "disabled";
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reg = <0x58781000 0x80>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <0 42 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c1>;
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clocks = <&peri_clk 5>;
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resets = <&peri_rst 5>;
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clock-frequency = <100000>;
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};
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i2c2: i2c@58782000 {
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compatible = "socionext,uniphier-fi2c";
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status = "disabled";
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reg = <0x58782000 0x80>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <0 43 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c2>;
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clocks = <&peri_clk 6>;
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resets = <&peri_rst 6>;
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clock-frequency = <100000>;
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};
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i2c3: i2c@58783000 {
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compatible = "socionext,uniphier-fi2c";
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status = "disabled";
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reg = <0x58783000 0x80>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <0 44 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c3>;
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clocks = <&peri_clk 7>;
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resets = <&peri_rst 7>;
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clock-frequency = <100000>;
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};
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/* chip-internal connection for DMD */
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i2c4: i2c@58784000 {
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compatible = "socionext,uniphier-fi2c";
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reg = <0x58784000 0x80>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <0 45 4>;
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clocks = <&peri_clk 8>;
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resets = <&peri_rst 8>;
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clock-frequency = <400000>;
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};
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/* chip-internal connection for STM */
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i2c5: i2c@58785000 {
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compatible = "socionext,uniphier-fi2c";
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reg = <0x58785000 0x80>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <0 25 4>;
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clocks = <&peri_clk 9>;
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resets = <&peri_rst 9>;
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clock-frequency = <400000>;
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};
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/* chip-internal connection for HDMI */
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i2c6: i2c@58786000 {
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compatible = "socionext,uniphier-fi2c";
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reg = <0x58786000 0x80>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <0 26 4>;
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clocks = <&peri_clk 10>;
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resets = <&peri_rst 10>;
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clock-frequency = <400000>;
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};
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system_bus: system-bus@58c00000 {
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compatible = "socionext,uniphier-system-bus";
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status = "disabled";
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reg = <0x58c00000 0x400>;
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#address-cells = <2>;
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#size-cells = <1>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_system_bus>;
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};
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smpctrl@59801000 {
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compatible = "socionext,uniphier-smpctrl";
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reg = <0x59801000 0x400>;
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};
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sdctrl@59810000 {
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compatible = "socionext,uniphier-pxs2-sdctrl",
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"simple-mfd", "syscon";
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reg = <0x59810000 0x400>;
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sd_clk: clock {
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compatible = "socionext,uniphier-pxs2-sd-clock";
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#clock-cells = <1>;
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};
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sd_rst: reset {
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compatible = "socionext,uniphier-pxs2-sd-reset";
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#reset-cells = <1>;
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};
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};
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perictrl@59820000 {
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compatible = "socionext,uniphier-pxs2-perictrl",
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"simple-mfd", "syscon";
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reg = <0x59820000 0x200>;
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peri_clk: clock {
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compatible = "socionext,uniphier-pxs2-peri-clock";
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#clock-cells = <1>;
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};
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peri_rst: reset {
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compatible = "socionext,uniphier-pxs2-peri-reset";
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#reset-cells = <1>;
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};
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};
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emmc: mmc@5a000000 {
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compatible = "socionext,uniphier-sd-v3.1.1";
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status = "disabled";
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reg = <0x5a000000 0x800>;
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interrupts = <0 78 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_emmc>;
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clocks = <&sd_clk 1>;
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reset-names = "host", "hw";
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resets = <&sd_rst 1>, <&sd_rst 6>;
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bus-width = <8>;
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cap-mmc-highspeed;
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cap-mmc-hw-reset;
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non-removable;
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};
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sd: mmc@5a400000 {
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compatible = "socionext,uniphier-sd-v3.1.1";
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status = "disabled";
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reg = <0x5a400000 0x800>;
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interrupts = <0 76 4>;
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pinctrl-names = "default", "uhs";
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pinctrl-0 = <&pinctrl_sd>;
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pinctrl-1 = <&pinctrl_sd_uhs>;
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clocks = <&sd_clk 0>;
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reset-names = "host";
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resets = <&sd_rst 0>;
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bus-width = <4>;
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cap-sd-highspeed;
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sd-uhs-sdr12;
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sd-uhs-sdr25;
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sd-uhs-sdr50;
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};
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soc_glue: soc-glue@5f800000 {
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compatible = "socionext,uniphier-pxs2-soc-glue",
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"simple-mfd", "syscon";
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reg = <0x5f800000 0x2000>;
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pinctrl: pinctrl {
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compatible = "socionext,uniphier-pxs2-pinctrl";
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};
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};
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soc-glue@5f900000 {
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compatible = "socionext,uniphier-pxs2-soc-glue-debug",
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"simple-mfd";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x5f900000 0x2000>;
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efuse@100 {
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compatible = "socionext,uniphier-efuse";
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reg = <0x100 0x28>;
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};
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efuse@200 {
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compatible = "socionext,uniphier-efuse";
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reg = <0x200 0x58>;
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};
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|
};
|
|
|
|
aidet: interrupt-controller@5fc20000 {
|
|
compatible = "socionext,uniphier-pxs2-aidet";
|
|
reg = <0x5fc20000 0x200>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
timer@60000200 {
|
|
compatible = "arm,cortex-a9-global-timer";
|
|
reg = <0x60000200 0x20>;
|
|
interrupts = <1 11 0xf04>;
|
|
clocks = <&arm_timer_clk>;
|
|
};
|
|
|
|
timer@60000600 {
|
|
compatible = "arm,cortex-a9-twd-timer";
|
|
reg = <0x60000600 0x20>;
|
|
interrupts = <1 13 0xf04>;
|
|
clocks = <&arm_timer_clk>;
|
|
};
|
|
|
|
intc: interrupt-controller@60001000 {
|
|
compatible = "arm,cortex-a9-gic";
|
|
reg = <0x60001000 0x1000>,
|
|
<0x60000100 0x100>;
|
|
#interrupt-cells = <3>;
|
|
interrupt-controller;
|
|
};
|
|
|
|
sysctrl@61840000 {
|
|
compatible = "socionext,uniphier-pxs2-sysctrl",
|
|
"simple-mfd", "syscon";
|
|
reg = <0x61840000 0x10000>;
|
|
|
|
sys_clk: clock {
|
|
compatible = "socionext,uniphier-pxs2-clock";
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
sys_rst: reset {
|
|
compatible = "socionext,uniphier-pxs2-reset";
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
pvtctl: pvtctl {
|
|
compatible = "socionext,uniphier-pxs2-thermal";
|
|
interrupts = <0 3 4>;
|
|
#thermal-sensor-cells = <0>;
|
|
socionext,tmod-calibration = <0x0f86 0x6844>;
|
|
};
|
|
};
|
|
|
|
eth: ethernet@65000000 {
|
|
compatible = "socionext,uniphier-pxs2-ave4";
|
|
status = "disabled";
|
|
reg = <0x65000000 0x8500>;
|
|
interrupts = <0 66 4>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_ether_rgmii>;
|
|
clock-names = "ether";
|
|
clocks = <&sys_clk 6>;
|
|
reset-names = "ether";
|
|
resets = <&sys_rst 6>;
|
|
phy-mode = "rgmii";
|
|
local-mac-address = [00 00 00 00 00 00];
|
|
socionext,syscon-phy-mode = <&soc_glue 0>;
|
|
|
|
mdio: mdio {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
};
|
|
|
|
usb0: usb@65a00000 {
|
|
compatible = "socionext,uniphier-dwc3", "snps,dwc3";
|
|
status = "disabled";
|
|
reg = <0x65a00000 0xcd00>;
|
|
interrupt-names = "host", "peripheral";
|
|
interrupts = <0 134 4>, <0 135 4>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>;
|
|
clock-names = "ref", "bus_early", "suspend";
|
|
clocks = <&sys_clk 14>, <&sys_clk 14>, <&sys_clk 14>;
|
|
resets = <&usb0_rst 15>;
|
|
phys = <&usb0_hsphy0>, <&usb0_hsphy1>,
|
|
<&usb0_ssphy0>, <&usb0_ssphy1>;
|
|
dr_mode = "host";
|
|
};
|
|
|
|
usb-glue@65b00000 {
|
|
compatible = "socionext,uniphier-pxs2-dwc3-glue",
|
|
"simple-mfd";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0 0x65b00000 0x400>;
|
|
|
|
usb0_rst: reset@0 {
|
|
compatible = "socionext,uniphier-pxs2-usb3-reset";
|
|
reg = <0x0 0x4>;
|
|
#reset-cells = <1>;
|
|
clock-names = "link";
|
|
clocks = <&sys_clk 14>;
|
|
reset-names = "link";
|
|
resets = <&sys_rst 14>;
|
|
};
|
|
|
|
usb0_vbus0: regulator@100 {
|
|
compatible = "socionext,uniphier-pxs2-usb3-regulator";
|
|
reg = <0x100 0x10>;
|
|
clock-names = "link";
|
|
clocks = <&sys_clk 14>;
|
|
reset-names = "link";
|
|
resets = <&sys_rst 14>;
|
|
};
|
|
|
|
usb0_vbus1: regulator@110 {
|
|
compatible = "socionext,uniphier-pxs2-usb3-regulator";
|
|
reg = <0x110 0x10>;
|
|
clock-names = "link";
|
|
clocks = <&sys_clk 14>;
|
|
reset-names = "link";
|
|
resets = <&sys_rst 14>;
|
|
};
|
|
|
|
usb0_hsphy0: hs-phy@200 {
|
|
compatible = "socionext,uniphier-pxs2-usb3-hsphy";
|
|
reg = <0x200 0x10>;
|
|
#phy-cells = <0>;
|
|
clock-names = "link", "phy";
|
|
clocks = <&sys_clk 14>, <&sys_clk 16>;
|
|
reset-names = "link", "phy";
|
|
resets = <&sys_rst 14>, <&sys_rst 16>;
|
|
vbus-supply = <&usb0_vbus0>;
|
|
};
|
|
|
|
usb0_hsphy1: hs-phy@210 {
|
|
compatible = "socionext,uniphier-pxs2-usb3-hsphy";
|
|
reg = <0x210 0x10>;
|
|
#phy-cells = <0>;
|
|
clock-names = "link", "phy";
|
|
clocks = <&sys_clk 14>, <&sys_clk 16>;
|
|
reset-names = "link", "phy";
|
|
resets = <&sys_rst 14>, <&sys_rst 16>;
|
|
vbus-supply = <&usb0_vbus1>;
|
|
};
|
|
|
|
usb0_ssphy0: ss-phy@300 {
|
|
compatible = "socionext,uniphier-pxs2-usb3-ssphy";
|
|
reg = <0x300 0x10>;
|
|
#phy-cells = <0>;
|
|
clock-names = "link", "phy";
|
|
clocks = <&sys_clk 14>, <&sys_clk 17>;
|
|
reset-names = "link", "phy";
|
|
resets = <&sys_rst 14>, <&sys_rst 17>;
|
|
vbus-supply = <&usb0_vbus0>;
|
|
};
|
|
|
|
usb0_ssphy1: ss-phy@310 {
|
|
compatible = "socionext,uniphier-pxs2-usb3-ssphy";
|
|
reg = <0x310 0x10>;
|
|
#phy-cells = <0>;
|
|
clock-names = "link", "phy";
|
|
clocks = <&sys_clk 14>, <&sys_clk 18>;
|
|
reset-names = "link", "phy";
|
|
resets = <&sys_rst 14>, <&sys_rst 18>;
|
|
vbus-supply = <&usb0_vbus1>;
|
|
};
|
|
};
|
|
|
|
usb1: usb@65c00000 {
|
|
compatible = "socionext,uniphier-dwc3", "snps,dwc3";
|
|
status = "disabled";
|
|
reg = <0x65c00000 0xcd00>;
|
|
interrupt-names = "host", "peripheral";
|
|
interrupts = <0 137 4>, <0 138 4>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>;
|
|
clock-names = "ref", "bus_early", "suspend";
|
|
clocks = <&sys_clk 15>, <&sys_clk 15>, <&sys_clk 15>;
|
|
resets = <&usb1_rst 15>;
|
|
phys = <&usb1_hsphy0>, <&usb1_hsphy1>, <&usb1_ssphy0>;
|
|
dr_mode = "host";
|
|
};
|
|
|
|
usb-glue@65d00000 {
|
|
compatible = "socionext,uniphier-pxs2-dwc3-glue",
|
|
"simple-mfd";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0 0x65d00000 0x400>;
|
|
|
|
usb1_rst: reset@0 {
|
|
compatible = "socionext,uniphier-pxs2-usb3-reset";
|
|
reg = <0x0 0x4>;
|
|
#reset-cells = <1>;
|
|
clock-names = "link";
|
|
clocks = <&sys_clk 15>;
|
|
reset-names = "link";
|
|
resets = <&sys_rst 15>;
|
|
};
|
|
|
|
usb1_vbus0: regulator@100 {
|
|
compatible = "socionext,uniphier-pxs2-usb3-regulator";
|
|
reg = <0x100 0x10>;
|
|
clock-names = "link";
|
|
clocks = <&sys_clk 15>;
|
|
reset-names = "link";
|
|
resets = <&sys_rst 15>;
|
|
};
|
|
|
|
usb1_vbus1: regulator@110 {
|
|
compatible = "socionext,uniphier-pxs2-usb3-regulator";
|
|
reg = <0x110 0x10>;
|
|
clock-names = "link";
|
|
clocks = <&sys_clk 15>;
|
|
reset-names = "link";
|
|
resets = <&sys_rst 15>;
|
|
};
|
|
|
|
usb1_hsphy0: hs-phy@200 {
|
|
compatible = "socionext,uniphier-pxs2-usb3-hsphy";
|
|
reg = <0x200 0x10>;
|
|
#phy-cells = <0>;
|
|
clock-names = "link", "phy";
|
|
clocks = <&sys_clk 15>, <&sys_clk 20>;
|
|
reset-names = "link", "phy";
|
|
resets = <&sys_rst 15>, <&sys_rst 20>;
|
|
vbus-supply = <&usb1_vbus0>;
|
|
};
|
|
|
|
usb1_hsphy1: hs-phy@210 {
|
|
compatible = "socionext,uniphier-pxs2-usb3-hsphy";
|
|
reg = <0x210 0x10>;
|
|
#phy-cells = <0>;
|
|
clock-names = "link", "phy";
|
|
clocks = <&sys_clk 15>, <&sys_clk 20>;
|
|
reset-names = "link", "phy";
|
|
resets = <&sys_rst 15>, <&sys_rst 20>;
|
|
vbus-supply = <&usb1_vbus1>;
|
|
};
|
|
|
|
usb1_ssphy0: ss-phy@300 {
|
|
compatible = "socionext,uniphier-pxs2-usb3-ssphy";
|
|
reg = <0x300 0x10>;
|
|
#phy-cells = <0>;
|
|
clock-names = "link", "phy";
|
|
clocks = <&sys_clk 15>, <&sys_clk 21>;
|
|
reset-names = "link", "phy";
|
|
resets = <&sys_rst 15>, <&sys_rst 21>;
|
|
vbus-supply = <&usb1_vbus0>;
|
|
};
|
|
};
|
|
|
|
nand: nand-controller@68000000 {
|
|
compatible = "socionext,uniphier-denali-nand-v5b";
|
|
status = "disabled";
|
|
reg-names = "nand_data", "denali_reg";
|
|
reg = <0x68000000 0x20>, <0x68100000 0x1000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <0 65 4>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_nand>;
|
|
clock-names = "nand", "nand_x", "ecc";
|
|
clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
|
|
reset-names = "nand", "reg";
|
|
resets = <&sys_rst 2>, <&sys_rst 2>;
|
|
};
|
|
};
|
|
};
|
|
|
|
#include "uniphier-pinctrl.dtsi"
|