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ARM: dts: uniphier: add SPI node for UniPhier 32bit SoCs

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Add nodes of SPI controller for LD4, Pro4, sLD8, Pro5 and PXs2.

Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
This commit is contained in:
Kunihiko Hayashi 2018-07-26 16:09:59 +09:00 committed by Masahiro Yamada
parent dc0a2098cc
commit 92fa4f4cc2
5 changed files with 77 additions and 0 deletions
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11
arch/arm/boot/dts/uniphier-ld4.dtsi
View File

@ -63,6 +63,17 @@ l2: l2-cache@500c0000 {
cache-level = <2>;
};
spi: spi@54006000 {
compatible = "socionext,uniphier-scssi";
status = "disabled";
reg = <0x54006000 0x100>;
interrupts = <0 39 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi0>;
clocks = <&peri_clk 11>;
resets = <&peri_rst 11>;
};
serial0: serial@54006800 {
compatible = "socionext,uniphier-uart";
status = "disabled";

11
arch/arm/boot/dts/uniphier-pro4.dtsi
View File

@ -71,6 +71,17 @@ l2: l2-cache@500c0000 {
cache-level = <2>;
};
spi0: spi@54006000 {
compatible = "socionext,uniphier-scssi";
status = "disabled";
reg = <0x54006000 0x100>;
interrupts = <0 39 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi0>;
clocks = <&peri_clk 11>;
resets = <&peri_rst 11>;
};
serial0: serial@54006800 {
compatible = "socionext,uniphier-uart";
status = "disabled";

22
arch/arm/boot/dts/uniphier-pro5.dtsi
View File

@ -156,6 +156,28 @@ l3: l3-cache@500c8000 {
cache-level = <3>;
};
spi0: spi@54006000 {
compatible = "socionext,uniphier-scssi";
status = "disabled";
reg = <0x54006000 0x100>;
interrupts = <0 39 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi0>;
clocks = <&peri_clk 11>;
resets = <&peri_rst 11>;
};
spi1: spi@54006100 {
compatible = "socionext,uniphier-scssi";
status = "disabled";
reg = <0x54006100 0x100>;
interrupts = <0 216 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi1>;
clocks = <&peri_clk 11>;
resets = <&peri_rst 11>;
};
serial0: serial@54006800 {
compatible = "socionext,uniphier-uart";
status = "disabled";

22
arch/arm/boot/dts/uniphier-pxs2.dtsi
View File

@ -167,6 +167,28 @@ l2: l2-cache@500c0000 {
cache-level = <2>;
};
spi0: spi@54006000 {
compatible = "socionext,uniphier-scssi";
status = "disabled";
reg = <0x54006000 0x100>;
interrupts = <0 39 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi0>;
clocks = <&peri_clk 11>;
resets = <&peri_rst 11>;
};
spi1: spi@54006100 {
compatible = "socionext,uniphier-scssi";
status = "disabled";
reg = <0x54006100 0x100>;
interrupts = <0 216 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi1>;
clocks = <&peri_clk 11>;
resets = <&peri_rst 11>;
};
serial0: serial@54006800 {
compatible = "socionext,uniphier-uart";
status = "disabled";

11
arch/arm/boot/dts/uniphier-sld8.dtsi
View File

@ -63,6 +63,17 @@ l2: l2-cache@500c0000 {
cache-level = <2>;
};
spi: spi@54006000 {
compatible = "socionext,uniphier-scssi";
status = "disabled";
reg = <0x54006000 0x100>;
interrupts = <0 39 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi0>;
clocks = <&peri_clk 11>;
resets = <&peri_rst 11>;
};
serial0: serial@54006800 {
compatible = "socionext,uniphier-uart";
status = "disabled";