Charlene Liu 4850ce697f drm/amd/display: Add hubp_init entry to hubp vtable ... Different HW will need to init HUBP differently. For now, add a vtable entry, and hook a NO-OP for DCN1 and DCN2. In addition, future HW will need to access the HUBPREQ_DEBUG and CUR_TTU_CNTL0 register for hubp_init. Add that here. Signed-off-by: Charlene Liu <charlene.liu@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Acked-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2019-06-22 09:34:10 -05:00
..
hw	drm/amd/display: Add hubp_init entry to hubp vtable	2019-06-22 09:34:10 -05:00
bw_fixed.h	drm/amd/display: explicit uint64_t casting	2018-11-05 14:20:50 -05:00
clock_source.h	drm/amd/display: Keep clocks high before seamless boot done	2019-03-19 15:04:03 -05:00
compressor.h	drm/amd/display: fbc state could not reach while enable fbc	2018-11-30 12:02:35 -05:00
core_status.h	drm/amd/display: Add DSC support for Navi (v2)	2019-06-22 09:34:07 -05:00
core_types.h	drm/amd/display: Acquire DSC HW resource only if required by stream	2019-06-22 09:34:10 -05:00
custom_float.h	drm/amd/display: Enable regamma 25 segments and use double buffer.	2017-09-26 17:14:18 -04:00
dc_link_ddc.h	drm/amd/display: Respect aux return values	2019-03-19 15:04:02 -05:00
dc_link_dp.h	drm/amd/display: Add DSC support for Navi (v2)	2019-06-22 09:34:07 -05:00
dce_calcs.h	drm/amdgpu/display: remove VEGAM config option	2018-05-18 16:08:18 -05:00
dcn_calcs.h	drm/amd/display: make clk mgr soc specific	2019-05-31 10:39:29 -05:00
hw_sequencer.h	drm/amd/display: add global master update lock for DCN2	2019-06-22 09:34:10 -05:00
link_hwss.h	drm/amd/display: add eDP 1.2+ polling for T7	2018-02-19 14:19:34 -05:00
reg_helper.h	drm/amd/display: Combine field toggle macro and sequence write macro.	2019-03-19 15:36:49 -05:00
resource.h	drm/amd/display: Add DSC support for Navi (v2)	2019-06-22 09:34:07 -05:00
vm_helper.h	Revert "drm/amd/display: move vmid determination logic out of dc"	2019-06-20 12:26:57 -05:00