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b8d2798f32
framework. The only patch that can even be considered "core" adds another clk_get() variant. The rest of the changes are in drivers for various SoCs, and we have a few bits for ARM shmobile architecture code (dts and mach) due to the dependency we're breaking between shmobile architecture code and its clk driver. Those shmobile bits have also been pulled into arm-soc tree. Here's the summary: Core: - Support for devm_get_clk_from_child() used with DT bindings that have subnodes with the 'clocks' property New Drivers: - Allwinner A64 (sun50i) - i.MX imx6ull - Socionext's UniPhier SoC CPUs - Mediatek MT2701 SoCs - Rockchip rk1108 SoCs - Qualcomm MSM8994/MSM8992 SoCS - Qualcomm RPM Clocks - Hisilicon Hi3516CV300 and Hi3798CV200 CRG - Oxford Semiconductor OX820 and OX810SE SoCs - Renesas RZ/G1M and RZ/GIE SoCs - Renesas R-Car RST driver for mode pin states Updates: - Four Allwinner SoCs are migrated to the new style clk driver - Rockchip rk3399,rk3066 PLL optimizations - i.MX LVDS display glitch fixes and AV PLL precision improvements - Qualcomm MSM8996 GPU GDSCs, hw controlled GDSCs, and Alpha PLL support - Explicit demodularization of always builtin drivers - Freescale Qoriq ls1012a and ls1046a support - Exynos 5433 parent typo fix and critical clock tagging - Renesas r8a7743/r8a7745 CPG - Renesas R-Car M3-W CSI2/VIN/SYS-DMAC/(H)SCIF/I2C/DRIF/gfx support - stm32f4* LSI, LSE, RTC, and QSPI clocks - pxa27x and pxa25x cpufreq as clks - TI omap36xx sprz319 advisory 2.1 workaround - Broadcom bcm2835 rate change propogation to PLLH_AUX from VEC -----BEGIN PGP SIGNATURE----- Version: GnuPG v2.0.22 (GNU/Linux) iQIcBAABCAAGBQJYT1GXAAoJEK0CiJfG5JUlQ1QP/iOaWnE8TBLK/lOKPte2rw8U 1rw2SDQ8gEJBGIVbZZsnOq6Pp1sVKrJ/7S9ybBeSHoOVb5iTCVAB4wG5uqdLLUGs 4cHj4Vtge7xSxPLCh6YzawS0SjbtbYp1KXHBygGB2COIF53zphkmuM74gZ+l3dcz TMkfbIvwm8ISvNjc7tRpjhzf6+XUTIVRJ6UZPMnir08lTmDqHz7mouY7nUxlbWOy lOlF725RoBSa4LcBt+nZcNZ7Cu8eajFneeE87YiLdM4aS/VYm1Ajs9KzZYIRM3R6 mznmiSDwCWTOzU4CsPSdcxGXePzyPrkDvRGWED2qHXNwWQ7Asbtm5pxDKEJ+rj8L LoB60z20d5PP0zJeiSwnr3XOgp95gW6vduAngu094O7FDZV7yY90wENIphQqgHaU 5nVEPYWTK3lrxAShadpHvnyZI5A621QbNYzAoCAM/jf5xa3JW+AbkERmO/RyEsTO s6gAKX9H4WiQsEHrmBpJ+VsVVmlT5fhCtqskohaEqFg9CaVaxXvTPzN2fO9KtbDC M6JPycE9qgu08TWTyJr9xGDGBh0mKP+7ffxpj1x1gVT59HmCLAGTMEvMuHAfKCfW vz6qPjWW4KnqwAY0JvDZy1y37YQMytA5PVidV/XsEM7WLnmbutTCEbmwIx8eUNGv NaEpc4l2hvKLwCo4w0J+ =RXZr -----END PGP SIGNATURE----- Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "This is a fairly quiet release. We don't have any patches to the core framework. The only patch that can even be considered "core" adds another clk_get() variant. The rest of the changes are in drivers for various SoCs, and we have a few bits for ARM shmobile architecture code (dts and mach) due to the dependency we're breaking between shmobile architecture code and its clk driver. Those shmobile bits have also been pulled into arm-soc tree. Here's the summary: Core: - Support for devm_get_clk_from_child() used with DT bindings that have subnodes with the 'clocks' property New Drivers: - Allwinner A64 (sun50i) - i.MX imx6ull - Socionext's UniPhier SoC CPUs - Mediatek MT2701 SoCs - Rockchip rk1108 SoCs - Qualcomm MSM8994/MSM8992 SoCS - Qualcomm RPM Clocks - Hisilicon Hi3516CV300 and Hi3798CV200 CRG - Oxford Semiconductor OX820 and OX810SE SoCs - Renesas RZ/G1M and RZ/GIE SoCs - Renesas R-Car RST driver for mode pin states Updates: - Four Allwinner SoCs are migrated to the new style clk driver - Rockchip rk3399,rk3066 PLL optimizations - i.MX LVDS display glitch fixes and AV PLL precision improvements - Qualcomm MSM8996 GPU GDSCs, hw controlled GDSCs, and Alpha PLL support - Explicit demodularization of always builtin drivers - Freescale Qoriq ls1012a and ls1046a support - Exynos 5433 parent typo fix and critical clock tagging - Renesas r8a7743/r8a7745 CPG - Renesas R-Car M3-W CSI2/VIN/SYS-DMAC/(H)SCIF/I2C/DRIF/gfx support - stm32f4* LSI, LSE, RTC, and QSPI clocks - pxa27x and pxa25x cpufreq as clks - TI omap36xx sprz319 advisory 2.1 workaround - Broadcom bcm2835 rate change propogation to PLLH_AUX from VEC" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (150 commits) clk: bcm: Fix 'maybe-uninitialized' warning in bcm2835_clock_choose_div_and_prate() clk: add devm_get_clk_from_child() API clk: st: clk-flexgen: Unmap region obtained by of_iomap clk: keystone: pll: Unmap region obtained by of_iomap clk:mmp:clk-of-mmp2: Free memory and Unmap region obtained by kzalloc and of_iomap clk:mmp:clk-of-pxa910: Free memory and Unmap region obtained by kzmalloc and of_iomap clk: mmp: clk-of-pxa1928: Free memory obtained by kzalloc clk: cdce925: Fix limit check clk: bcm: Make COMMON_CLK_IPROC into a library clk: qoriq: added ls1012a clock configuration clk: ti: dra7: fix "failed to lookup clock node gmac_gmii_ref_clk_div" boot message clk: bcm: Allow rate change propagation to PLLH_AUX on VEC clock clk: bcm: Support rate change propagation on bcm2835 clocks clk: bcm2835: Avoid overwriting the div info when disabling a pll_div clk clk: ti: omap36xx: Work around sprz319 advisory 2.1 clk: clk-wm831x: fix a logic error clk: uniphier: add cpufreq data for LD11, LD20 SoCs clk: uniphier: add CPU-gear change (cpufreq) support clk: qcom: Put venus core0/1 gdscs to hw control mode clk: qcom: gdsc: Add support for gdscs with HW control ... |
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.. | ||
allwinner,sunxi-clock-reset.txt | ||
amlogic,meson-reset.txt | ||
ath79-reset.txt | ||
berlin,reset.txt | ||
brcm,bcm63138-pmb.txt | ||
fsl,imx-src.txt | ||
hisilicon,hi6220-reset.txt | ||
img,pistachio-reset.txt | ||
nxp,lpc1850-rgu.txt | ||
oxnas,reset.txt | ||
renesas,rst.txt | ||
reset.txt | ||
sirf,rstc.txt | ||
socfpga-reset.txt | ||
st,sti-picophyreset.txt | ||
st,sti-powerdown.txt | ||
st,sti-softreset.txt | ||
st,stm32-rcc.txt | ||
ti-syscon-reset.txt | ||
uniphier-reset.txt | ||
zynq-reset.txt |