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reset: uniphier: rename MIO reset to SD reset for Pro5, PXs2, LD20 SoCs
I made a mistake as for naming for this block. The MIO block is not implemented for these 3 SoCs in the first place. The current naming will be a trouble if an SoC with both MIO and SD-ctrl blocks appear in the future. This driver has just been merged in the previous merge window. Rename it before the release. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
This commit is contained in:
Masahiro Yamada
parent
75924903c5
commit
19eb4a4722
@ -6,25 +6,25 @@ System reset
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Required properties:
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- compatible: should be one of the following:
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"socionext,uniphier-sld3-reset" - for PH1-sLD3 SoC.
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"socionext,uniphier-ld4-reset" - for PH1-LD4 SoC.
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"socionext,uniphier-pro4-reset" - for PH1-Pro4 SoC.
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"socionext,uniphier-sld8-reset" - for PH1-sLD8 SoC.
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"socionext,uniphier-pro5-reset" - for PH1-Pro5 SoC.
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"socionext,uniphier-pxs2-reset" - for ProXstream2/PH1-LD6b SoC.
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"socionext,uniphier-ld11-reset" - for PH1-LD11 SoC.
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"socionext,uniphier-ld20-reset" - for PH1-LD20 SoC.
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"socionext,uniphier-sld3-reset" - for sLD3 SoC.
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"socionext,uniphier-ld4-reset" - for LD4 SoC.
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"socionext,uniphier-pro4-reset" - for Pro4 SoC.
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"socionext,uniphier-sld8-reset" - for sLD8 SoC.
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"socionext,uniphier-pro5-reset" - for Pro5 SoC.
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"socionext,uniphier-pxs2-reset" - for PXs2/LD6b SoC.
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"socionext,uniphier-ld11-reset" - for LD11 SoC.
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"socionext,uniphier-ld20-reset" - for LD20 SoC.
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- #reset-cells: should be 1.
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Example:
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sysctrl@61840000 {
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compatible = "socionext,uniphier-ld20-sysctrl",
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compatible = "socionext,uniphier-ld11-sysctrl",
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"simple-mfd", "syscon";
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reg = <0x61840000 0x4000>;
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reset {
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compatible = "socionext,uniphier-ld20-reset";
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compatible = "socionext,uniphier-ld11-reset";
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#reset-cells = <1>;
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};
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@ -32,30 +32,30 @@ Example:
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};
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Media I/O (MIO) reset
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---------------------
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Media I/O (MIO) reset, SD reset
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-------------------------------
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Required properties:
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- compatible: should be one of the following:
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"socionext,uniphier-sld3-mio-reset" - for PH1-sLD3 SoC.
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"socionext,uniphier-ld4-mio-reset" - for PH1-LD4 SoC.
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"socionext,uniphier-pro4-mio-reset" - for PH1-Pro4 SoC.
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"socionext,uniphier-sld8-mio-reset" - for PH1-sLD8 SoC.
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"socionext,uniphier-pro5-mio-reset" - for PH1-Pro5 SoC.
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"socionext,uniphier-pxs2-mio-reset" - for ProXstream2/PH1-LD6b SoC.
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"socionext,uniphier-ld11-mio-reset" - for PH1-LD11 SoC.
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"socionext,uniphier-ld20-mio-reset" - for PH1-LD20 SoC.
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"socionext,uniphier-sld3-mio-reset" - for sLD3 SoC.
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"socionext,uniphier-ld4-mio-reset" - for LD4 SoC.
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"socionext,uniphier-pro4-mio-reset" - for Pro4 SoC.
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"socionext,uniphier-sld8-mio-reset" - for sLD8 SoC.
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"socionext,uniphier-pro5-sd-reset" - for Pro5 SoC.
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"socionext,uniphier-pxs2-sd-reset" - for PXs2/LD6b SoC.
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"socionext,uniphier-ld11-mio-reset" - for LD11 SoC.
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"socionext,uniphier-ld20-sd-reset" - for LD20 SoC.
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- #reset-cells: should be 1.
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Example:
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mioctrl@59810000 {
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compatible = "socionext,uniphier-ld20-mioctrl",
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compatible = "socionext,uniphier-ld11-mioctrl",
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"simple-mfd", "syscon";
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reg = <0x59810000 0x800>;
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reset {
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compatible = "socionext,uniphier-ld20-mio-reset";
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compatible = "socionext,uniphier-ld11-mio-reset";
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#reset-cells = <1>;
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};
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@ -68,24 +68,24 @@ Peripheral reset
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Required properties:
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- compatible: should be one of the following:
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"socionext,uniphier-ld4-peri-reset" - for PH1-LD4 SoC.
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"socionext,uniphier-pro4-peri-reset" - for PH1-Pro4 SoC.
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"socionext,uniphier-sld8-peri-reset" - for PH1-sLD8 SoC.
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"socionext,uniphier-pro5-peri-reset" - for PH1-Pro5 SoC.
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"socionext,uniphier-pxs2-peri-reset" - for ProXstream2/PH1-LD6b SoC.
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"socionext,uniphier-ld11-peri-reset" - for PH1-LD11 SoC.
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"socionext,uniphier-ld20-peri-reset" - for PH1-LD20 SoC.
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"socionext,uniphier-ld4-peri-reset" - for LD4 SoC.
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"socionext,uniphier-pro4-peri-reset" - for Pro4 SoC.
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"socionext,uniphier-sld8-peri-reset" - for sLD8 SoC.
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"socionext,uniphier-pro5-peri-reset" - for Pro5 SoC.
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"socionext,uniphier-pxs2-peri-reset" - for PXs2/LD6b SoC.
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"socionext,uniphier-ld11-peri-reset" - for LD11 SoC.
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"socionext,uniphier-ld20-peri-reset" - for LD20 SoC.
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- #reset-cells: should be 1.
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Example:
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perictrl@59820000 {
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compatible = "socionext,uniphier-ld20-perictrl",
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compatible = "socionext,uniphier-ld11-perictrl",
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"simple-mfd", "syscon";
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reg = <0x59820000 0x200>;
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reset {
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compatible = "socionext,uniphier-ld20-peri-reset";
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compatible = "socionext,uniphier-ld11-peri-reset";
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#reset-cells = <1>;
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};
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@ -154,7 +154,7 @@ const struct uniphier_reset_data uniphier_sld3_mio_reset_data[] = {
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UNIPHIER_RESET_END,
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};
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const struct uniphier_reset_data uniphier_pro5_mio_reset_data[] = {
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const struct uniphier_reset_data uniphier_pro5_sd_reset_data[] = {
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UNIPHIER_MIO_RESET_SD(0, 0),
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UNIPHIER_MIO_RESET_SD(1, 1),
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UNIPHIER_MIO_RESET_EMMC_HW_RESET(6, 1),
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@ -360,7 +360,7 @@ static const struct of_device_id uniphier_reset_match[] = {
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.compatible = "socionext,uniphier-ld20-reset",
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.data = uniphier_ld20_sys_reset_data,
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},
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/* Media I/O reset */
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/* Media I/O reset, SD reset */
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{
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.compatible = "socionext,uniphier-sld3-mio-reset",
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.data = uniphier_sld3_mio_reset_data,
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@ -378,20 +378,20 @@ static const struct of_device_id uniphier_reset_match[] = {
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.data = uniphier_sld3_mio_reset_data,
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},
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{
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.compatible = "socionext,uniphier-pro5-mio-reset",
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.data = uniphier_pro5_mio_reset_data,
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.compatible = "socionext,uniphier-pro5-sd-reset",
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.data = uniphier_pro5_sd_reset_data,
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},
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{
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.compatible = "socionext,uniphier-pxs2-mio-reset",
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.data = uniphier_pro5_mio_reset_data,
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.compatible = "socionext,uniphier-pxs2-sd-reset",
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.data = uniphier_pro5_sd_reset_data,
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},
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{
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.compatible = "socionext,uniphier-ld11-mio-reset",
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.data = uniphier_sld3_mio_reset_data,
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},
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{
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.compatible = "socionext,uniphier-ld20-mio-reset",
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.data = uniphier_pro5_mio_reset_data,
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.compatible = "socionext,uniphier-ld20-sd-reset",
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.data = uniphier_pro5_sd_reset_data,
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},
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/* Peripheral reset */
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{
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