mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-17 06:57:10 +07:00
1e9e2622a1
ICR and TSCDEADLINE MSRs write cause the main MSRs write vmexits in our product observation, multicast IPIs are not as common as unicast IPI like RESCHEDULE_VECTOR and CALL_FUNCTION_SINGLE_VECTOR etc. This patch introduce a mechanism to handle certain performance-critical WRMSRs in a very early stage of KVM VMExit handler. This mechanism is specifically used for accelerating writes to x2APIC ICR that attempt to send a virtual IPI with physical destination-mode, fixed delivery-mode and single target. Which was found as one of the main causes of VMExits for Linux workloads. The reason this mechanism significantly reduce the latency of such virtual IPIs is by sending the physical IPI to the target vCPU in a very early stage of KVM VMExit handler, before host interrupts are enabled and before expensive operations such as reacquiring KVM’s SRCU lock. Latency is reduced even more when KVM is able to use APICv posted-interrupt mechanism (which allows to deliver the virtual IPI directly to target vCPU without the need to kick it to host). Testing on Xeon Skylake server: The virtual IPI latency from sender send to receiver receive reduces more than 200+ cpu cycles. Reviewed-by: Liran Alon <liran.alon@oracle.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Radim Krčmář <rkrcmar@redhat.com> Cc: Sean Christopherson <sean.j.christopherson@intel.com> Cc: Vitaly Kuznetsov <vkuznets@redhat.com> Cc: Liran Alon <liran.alon@oracle.com> Signed-off-by: Wanpeng Li <wanpengli@tencent.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
377 lines
9.0 KiB
C
377 lines
9.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef ARCH_X86_KVM_X86_H
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#define ARCH_X86_KVM_X86_H
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#include <linux/kvm_host.h>
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#include <asm/pvclock.h>
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#include "kvm_cache_regs.h"
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#define KVM_DEFAULT_PLE_GAP 128
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#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
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#define KVM_DEFAULT_PLE_WINDOW_GROW 2
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#define KVM_DEFAULT_PLE_WINDOW_SHRINK 0
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#define KVM_VMX_DEFAULT_PLE_WINDOW_MAX UINT_MAX
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#define KVM_SVM_DEFAULT_PLE_WINDOW_MAX USHRT_MAX
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#define KVM_SVM_DEFAULT_PLE_WINDOW 3000
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static inline unsigned int __grow_ple_window(unsigned int val,
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unsigned int base, unsigned int modifier, unsigned int max)
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{
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u64 ret = val;
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if (modifier < 1)
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return base;
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if (modifier < base)
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ret *= modifier;
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else
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ret += modifier;
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return min(ret, (u64)max);
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}
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static inline unsigned int __shrink_ple_window(unsigned int val,
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unsigned int base, unsigned int modifier, unsigned int min)
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{
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if (modifier < 1)
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return base;
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if (modifier < base)
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val /= modifier;
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else
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val -= modifier;
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return max(val, min);
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}
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#define MSR_IA32_CR_PAT_DEFAULT 0x0007040600070406ULL
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static inline void kvm_clear_exception_queue(struct kvm_vcpu *vcpu)
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{
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vcpu->arch.exception.pending = false;
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vcpu->arch.exception.injected = false;
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}
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static inline void kvm_queue_interrupt(struct kvm_vcpu *vcpu, u8 vector,
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bool soft)
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{
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vcpu->arch.interrupt.injected = true;
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vcpu->arch.interrupt.soft = soft;
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vcpu->arch.interrupt.nr = vector;
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}
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static inline void kvm_clear_interrupt_queue(struct kvm_vcpu *vcpu)
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{
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vcpu->arch.interrupt.injected = false;
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}
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static inline bool kvm_event_needs_reinjection(struct kvm_vcpu *vcpu)
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{
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return vcpu->arch.exception.injected || vcpu->arch.interrupt.injected ||
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vcpu->arch.nmi_injected;
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}
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static inline bool kvm_exception_is_soft(unsigned int nr)
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{
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return (nr == BP_VECTOR) || (nr == OF_VECTOR);
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}
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static inline bool is_protmode(struct kvm_vcpu *vcpu)
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{
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return kvm_read_cr0_bits(vcpu, X86_CR0_PE);
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}
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static inline int is_long_mode(struct kvm_vcpu *vcpu)
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{
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#ifdef CONFIG_X86_64
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return vcpu->arch.efer & EFER_LMA;
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#else
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return 0;
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#endif
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}
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static inline bool is_64_bit_mode(struct kvm_vcpu *vcpu)
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{
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int cs_db, cs_l;
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if (!is_long_mode(vcpu))
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return false;
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kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
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return cs_l;
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}
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static inline bool is_la57_mode(struct kvm_vcpu *vcpu)
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{
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#ifdef CONFIG_X86_64
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return (vcpu->arch.efer & EFER_LMA) &&
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kvm_read_cr4_bits(vcpu, X86_CR4_LA57);
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#else
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return 0;
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#endif
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}
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static inline bool x86_exception_has_error_code(unsigned int vector)
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{
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static u32 exception_has_error_code = BIT(DF_VECTOR) | BIT(TS_VECTOR) |
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BIT(NP_VECTOR) | BIT(SS_VECTOR) | BIT(GP_VECTOR) |
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BIT(PF_VECTOR) | BIT(AC_VECTOR);
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return (1U << vector) & exception_has_error_code;
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}
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static inline bool mmu_is_nested(struct kvm_vcpu *vcpu)
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{
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return vcpu->arch.walk_mmu == &vcpu->arch.nested_mmu;
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}
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static inline int is_pae(struct kvm_vcpu *vcpu)
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{
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return kvm_read_cr4_bits(vcpu, X86_CR4_PAE);
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}
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static inline int is_pse(struct kvm_vcpu *vcpu)
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{
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return kvm_read_cr4_bits(vcpu, X86_CR4_PSE);
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}
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static inline int is_paging(struct kvm_vcpu *vcpu)
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{
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return likely(kvm_read_cr0_bits(vcpu, X86_CR0_PG));
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}
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static inline bool is_pae_paging(struct kvm_vcpu *vcpu)
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{
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return !is_long_mode(vcpu) && is_pae(vcpu) && is_paging(vcpu);
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}
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static inline u32 bit(int bitno)
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{
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return 1 << (bitno & 31);
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}
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static inline u8 vcpu_virt_addr_bits(struct kvm_vcpu *vcpu)
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{
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return kvm_read_cr4_bits(vcpu, X86_CR4_LA57) ? 57 : 48;
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}
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static inline u8 ctxt_virt_addr_bits(struct x86_emulate_ctxt *ctxt)
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{
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return (ctxt->ops->get_cr(ctxt, 4) & X86_CR4_LA57) ? 57 : 48;
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}
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static inline u64 get_canonical(u64 la, u8 vaddr_bits)
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{
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return ((int64_t)la << (64 - vaddr_bits)) >> (64 - vaddr_bits);
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}
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static inline bool is_noncanonical_address(u64 la, struct kvm_vcpu *vcpu)
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{
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#ifdef CONFIG_X86_64
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return get_canonical(la, vcpu_virt_addr_bits(vcpu)) != la;
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#else
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return false;
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#endif
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}
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static inline bool emul_is_noncanonical_address(u64 la,
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struct x86_emulate_ctxt *ctxt)
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{
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#ifdef CONFIG_X86_64
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return get_canonical(la, ctxt_virt_addr_bits(ctxt)) != la;
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#else
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return false;
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#endif
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}
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static inline void vcpu_cache_mmio_info(struct kvm_vcpu *vcpu,
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gva_t gva, gfn_t gfn, unsigned access)
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{
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u64 gen = kvm_memslots(vcpu->kvm)->generation;
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if (unlikely(gen & KVM_MEMSLOT_GEN_UPDATE_IN_PROGRESS))
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return;
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/*
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* If this is a shadow nested page table, the "GVA" is
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* actually a nGPA.
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*/
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vcpu->arch.mmio_gva = mmu_is_nested(vcpu) ? 0 : gva & PAGE_MASK;
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vcpu->arch.mmio_access = access;
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vcpu->arch.mmio_gfn = gfn;
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vcpu->arch.mmio_gen = gen;
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}
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static inline bool vcpu_match_mmio_gen(struct kvm_vcpu *vcpu)
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{
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return vcpu->arch.mmio_gen == kvm_memslots(vcpu->kvm)->generation;
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}
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/*
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* Clear the mmio cache info for the given gva. If gva is MMIO_GVA_ANY, we
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* clear all mmio cache info.
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*/
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#define MMIO_GVA_ANY (~(gva_t)0)
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static inline void vcpu_clear_mmio_info(struct kvm_vcpu *vcpu, gva_t gva)
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{
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if (gva != MMIO_GVA_ANY && vcpu->arch.mmio_gva != (gva & PAGE_MASK))
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return;
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vcpu->arch.mmio_gva = 0;
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}
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static inline bool vcpu_match_mmio_gva(struct kvm_vcpu *vcpu, unsigned long gva)
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{
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if (vcpu_match_mmio_gen(vcpu) && vcpu->arch.mmio_gva &&
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vcpu->arch.mmio_gva == (gva & PAGE_MASK))
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return true;
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return false;
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}
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static inline bool vcpu_match_mmio_gpa(struct kvm_vcpu *vcpu, gpa_t gpa)
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{
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if (vcpu_match_mmio_gen(vcpu) && vcpu->arch.mmio_gfn &&
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vcpu->arch.mmio_gfn == gpa >> PAGE_SHIFT)
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return true;
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return false;
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}
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static inline unsigned long kvm_register_readl(struct kvm_vcpu *vcpu, int reg)
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{
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unsigned long val = kvm_register_read(vcpu, reg);
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return is_64_bit_mode(vcpu) ? val : (u32)val;
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}
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static inline void kvm_register_writel(struct kvm_vcpu *vcpu,
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int reg, unsigned long val)
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{
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if (!is_64_bit_mode(vcpu))
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val = (u32)val;
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return kvm_register_write(vcpu, reg, val);
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}
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static inline bool kvm_check_has_quirk(struct kvm *kvm, u64 quirk)
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{
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return !(kvm->arch.disabled_quirks & quirk);
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}
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static inline bool kvm_vcpu_latch_init(struct kvm_vcpu *vcpu)
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{
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return is_smm(vcpu) || kvm_x86_ops->apic_init_signal_blocked(vcpu);
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}
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void kvm_set_pending_timer(struct kvm_vcpu *vcpu);
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void kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip);
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void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr);
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u64 get_kvmclock_ns(struct kvm *kvm);
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int kvm_read_guest_virt(struct kvm_vcpu *vcpu,
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gva_t addr, void *val, unsigned int bytes,
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struct x86_exception *exception);
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int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu,
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gva_t addr, void *val, unsigned int bytes,
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struct x86_exception *exception);
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int handle_ud(struct kvm_vcpu *vcpu);
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void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu);
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void kvm_vcpu_mtrr_init(struct kvm_vcpu *vcpu);
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u8 kvm_mtrr_get_guest_memory_type(struct kvm_vcpu *vcpu, gfn_t gfn);
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bool kvm_mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data);
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int kvm_mtrr_set_msr(struct kvm_vcpu *vcpu, u32 msr, u64 data);
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int kvm_mtrr_get_msr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata);
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bool kvm_mtrr_check_gfn_range_consistency(struct kvm_vcpu *vcpu, gfn_t gfn,
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int page_num);
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bool kvm_vector_hashing_enabled(void);
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int x86_emulate_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
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int emulation_type, void *insn, int insn_len);
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enum exit_fastpath_completion handle_fastpath_set_msr_irqoff(struct kvm_vcpu *vcpu);
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#define KVM_SUPPORTED_XCR0 (XFEATURE_MASK_FP | XFEATURE_MASK_SSE \
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| XFEATURE_MASK_YMM | XFEATURE_MASK_BNDREGS \
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| XFEATURE_MASK_BNDCSR | XFEATURE_MASK_AVX512 \
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| XFEATURE_MASK_PKRU)
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extern u64 host_xcr0;
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extern u64 kvm_supported_xcr0(void);
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extern unsigned int min_timer_period_us;
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extern bool enable_vmware_backdoor;
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extern int pi_inject_timer;
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extern struct static_key kvm_no_apic_vcpu;
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static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
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{
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return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
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vcpu->arch.virtual_tsc_shift);
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}
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/* Same "calling convention" as do_div:
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* - divide (n << 32) by base
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* - put result in n
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* - return remainder
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*/
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#define do_shl32_div32(n, base) \
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({ \
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u32 __quot, __rem; \
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asm("divl %2" : "=a" (__quot), "=d" (__rem) \
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: "rm" (base), "0" (0), "1" ((u32) n)); \
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n = __quot; \
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__rem; \
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})
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static inline bool kvm_mwait_in_guest(struct kvm *kvm)
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{
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return kvm->arch.mwait_in_guest;
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}
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static inline bool kvm_hlt_in_guest(struct kvm *kvm)
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{
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return kvm->arch.hlt_in_guest;
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}
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static inline bool kvm_pause_in_guest(struct kvm *kvm)
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{
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return kvm->arch.pause_in_guest;
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}
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static inline bool kvm_cstate_in_guest(struct kvm *kvm)
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{
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return kvm->arch.cstate_in_guest;
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}
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DECLARE_PER_CPU(struct kvm_vcpu *, current_vcpu);
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static inline void kvm_before_interrupt(struct kvm_vcpu *vcpu)
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{
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__this_cpu_write(current_vcpu, vcpu);
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}
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static inline void kvm_after_interrupt(struct kvm_vcpu *vcpu)
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{
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__this_cpu_write(current_vcpu, NULL);
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}
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static inline bool kvm_pat_valid(u64 data)
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{
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if (data & 0xF8F8F8F8F8F8F8F8ull)
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return false;
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/* 0, 1, 4, 5, 6, 7 are valid values. */
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return (data | ((data & 0x0202020202020202ull) << 1)) == data;
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}
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void kvm_load_guest_xsave_state(struct kvm_vcpu *vcpu);
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void kvm_load_host_xsave_state(struct kvm_vcpu *vcpu);
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#endif
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