Eric Yang a7f90cbc0e drm/amd/display: Move CLK_BASE_INNER macro ... This macro is specificly used by RV1. Move it to the appropriate location. Signed-off-by: Eric Yang <Eric.Yang2@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2019-05-31 10:39:30 -05:00
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hw	drm/amd/display: Move CLK_BASE_INNER macro	2019-05-31 10:39:30 -05:00
bw_fixed.h	drm/amd/display: explicit uint64_t casting	2018-11-05 14:20:50 -05:00
clock_source.h	drm/amd/display: Keep clocks high before seamless boot done	2019-03-19 15:04:03 -05:00
compressor.h	drm/amd/display: fbc state could not reach while enable fbc	2018-11-30 12:02:35 -05:00
core_status.h	drm/amd/display: return correct dc_status for dcn10_validate_global	2019-04-10 13:53:28 -05:00
core_types.h	drm/amd/display: make clk mgr soc specific	2019-05-31 10:39:29 -05:00
custom_float.h	drm/amd/display: Enable regamma 25 segments and use double buffer.	2017-09-26 17:14:18 -04:00
dc_link_ddc.h	drm/amd/display: Respect aux return values	2019-03-19 15:04:02 -05:00
dc_link_dp.h	drm/amd/display: Retry link training again	2018-07-27 09:07:42 -05:00
dce_calcs.h	drm/amdgpu/display: remove VEGAM config option	2018-05-18 16:08:18 -05:00
dcn_calcs.h	drm/amd/display: make clk mgr soc specific	2019-05-31 10:39:29 -05:00
hw_sequencer.h	drm/amd/display: Expose send immediate sdp message interface	2019-05-24 12:20:50 -05:00
link_hwss.h	drm/amd/display: add eDP 1.2+ polling for T7	2018-02-19 14:19:34 -05:00
reg_helper.h	drm/amd/display: Combine field toggle macro and sequence write macro.	2019-03-19 15:36:49 -05:00
resource.h	drm/amd/display: make clk mgr soc specific	2019-05-31 10:39:29 -05:00
vm_helper.h	drm/amd/display: DC VM Fixes	2019-02-06 13:30:12 -05:00